Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral forProcessing Direct Electrical Networks Measurements

J. Viejo, M.J. Bellido, A. Millan, E. Ostua, J. Juan, P. Ruiz-de-Clavijo and D. GuerreroDepartamento de Tecnologia Electronica - Universidad de Sevilla

Av. Reina Mercedes, s/n (E. T. S. Ingenieria Informatica) - 41012 Sevilla{julian, bellido, amillan, ostua, jjchico, paulino, guerre} dte.us.es

Tel.: +34 954556160 - Fax: +34 954552764http://www.dte.us.es/gtm/

Abstract

This contribution successfully accomplished thedesign and implementation of an advanced DSP circuitfor direct measurements of electrical networkparameters (RMS and real and reactive power) withapplication to network monitoring and qualityassurance.

The device is implemented on a mid-range XilinxSpartan-3 family FPGA and includes an OPB interfaceso that it can be integrated as a standardperipheral ofamicroprocessor system like the MicroBlaze. Specialattention has been paid to resources optimization andaccuracy with simulated error below l%.

1. Introduction

The technological development has given rise to sucha significant increase of the integration density that it iscausing more and more parts of a complete system to beincluded inside the main core, constituted by a singlechip. This chip has been traditionally referred to asIntegrated Circuit, but new terms like Integrated Systemor System on Chip (SoC) have become popular becausethey better express the fact that the chip can contain notonly a part of the system but the whole system itself.

Most of the times, a SoC structure includes amicroprocessor as a central core in charge of the controlof the system, and a set of general purpose and/orcustom peripherals that carry out different operations:co-processing, display control, communication, etc. SoCclearly fulfils the demand for more compact, function-rich and portable appliances that has become so popular,like multimedia-enabled cellular phones, tiny multimediaplayers, pocket computers, etc. In fact, SoC design iscurrently the most relevant methodology for the designof a wide range of embedded systems.

SoC designs are commonly built out of alreadyavailable parts in the form of IP-cores: microprocessors,memory blocks, Ethernet controllers, standard input-

output devices, etc; so that SoC designers typically do awork of integrations of already available parts anddesign of specific functions and glue logic. This schemeimproves re-usability and reduce the time to market andtotal costs.

The advance in technology has also made possible toproduce better programmable circuits (FPGAs) withincreased performance and higher integration densities.FPGAs offer the highest flexibility and costeffectiveness because hardware implementation can bedone several times on the same chip at no additional costand because mass productions ofFPGA chips has lead tovery competitive prices. Today, full systems may beimplemented in mid-range FPGAs from several vendors[1, 2] that can allocate 1,5X 106 equivalent gates workingat 100MHz or more (Spartan-3 XC3S1500 FPGA [3]).FPGA vendors also provide high level developmenttools where the designer typically works by assemblinghigh level configurable building blocks from a libraryand designing custom parts through a HardwareDescription Language (Verilog, VHDL, etc.) [4, 5].

This makes FPGAs an ideal platform to implementSoC where flexibility, re-usability, development cost andtime to market is improved by an order of magnitudewhen compared to the traditional ASIC design path. Thismethodology, widely known as System on aProgrammable Chip (SoPC) is rapidly gainingacceptance as technology produces more powerfulFPGA chips widening the range of possible applications.With this in mind, FPGA vendors offer some chips thatintegrate processor cores and memory in the FPGA,focusing at processor-driven applications, thus leavingplenty resources for custom modules or soft IP cores. Onthe side of the tools, development platforms usuallyprovide and integrates both hardware and softwaredesign and test for the convenience of the systemdesigner.

This work is part of the OpenRTU project (seesection 7) which main objective is the implementation offlexible embedded system to be used as a technologycore for Remote Terminal Units (RTU) with applicationin industrial control systems. Most of these units are

1-4244-0777-X/06/$20.00 §2006 IEEE

customized for a particular application despite they mayshare most of the functionality, so the ability to re-usethe building blocks from a previous implementation andthe possibility of timely and predictable production ofvariants at a low cost is mandatory. For these reason theimplementation of the system as a SoPC seems the mostappropriate solution. The system is based on amicroprocessor and a set of optional devices connectedto the internal bus that provide various processing andcommunication capabilities: LAN, wireless, signalprocessing, etc. But the most important technologychallenge of the project is to include in the same device aDigital Signal Processor (DSP) for direct measurementand real-time processing of electrical networkparameters. In this paper, the design and implementationdetails of this DSP are presented. The overall objective isto provide a much improved alternative to the currentsolution in which a RTU consists of a set of generalpurpose DSPs mounted on a board, which implement therequired functionality. The board is then connected to acomputer running a controlling software. The newsystem will drastically improve the solution in all thesenses: physical allocation, power consumption,performance, robustness and cost, since most of thehardware is now included in a single FPGA chip.

The designed DSP is able to process electricalnetwork parameters in real time, which involvescomplex operations like filtering, multiplications andsquare root calculations. As a result, it provides acontinuous flow of high level calibrated and filtered datalike instant current and voltage, active and reactivepower, etc. that can then be used in a variety ofapplications like quality assurance or networkmonitoring. Moreover, the DSP is implemented as astandard peripheral connected to the standard OPB busand is included in a peripheral library, so that its use inother designs is straightforward.

In order to optimize the implementation of such adevice in hardware, two different design methodologieshave been explored: direct VHDL coding and use ofsystem level tools provided by the programmable devicefoundry, it is System Generator for DSP [6] from Xilinx,since Xilinx Spartan-3 FPGAs were selected toimplement the hardware platform. The use of system-level tools resulted in a much more productive, resource-efficient and produced better performance do to thevariety of fully parametrizable building blocks availablein the library and the fact that these blocks are highlyoptimized for the target programmable chip. Then, it isthis methodology that is described in this work.

The rest of the paper is organized as follows: in thenext section, the system tools used to develop the DSPdevice will be described. In section 3, DSP specificationswill be presented. In the fourth section, the mostimportant details of the design are discussed. The fifthsection is dedicated to presenting the main results both

from simulation and implementation. Finally, someconclusions will be derived.

2. Design and implementation methodology

As it has been mentioned previously, it was decidedto address the design of the system using the new toolsdeveloped by Xilinx to facilitate the design andimplementation of DSPs on its FPGAs: SystemGenerator for DSP [6] and EDK [7].

System Generator for DSP is a software platform,integrated within M\ATLAB and Simulink [8] tools fromThe MathWorks, that allows for the design of DSPsystems using The Xilinx BlockSet [9, 10]. SystemGenerator also handles the automatic generation ofperipherals for MicroBlaze [11], synthesizable on XilinxFPGAs. The typical methodology for digital systemdesign has been followed, based on a control unitimplemented in VHDL code and a data path built out ofSystem Generator's building blocks. The different toolsused in the methodology followed for the design of theDSP peripheral are shown in Fig. 1. Most of the systemsimulation is carried out using Simulink; however,Mentor Graphics tool ModelSim [12] has been used tosimulate VHDL code (HDL Co-simulation). Synthesisand implementation of the system on FPGA have beendone using the Xilinx Platform Studio for embeddedsystems (XPS) integrated within the EmbeddedDevelopment Kit (EDK).

Fig. 1: Environment and tools used.

3. System specifications

With regard to the specifications, the designed DSPperipheral carries out digital processing tasks on eightanalog inputs (Al) which are acquired through anexternal Analog Front-End (AFE). These signals comefrom a system of three-phase measurement transformers(voltages and/or currents in power lines: R, S, T phasesand neuter).

The eight analog inputs are subjected to a series ofconfigurable treatments. Different sampling frequencies,gain control or offset elimination can be configured.Different sampling rates are determined by two setupbits: TADC and C50/60, so that it is possible to sampleat 64 or 128 samples by cycle of the electrical signal;this is equivalent to sampling frequencies of 3200 Hz (64s/c) or 6400 Hz (128 s/c) for 50 Hz input signals and of3840 Hz (64 s/c) or 7680 Hz (128 s/c) for 60 Hz inputsignals.A diagram of the modules that form the DSP

peripheral is shown in Fig. 2. We can clearly distinguishthree parts: AFE Interface, OPB Interface and DirectMeasurements Processing. Next, we will briefly explainthe functionality of each one of these subsystems.

The AFE Interface module carries out the twofollowing functions: A/D Conversion Control that is incharge of controlling the sampling frequency of theexternal ADC converters and capturing the digitizedanalog inputs, coming from these converters; and GainControl applies to each analog input.

The OPB Interface module establishes the connectionof the peripheral with the On-chip Peripheral Bus (OPB),allowing the communication and the interchange ofinformation between MicroBlaze and the designed DSP.MicroBlaze and the Al peripheral exchange informationin two ways: sending of configuration parameters fromMicroBlaze to the peripheral (write operation of thesetup registers) and relay of calculated data from theperipheral to MicroBlaze (read operation of thecalculated parameters). Configuration parameters thatthis peripheral handles refer to control registers andcalibration factors.

The Direct Measurements Processing module is incharge of processing the signals acquired by the A/Dconversion module. The group of subsystems that formthis module are: FIR filter, offset control, instantaneousvalues, average and calibration.

The FIR filter module filters the eight analog inputs.Specifically, the implemented filter is a linear low-passFIR filter that eliminates high-frequency components.

The offset control function calculates the DCcomponent of each filtered signal using the followingequation:

1 N-1

DCi(n = N,xi(no -n)(1

Nn=Owhere DC1(no) is the offset value calculated in the

instant for the input signal i, N is the number of samplesby cycle and xi is the filtered input signal i.

These calculated data will be used in theinstantaneous values subsystem. The instantaneousvalues subsystem calculates root mean square values(RMS) and real and reactive power associated to eachanalog input. RMS values are calculated as follows:

X7IS (nO ) = (2)

where Xjms(no) is the RMS value of the input signal iin the instant no.

Real (Pij(no)) and reactive (Qij(no)) power are givenby:

1 N-1

Pili(no )=Ni xi(no - n)x xi(no - n) (3)

IN1 'K (3NQi j (no)::: N xi (no n)xxi no -(-n (4)

Nn=\OI O 4 )mdN)lwhere i,j indexes are selected so that xi and xj

correspond to voltage and current signals of the samephase, respectively.

Finally, AC power can be obtained by subtracting theDC component:

acjj(no)= Pi (no)-DCi(no)x DC (no) (5)

gnalo Input OPB InterfacePeripheral _

Co>ntrol CaiouihlaedBParamerem Data

AFE Control Cortrol Unit Sgiraece sigrls DS EA Da Path. .P ~~~~DSPEA

AnalaS _ _Inputs

Direct MeasurementtProcessirg

Fig. 2: DSP peripheral designed.

Qac(no) = Qij (no)- DCi(no)x DCj (no) (6)Parameters calculated by the two previous subsystems

are average values, the average period being one cycle ofthe electrical signal. For the estimation of reactive powerthe approximation that the input signal is sinusoidal andstationary has been used, so that the derivative of thecurrent signal is the same signal shifted 3N/4 samples.

The purpose of the average modules is to calculate theaverage of instantaneous values over a number of signalcycles determined by the NCP configuration parameter.

Finally, the average instantaneous parameters must becalibrated. The calibration subsystem does two

operations: the first one is the correction of distortions ofthe board and the second one is the correction of externaldistortions. Calibration parameters are available throughconfiguration registers. Calibrated average values are

made available to the MicroBlaze processor through theOPB interface as depicted in Fig. 2.

4. System design and implementation

In this section, the most important aspects of designand implementation are commented.

The AFE Interface subsystem has been designedaccording to the datasheets of the external systems we

have to interface to, AD7656 converter [13] andAD5233 digital potentiometer [14], by using a VHDLbehavioral description. The OPB Interface has beenmodeled using the Xilinx BlockSet, just as it is describedin [11].

To design the Direct Measurements Processingsubsystem, we have modeled a data path using SystemGenerator blocks, together with a VHDL control unitthat is in charge of controlling the processing of the eightanalog inputs.

In the design of this DSP peripheral, a great effort hasbeen made to optimize both FPGA resources andoperation frequency.

In order to optimize resources, it has been takenadvantage of the fact that operation frequency is muchhigher than Al sampling frequency (75-1OOMHz versus

3200-7680Hz). This feature allows us to have a lot ofclock cycles at our disposal between two consecutivecaptures.

Fig. 3: Processing algorithm.

Thus, the suggested approach consists on designing a

data path that uses the same processing elements forevery input (multipliers, adders, etc.) in series. Thecontrol unit is in charge of arbitrating the processing,establishing the input that is processed in each moment.A general algorithm of the functionality that implementsthe control unit is shown in Fig. 3.

In this behavioral description, two counters have beendeclared: samples and average_cycles which will countthe number of processed samples and average cycles,respectively, and two registers: limit samples andlimit_average_cycles. The first one will be initiated to 64or 128 samples according to the TADC bit, and thesecond to 2NCP. Moreover, a set of accumulators havebeen defined: ACDC, ACRms, ACP and ACQ. Theseaccumulators will store the average values of thefunctions: offset control (7), RMS value (8), real power

(9) and reactive power (10).N-1

ACDc(no) = xi(no -n)n=O

N-1

AC,,, (no) = Xi(n-n)n=O

N-1

AC,(no) = xi(no - n)x xi(no - n)n=O

(7)

(8)

(9)

ACQ (no) xi (no n)xxj n0 - --n (10)n=O modN)

In the following lines, the most outstandingimplementation details will be commented.

First, FIR filter design and coefficient calculationhave been carried out using FDATool, a MATLABpackage [10]. FDATool features an advanced interfacethat allows the design to define filter type, filter order,pass and stop frequencies, passband ripple, stopbandattenuation, etc. The System Generator FIR block hasbeen used for the filter implementation, providing a greatvariety of implementation options: filter coefficients(those generated by FDATool), number of bits per

coefficient (16 bits), entry number of channels (eightchannels), processing type (serial input) and latency (10cycles).

In order to implement offset control, RMS, real andreactive power subsystems, a data path where all inputsshare the same resources has been modeled. Thus,multiplexing logic has been added to select the inputchannel that will be processed.

System Generator's CORDIC SQRT block has beenused to implement square root operation. This block hasbeen modified so that negative inputs produce zero as

result, which is part of the system specifications.System Generator facilitates DSP design and

verification [10], reducing the design time andsimplifying the exploration of the design space.

Therefore, the challenge is to improve hardware area and

ACDC=O, ACRms=O, ACp=O, ACQ=O.for each sampling period do

capture_and_filter analog_inputs(;process analog-inputs(;update accumulators(ACDc, ACRms, ACp, ACQ);if(samples=limit samples-]) then

--One electrical signal cycle has been processedcalculate_instantaneous-values(;average instantaneous-values(;if(average cycles=limit_average cycles-]) then

--2NCP cycles have been processedcalibrate_instantaneous-values(;average cycles=O;

elseaverage cycles=average cycles+1;

end if,samples=0;

elsesamples=samples+1;

end if;end for each;

speed while producing acceptable results. To do this, aswell as optimizing the hardware architecture to suit theideal algorithm [15], a number of options are available:using on-chip resources (embedded multipliers, BRAMs,etc.) and configuring System Generator blocks [9, 10]:arithmetic type, precision, latency, overflow,quantization, etc. By using these options the systemfunctional behavior is not affected only the precision andoverall performance.

Taking account of these two last alternatives, twoversions of the peripheral have been developed: 1.0 and1.2. In the first version, all intermediate operations arecarried out using 32 bits fixed-point arithmetic. Inversion 1.2, the design has been modeled using 16 bitsfixed-point arithmetic. Besides, operations whichproduce 32 bits results are rounded to 16 bits.

System Generator's blocks may also be configuredfor frequency optimization, by adding pipeline stagesand latency in the different data path components:multipliers, adders, etc. However, these modificationsaffect the system behavior, making it necessary tomodify the control unit so that it behaves properly.

Once system requirements are fulfilled and checkedby simulation at the block level, the two versions of theDSP peripheral are generated and imported into an EDKproject for later integration with the MicroBlazeprocessor provided by Xilinx. OPB_Export_Tool [11]carries out these tasks.

5. Results

In this section, simulation and hardwareimplementation results are described in some detail.

5.1. Simulation resultsTo check that the design fulfills the specifications

Simulink and ModelSim tools have been used together(HDL Co-simulation) for system simulation. This kindof simulation is mandatory in order to take account ofblocks that are only available as black boxes.A wide range of system configurations have been

simulated: different sampling rates, NCP, amplitudes,offset, etc., getting a correct operation in all the cases.A simulation example that corresponds to the

following configuration is shown in Fig. 4:1. Sampling frequency fixed to 7680 Hz.2. Value ofNCP fixed to 0.3. Offset elimination option enabled.For the generation of the input stimuli to the system,

the Sources Blockset of Simulink has been used. Asample input signal is formed by the sum of twosinusoids with frequencies of 60 and 3200 Hz,amplitudes of 0.5 and 0.1 and offset of 0.01 and 0,respectively. This way we will be able to check thelittering stage where the smaller component at 3200 Hzshould be filtered.

Fig. 4: Simulation results. (a) Input signal.(b) Filtered input signal. (c) DC acumulatoroutput. (d) RMS acumulator output. (e)Real power acumulator output. (f) Reactivepower acumulator output.

Once the simulation begins, the analogue-to-digitalconversion control subsystem samples the generatedinput signals (see Fig. 4a). In Fig. 4a, the blue signal isthe voltage and the red signal is the current. Both signalsare out ofphase Kt/6 rad.

As it can be observed in Fig. 4b-4e and mainly inFig. 4f, a transitory phase exists during the first cycle ofthe input signal. From the second cycle on, when theprocessing of each cycle concludes, valid and updateddata of the different calculated parameters are obtained:offset, RMS values and real and reactive power.

For the offset and RMS values calculation the filteredsignal is used (Fig. 4b). The signals in Fig. 4c-4f showthe outputs of the accumulators ACDC, ACRms, ACP andACQ, respectively, which store inter-cycle transitoryvalues of the parameters being processed. When a cycleof the input signal is completed, the accumulated valuesin that instant are used to calculate the offset, the RMSvalue and real and reactive power corresponding to thatcycle, according to equations (1) to (6).

In Table 1 the obtained simulation results are shownfor each implemented peripheral, as well as thetheoretical values calculated for those functions.Comparing the results obtained by the peripherals we

realize that they are identical. Accuracy of both DSPimplementations for RMS values calculated are typicallyunder 1% of the exact theoretical value whereasaccuracy for real and reactive power are under 10%o.

5.2. Hardware implementation resultsIn order to compare the implementations of the two

versions of the peripheral, they have been synthesizedseparately using XPS from Xilinx [7]. Some figures ofmerit will be analyzed in this section: used hardwareresources and maximum frequency of operation.

Both designs have been implemented on a Spartan-3XC3S1500 FPGA. These devices have all the featuresrequired for efficiently implementing DSP functions:Embedded 18x18 Multipliers, Distributed RAM, ShiftRegister Logic, etc [15]. In short, these features allow forthe implementation of high-performance DSP functionsin a small fraction of the total device. XC3S1500 devicefeatures about 1,5X 106 equivalent gates, 32 multipliersand 32 BRAM and is in the moderate to low capacityrange of the Spartan-3 family.

The hardware implementation results show that theversion 1.0 of the peripheral occupies 5181 slices (38%of a XC3S1500 FPGA) and 6 embedded multiplierswhereas the version 1.2 only uses 4232 slices (310%) andhalf of the embedded multipliers, leaving plenty ofavailable resources for implementing the MicroBlazeprocessor and additional circuitry (see Table 2).

Finally, we observe that frequency optimization haveprovided a maximum frequency of 110.461MHz whicheasily meet the initial 75-100 MHz requirements.

6. Conclusions

An advanced DSP for direct electrical measurementshas been successfully designed and implemented on a

Xilinx Spartan-3 FPGA. The DSP takes the form of a

standard OPB peripheral so that it can be managed by a

system processor implemented in the same FPGA likethe MicroBlaze provided by Xilinx. The device is able tomonitor eight analog input signals and calculate offset,root mean square and real and reactive powers from theinputs in every signal cycle, thus providing the basic data

DSP DSP Theoretical(v.1.0) (v.1.2) value

RMS 0.3571 0.3571 0.35355valueReal 0.1084 0.1084 0.10825powerReactive -0.0626 -0.0626 -0.0625power

Table 1: Simulation results.

DSP (v.1.0) DSP (v.1.2)

Slices 5181 (38%) 4232 (31%)MULT18X1 6 (18%) 3 (90o)8s

RAMB16s 5 (15%) 5 (15%)

Max. Freq. 110.461 MHz

Table 2: Hardware implementation results.

Different design alternatives have been tried out inorder to optimize available resources and meet frequencyrequirements. As a result, the implemented device easilyexceeds the required operation frequency and accuracywhile only consuming 300O of the available resources ofa XC3S 1500 Xilinx FPGA chip.We can also conclude that state-of-the-art FPGAs are

ready to be used for advanced DSP design, takingadvantage of a variety of tools and integrated designenvironments that automate the most tedious designtasks, allowing the designer to focus on architecture andspecifications and facilitating the exploration of thedesign space in search of an optimal solution.

7. Acknowledgment

This work has been partially supported by thePROFIT-MITC OPENRTU FIT-330101-2004-5 andMYCT MEC META TEC 2004-00840/MIC projects ofthe Spanish Government and the CICE OFU TIC 1023project of the Andalusian Government.

References

[1] "Altera Website." http:Hwww.altera.com/.[2] "Xilinx Website." http:Hwww.xilinx.com/.[3] "Spartan-3 FPGA Family: Complete Data Sheet."

http:Hwww.xilinx.com/bvdocs/publications/dsO99.pdf.[4] W. F. Lee, Verilog Coding for Logic Synthesis, John

Wiley & Sons Inc., ISBN 0-471-42976-7, 2003.[5] B. Cohen, VHDL Coding Styles and Methodologies, 2nd

Edition, Kluber Academic Publishers, ISBN 0-7923-8474-1, 1999.

[6] Xilinx Inc., Xilinx System Generator for DSP v8.1User' s Guide, April 25, 2006.to detennine the quality of the electrical network.

http:Hwww.xilinx.com/support/sw_manuals/sysgen_ug.pdf

[7] Xilinx Inc., Platform Studio User Guide, EmbeddedDevelopment Kit EDK 7.1i, February 15, 2005.http:Hwww.xilinx.com/ise/embedded/edk7_ docs/ps_ug.pdf.

[8] "Simulink* - Simulation and Model-Based Design."http:Hwww.mathworks.com/products/simulink/.

[9] Robert D. Turney, Chris Dick, David B. Parlour, andJames Hwang, "Modeling and Implementation of DSPFPGA Solutions", International Conference on SignalProcessing Applications and Technology, ICSPAT'99,Orlando, November 1-4, 1999.http:Hwww.xilinx.com/products/logicore/dsp/matlab final.pdf

[10] J. Hwang, B. Milne, N. Shirazi, J. Stroomer, "SystemLevel Tools for DSP in FPGAs", Field-ProgrammableLogic and Applications - 11th International Conference,FPL 2001, Belfast, Northern Ireland, UK, August 27-29,2001.

http:Hwww.xilinx.com/products/logicore/dsp/sysgen fpl2001.pdf

[11] J. Ballagh, J. Hwang, P. James-Roxby, E. Keller, S. Sengand B. Taylor, "Building OPB Slave Peripherals usingSystem Generator for DSP", Xilinx Inc., 2004.http:Hwww.xilinx.com/bvdocs/appnotes/xapp264.zip.

[12] "The Mentor Graphics Website."http://www.model.com/.

[13] Analog Devices Inc., "250 kSPS, 6-Channel,Simultaneous Sampling, Bipolar 12/14/16-Bit ADC",2005.http:Hwww.analog.com/UploadedFiles/Data_Sheets/88119461AD7656_7_8_prl.pdf.

[14] Analog Devices Inc., "Nonvolatile Memory, Quad 64-Position Digital Potentiometer", 2005.http:Hwww.analog.com/UploadedFiles/Data_Sheets/ 112773373AD5233_a.pdf.

[15] S. Zack and S. Dhanani, "DSP Co-Processing in FPGAs:Embedding High-Performance, Low-Cost DSPFunctions", Xilinx Inc., March 18, 2004.http:Hwww.xilinx.com/bvdocs/whitepapers/wp212.pdf