ANADOLU UNIVERSITY

DEPARTMENT OF

ELECTRICAL AND ELECTRONICS ENGINEERING

EEM 489 Microprocessors II

Fall, 2014-2015

Lab 4 Report

Date: 21.11.2014

Mahmut Ferit YILDIZ 53206053790

Alper KAPITAŞI 15529041298

1.)Purpose

The purpose of Lab 4 is to learn minimally intrusive debugging skills and some

software skills. One of these skills is called “dump“ that allows the program to capture

strategic information which will will be viewed at a some definite later time. The other one of

these skills is “heartbeat” . Heartbeat is the visual means to see that the written program is still

running or not. The indexed adressing is the one of the software skills that examined in the lab

4. In addition , array data structures, phase lock loop initialization, and usage of systick timer

are the other software skills that learned in the lab 4.

The index addressing was used in this lab for accessing the arrays using pointers

(datapt and timept). The databuffer array was used to keep the situaion of the led(portE data)

whether it is 1 or 0 and timebuffer array was used to keep the value of the counter . To

calculate the counter value, the systick timer was used. Also the systick timer was used for

estimation of real time clock. In this lab system should work on the 80Mhz frequency . The

phase lock loop initialization was used for arranging the crystal to work on 80 Mhz frequency.

2.) Procedure

In the lab session, firstly, the our arrays that are DataBuffer and TimeBuffer were

defined and allocated. Also DataPt and TimePt pointers were defined. After that, port E ,port

F and Debug part were initialized. By the way, the bus speed was arranged to 80 Mhz using

the PLL. In the Debug_Init part, DataBuffer and TimeBuffer arrays that has 50 size of index

were initialized by moving 0xFFFFFFFF into these arrays. Then, pointers were adjusted to

the base addresses.

Secondly, the led that is second bit of port E is adjusted as on. Below the led_on label,

this led is changed according to switch is on or off. If switch is on, led will be toggle. In

addition, there is another led to the third pin of port F. This is toggling during the execution

time.

Final part of code is debug_capture part. That part is used for saving led situation and

time on the DataBuffer array and TimeBuffer array, respectively. Also, there are some

shifting operation as shown on the laboratory paper.

2.2).The Screenshots

3.) Conclusion

In this lab , the lab3 software program was used with real time delay. The real time

clock estimation using the 24 bit counter is learned. The Crystal arrangement of 80 Mhz is

learned and examined in the pll_init subroutine . Advanced index addressing and array data

structures is learned well.

4.) Appendix

SWITCH EQU 0x40024004 ;PE0

LED EQU 0x40024008 ;PE1

SYSCTL_RCGCGPIO_R EQU 0x400FE608

SYSCTL_RCGC2_GPIOE EQU 0x00000010 ; port E Clock Gating Control

SYSCTL_RCGC2_GPIOF EQU 0x00000020 ; port F Clock Gating Control

SYSCTL_RCC2_R EQU 0x400FE070

SYSCTL_RCC_R EQU 0x400FE060

SYSCTL_RIS_R EQU 0x400FE050

GPIO_PORTE_DATA_R EQU 0x400243FC

GPIO_PORTE_DIR_R EQU 0x40024400

GPIO_PORTE_AFSEL_R EQU 0x40024420

GPIO_PORTE_DEN_R EQU 0x4002451C

GPIO_PORTE_PCTL_R EQU 0x4002452C

GPIO_PORTE_AMSEL_R EQU 0x40024528

NVIC_ST_CURRENT_R EQU 0xE000E018

NVIC_ST_RELOAD_R EQU 0xE000E014

NVIC_ST_CTRL_R EQU 0xE000E010

GPIO_PORTF_DATA_R EQU 0x400253FC

GPIO_PORTF_DIR_R EQU 0x40025400

GPIO_PORTF_AFSEL_R EQU 0x40025420

GPIO_PORTF_DEN_R EQU 0x4002551C

GPIO_PORTF_AMSEL_R EQU 0x40025528

GPIO_PORTF_PCTL_R EQU 0x4002552C

GPIO_PORTF_PUR_R EQU 0x40025510

AREA DATA, ALIGN=2

SIZE EQU 50

;You MUST use these two buffers and two variables

;You MUST not change their names

DataBuffer SPACE SIZE*4

TimeBuffer SPACE SIZE*4

DataPt SPACE 4

TimePt SPACE 4

;These names MUST be exported

EXPORT DataBuffer

EXPORT TimeBuffer

EXPORT DataPt

EXPORT TimePt

ALIGN

AREA |.text|, CODE, READONLY, ALIGN=2

THUMB

EXPORT Start

IMPORT TExaS_Init

IMPORT SysTick_Init

IMPORT SysTick_Wait

IMPORT SysTick_Wait10ms

IMPORT PLL_Init

Start BL TExaS_Init ; running at 80 MHz, scope voltmeter on PD3

; initialize Port E

; initialize Port F

; initialize debugging dump

BL Port_Ini ;initialize the ports E and F

BL Debug_Init

BL PLL_Init ; set system clock to 80 MHz

CPSIE I ; TExaS voltmeter, scope runs on interrupts

;loop BL Debug_Capture

led_on

MOV R5, #0x02 ; R0 = 0x00000010 (PE1 LED on)

LDR R4, =GPIO_PORTE_DATA_R ; pointer to Port E data

STR R5, [R4] ; led on

LDR R0,=ONEMSEC

loop

BL delay

BL heartbeat

BL Debug_Capture

Buton

LDR R6, = GPIO_PORTE_DATA_R

LDR R7,[R6]

AND R7,R7,#1

CMP R7,#0

BEQ led_on

LDR R6, = GPIO_PORTE_DATA_R

LDR R8,[R6]

AND R8,R8,#0x02

EOR R8,R8,#0x02

STR R8,[R6]

B loop

heartbeat ; else, toggle led

LDR R1, =GPIO_PORTF_DATA_R ; pointer to Port F data

LDR R0, [R1] ; read all of Port F

AND R0,R0,#0x04 ; just the PF4 input

EOR R0,R0,#0x04

STR R0,[R1]

BX LR

;input PE0 test output PE1

B loop

;-------- Delay

ONEMSEC EQU 240000 ; 60 ms delay

delay

LDR R0,=240000

dela SUBS R0,R0,#1

BNE dela

BX LR

;------------Port Init-------------

; activate clock for Port F

Port_Ini

LDR R1, =SYSCTL_RCGCGPIO_R ; R1 = &SYSCTL_RCGCGPIO_R

LDR R0, [R1] ; R0 = [R1]

ORR R0, R0, #0x20 ; Port F

STR R0, [R1] ; [R1] = R0

NOP

NOP ; allow time to finish activating

; set direction register

LDR R1, =GPIO_PORTF_DIR_R ; R1 = &GPIO_PORTF_DIR_R

LDR R0, [R1] ; R0 = [R1]

ORR R0, R0, #0x04 ; R0 = R0|0x04 (make PF2 output; PF2 built-in blue

LED)

STR R0, [R1] ; [R1] = R0

; regular port function

LDR R1, =GPIO_PORTF_AFSEL_R ; 3) regular port function

MOV R0, #0 ; 0 means disable alternate function

STR R0, [R1]

; enable digital port

LDR R1, =GPIO_PORTF_DEN_R ; R1 = &GPIO_PORTF_DEN_R

LDR R0, [R1] ; R0 = [R1]

ORR R0, R0, #0xFF ; R0 = R0|0x04 (enable digital I/O on PF)

STR R0, [R1] ; [R1] = R0

; configure as GPIO

LDR R1, =GPIO_PORTF_PCTL_R ; configure as GPIO

MOV R0, #0 ; 0 means configure Port E as GPIO

STR R0, [R1]

LDR R1, =GPIO_PORTF_AMSEL_R ; disable analog functionality

MOV R0, #0 ; 0 means analog is off

STR R0, [R1]

LDR R1, =GPIO_PORTF_PUR_R ; pull-up resistors for PF4, PF3

LDR R0, [R1]

ORR R0, #0x18 ; enable weak pull-up on

PF4 and PF3

STR R0, [R1]

;PortE Init

LDR R1, =SYSCTL_RCGCGPIO_R ; 1) activate clock for Port E

LDR R0, [R1]

ORR R0, R0, #0x10 ; set bit 4 to turn on clock for PE

STR R0, [R1]

NOP

NOP ; allow time for clock to finish

LDR R1, =GPIO_PORTE_DIR_R ; 2) set direction register of PE

MOV R0,#0x02 ; PE3 and PE4 input, PE2 and others output

STR R0, [R1]

LDR R1, =GPIO_PORTE_AFSEL_R ; 3) regular port function

MOV R0, #0 ; 0 means disable alternate function

STR R0, [R1]

LDR R1, =GPIO_PORTE_PCTL_R ; configure as GPIO

MOV R0, #0 ; 0 means configure Port E as GPIO

STR R0, [R1]

LDR R1, =GPIO_PORTE_DEN_R ; 6) enable Port E digital port

MOV R0, #0xFF ; 1 means enable digital I/O

STR R0, [R1]

LDR R1, =GPIO_PORTE_AMSEL_R ; disable analog functionality

MOV R0, #0 ; 0 means analog is off

STR R0, [R1]

BX LR

;------------Debug_Init------------

Debug_Init

MOV R4, #50

LDR R2, = DataPt

LDR R1,[R2]

LDR R3, = TimePt

LDR R0,[R3]

LDR R5,= DataBuffer

LDR R6,= TimeBuffer

ops LDR R7, [R1,R5]

LDR R8, [R0,R6]

MOV R7,#0xFFFFFFFF;

MOV R8,#0xFFFFFFFF;

ADD R1,R1,#4;

ADD R0,R0,#4;

SUB R4,R4,#1;

CMP R4,#0;

BNE ops

MOV R1,#0

MOV R0,#0

MOV R10, #50

BX LR

;------------Debug_Capture------------

; Dump Port E and time into buffers

; Input: none

; Output: none

; Modifies: none

; Note: push/pop an even number of registers so C compiler is happy

Debug_Capture

MOV R11,#0

SUB R10,R10,#1

CMP R10,R11

BEQ ppp

LDR R0,=DataPt

LDR R2,[R0]

LDR R1,=TimePt

LDR R3,[R1]

LDR R5,=NVIC_ST_CURRENT_R ;read systick_Timer

LDR R6,[R5] ;

STR R6,[R3] ;dump this time data info into

timebuffer using timept pointer

ADD R3,R3,#4 ;increment the timept address

MOV R9,#0

LDR R1, =GPIO_PORTE_DATA_R ; pointer to Port E data

LDR R0, [R1] ; read all of Port E

ADD R8,R0,#0 ;use temporary register,original data is

in the r8

AND R0,R0,#0x02 ;mask the bit 1 of portE (PE1)

LSR R0,R0,#1 ;shift bit 1 into bit 0 position

STR R0,[R9] ;store it into R9

ADD R0,R8,#0 ;again R0 has the original portE data

AND R0,R0,#0x01 ;mask the bit 0 of portE (PE0)

LSL R0,R0,#4 ;shift bit 0 into bit 4 position

ADD R0,R0,R9 ;R0 = R0 + R9

STR R0,[R2] ;dump this port data info into databuffer

using datapt pointer

ADD R2,R2,#4 ;increment the datapt address

BX LR ; return R0 with inputs

ppp

ALIGN ; make sure the end of this section is aligned

END ; end of file