EEGN-CSCI 660 Introduction to VLSI Design Lecture 8

New York Institute of Technology

Engineering and Computer Sciences

CSCI 660

EEGN-CSCI 660

Introduction to VLSI DesignLecture 8

Khurram Kazi



CSCI 660 2

Verification Strategies: Motivation behind the verification efforts

Never under-estimate the verification effort of a design

Keep in mind Non-recurring Engineering ASICs costs are very high High upfront $ to get handful of sample

chips from the foundry The design is cast in “stone”, i.e. printed on

SiAny bugs or changes to the design cost in

terms of time, $, market share, credibility with your customers, potential law-suits etc.



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Pay extra attention to the verification efforts

In large complex ASICs, at times 70%+ of the project time is spent on ASIC verification. So pay close attention to it while designing.

This is a relatively new field (so to speak) where newer ways have to be used in order to verify the design for 1st time success.

Verification effort can be reduced through abstractionHowever, this requires additional training.

Languages like SystemC and System Verilog are gaining popularity in design verification of complex designs

Verification time can be reduced by using automation



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When should the verification effort start During the specification of the device,

verification methodology should begin also. Develop the verification architecture and build

a comprehensive environment. Think carefully how testbenches need to be

developed. Just don’t throw code at it. Have systems perspective in mind, along with various stages of verification



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Levels of verificationSystem

Board

Multiple ASICs or FPGAs

Single ASIC or FPGA

Top level Block

Sub-blocks

Most likely ASIC designers will have to make provisions for all these levels of verification

Try to develop testbench such that it can be re-used at various levels or verification



CSCI 660 6

Example of a Multi ASIC verification environment

Pattern Generator (1)



Rx ofASIC 1

ASIC 4Rx ofASIC 2

Rx ofASIC 3

Tx ofASIC 1

Tx ofASIC 2

Tx ofASIC 3

Analyzer (1)

Analyzer (2)

Analyzer (3)



CSCI 660 7

Sample architecture of a generator and analyzer

Transmitter.vhd

Global signals and control of tests;Global signals values are set at this level

Analyzer.vhd

Global signals can be used to as expected values of out of ASIC

ASIC

Tb_dcom1Tb_dcom2Tb_frame_length….

Tb_testcase1.vhd



CSCI 660 8

Tasks and Functions in Verilog Same functionality is frequently required to be

implemented in many places. The implies that commonly used portions of the design should be abstracted into routines and these routines should be invoked instead of repeating the code.

Verilog provides tasks and functions to break up large behavioral design into smaller pieces.

Tasks and functions in Verilog allow the designer to abstract the commonly used code that is used in many places



CSCI 660 9

Functions in VerilogSource: HDL programming Fundamentals: VHDL and Verilog by Nazieh M. Botros

Functions in Verilog have a declaration statements and a body. In the declaration, the size (dimension), type, and name of the output are specified, as well as the names and sizes (dimensions) of the inputs. e.g., the declaration statement:

function expinput a, b;

Declares a function with a name “exp”. The functions has two inputs, a and b, and one output, exp.



CSCI 660 10

Functions in VerilogSource: HDL programming Fundamentals: VHDL and Verilog by Nazieh M. Botros

module greater_2 (x, y, z) input signed [3:0] x, y; output signed [3:0] z;

reg signed [3:0] z;always @ (x,y)begin z = grt (x,y); // This is a function

callend

function [3:0] grt;/* The above function declares a function by the name grt;grt is also the output of the functions */

input signed [3:0] a, b;/* The above statement declares two inputs to the function;both are 4-bit signed numbers. */begin if (a >= b) grt = a; else grt = b; endendfunction

endmodule



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Tasks in VerilogTasks are declared with keywords task

and endtask. The format of the task is divided into two

partsdeclaration

Name of the task is specified along with the inputs and outputs of the task

bodyDescribes the relationships between the input and

outputs



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Sample code of a task in Verilogmodule task_ex; integer a, b, c, d; initial begin

a = 3;b = 4;d = 12;add (a, c, d); //Notice.. here the port mapping is positional

$display (" final valus for c = %d", c); end

task add; input [31:0] in1; output [31:0] out; //Notice this maps to "c" input [31:0] in2; out = in1 + in2 + d; //Notice here the value of "d" is defined in the module; it is

a global variable endtask // addendmodule // task_ex



CSCI 660 13

File Processing in VerilogSource: HDL programming Fundamentals: VHDL and Verilog by Nazieh M. Botros

$fopen The task $fopen is used to open files. The format

for opening a file ischannel = $fopen (“name of the file”);

The channel is a variable of type integer; it indicates the channel number. Verilog uses this channel number to track and identify which files are open. Verilog automatically assigns an integer value to each channel. For example, to open a text file names testfile, we can write

ch1 = $fopen(testfile.txt”);ch1 becomes the indicator (identifier) of the file

testfile.txt



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$fclose The task $fclose is used to close a file indicated by the

channel number. e.g., $fclose(ch1);closes the file “testfile.txt”

$fdisplay The task $fdisplay is used to write variables, signals or

quoted strings. The format of $fdisplay is as follows:$fdisplay (channel1, V1, V2, V3, …);

where V1, V2, V3 … are variable, signals, or quoted strings. e.g.,

$fdisplay (ch1, “item description quantity”);After executing the task, the file testfile.txt will display

item description quantity



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$fmonitor The task $fmonitor is used to monitor and record values of

variables signals etc.$fmonitor (channel, v1, v2, v3, …); e.g. $fmonitor (ch1, “ %b”, quantity);

The above task monitors quantity and records its value in binary in the file testfile.txt, indicated by ch1; %b indicates binary format. If quantity = 7 in decimal, after execution of the above task, the file testfile.txt looks like:

item description quantity (from the previous slide) 111

%d Display in decimal%h Display in hex etc.

Escape characters may also be used\n insert a blank line\t Insert tab etc.



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$fgets( ) and $sscanf( ) $fgets( )Gets string from a streame.g. $fgets (str, file4)

$sscanf( )Read formatted data from string

Reads data from str and stores them according to the parameter format into the locations give by the additional arguments. See example in the next slide



CSCI 660 17

Text I/O in Verilog: Used for testbench purposes

File that is being read

(“file4.txt”)0001 0002 00030030 0040 0050aa10 bb10 cc2bfff1 f210 ffe1

module txtio3 (out1, out2, out3, clk); output [15:0] out1; output [15:0] out2; output [15:0] out3; output clk; reg [15:0] out1, out2, out3; reg [4*8*4:1] str; reg clk; reg [15:0] a, b, c; integer file4, rc, line=0;

initial begin file4 = $fopen("file4.txt", "r"); if (file4 == 0)

$finish; clk = 0; forever #10 clk = !clk; end

always @ (posedge clk) begin rc = $fgets (str, file4); rc = $sscanf (str, "%h %h %h\n", a, b, c); $display ( "\tLine %d read %h,\t%h, \t%h", line, a, b, c); out1 <= a; out2 <= b; out3 <= c; line = line +1; if (rc == 0) begin $fclose (file4); $finish; end end // always @ (posedge clk) endmodule // txtio3



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Simulation Results



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Packages in VHDLFrequently used pieces of VHDL code

are written in the form of Components, Functions, or Procedures

Such code can be placed in a Package and compiled into a destination Library

This allows code partitioning, code sharing and code reuse



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Packages in VHDL Package can contain

Components Functions Procedure Type and constant definitions

Syntax of a packagePACKAGE package_name IS

(declarations)END package_name;[PACKAGE BODY package_name IS

(functions and procedures descriptions)END package_name;]



CSCI 660 21

Packages in VHDL: A Simple PackageLIBRARY ieee;USE ieee.std_logic_1164.all;

PACKAGE my_package IS

TYPE state is (st1, st2, st3, st4);TYPE color is (red, green, blue);CONSTANT F628 : STD_LOGIC_VECTOR (15 downto 0) :=

“1111_0110_0010_1000”;SIGNAL TB_DCOM1: STD_LOGIC_VECTOR (7 downto 0);

END my_package;



CSCI 660 22

Functions in VHDLA FUNCTION is a section of sequential codeOperations like data type conversions,

logical operations, arithmetic computations etc., can be created as functions

Function BodyFUNCTION function_name [<parameter list>] RETURN

data_type is [declarations]BEGIN

(sequential statements)END fucntions_name;



CSCI 660 23

Functions in VHDLFunction conv_integer (SIGNAL vector :STD_LOGIC_VECTOR) RETURN INTEGER IS;VARIABLE result : INTEGER RANGE 0 to 2**vector’LENGTH -1;BEGIN

IF (vector’HIGH) = ‘1’) THEN result :=1;ELSE result := 0;END IF;FOR I IN (vector’HIGH-1) DOWNTO (vector’LOW) LOOP

result := result * 2;IF (vector(i) = ‘1’) THEN result := result+1;END IF;

END LOOP;RETURN result;END conv_integer;

-----Function call-----….. y <= conv_integer (a);….---------------------------



CSCI 660 24

Procedures in VHDLProcedure is similar to a Function,

however, it can return more than one value

Procedure BodyPROCEDURE precedure_name

[<parameter lisr.] IS[declarations]

BEGIN(sequential statements)

END procedure_name;



CSCI 660 25

Procedures in VHDLPROCEDURE sort (SIGNAL in1, in2: IN INTEGER RANGE 0 TO 255;SIGNAL min, max: OUT INTEGER RANGE 0 TO

255) ISBEGIN

IF (in1 > in2) THEN max <= in1; min <= in2;ELSE max <= in2; min <= in1;END IF;

END sort;



CSCI 660 26

Locations of Procedures and Functions in VHDLFunctions and Procedures can be

placed inPACKAGE

Where the Package is compiled in a LibraryMain Code



CSCI 660 27

Locations of Procedures and Functions in VHDL

-----Package: ----LIBRARY ieee;USE ieee.std_logic_1164;Package my_package ISFunction conv_integer (SIGNAL vector :STD_LOGIC_VECTOR) RETURN

INTEGER IS;PROCEDURE sort ( SIGNAL in1, in2: IN INTEGER RANGE 0 TO 255;SIGNAL min, max: OUT INTEGER RANGE 0 TO 255) ISEND my_package;PACKAGE BODY my_package ISPROCEDURE sort (SIGNAL in1, in2: IN INTEGER RANGE 0 TO 255;SIGNAL min, max: OUT INTEGER RANGE 0 TO 255) ISBEGIN

IF (in1 > in2) THEN max <= in1; min <= in2;ELSE max <= in2; min <= in1;END IF;

END sort;

Copy the Function code here if you want to add any functions to the package

END my_package;

Compile the package in the work.libIn the main code of the design or the testbench the package can be called as

Library ieee;USE ieee.std_logic….USE work.my_package.all…….



CSCI 660 28

Text I/O to/from Files library ieee;use ieee.std_logic_1164.all;use std.textio.all;ENTITY txtio is port(start : in STD_LOGIC; z, z1, z2, z3 : out integer);end txtio;architecture integer_proc of txtio isbeginprocess-- declare the infile as a text filefile infile : text;--declare variable fstatus (or any other variable name)-- as of type file_open_statusvariable fstatus : file_open_status;variable count : integer;--declare variable temp as the type linevariable temp : line;begin wait for 1 ns;--open the file file_int.txt in read mode file_open (fstatus, infile, "file_int.txt", read_mode);--read the first line of the file and store the line in tempreadline (infile, temp);--temp now has the data: 12 -3 5

-- Read the first integer (12) from the line temp and store it-- in the integer variable count.read (temp, count);-- count has the value of 12. Multiply by 2 and store in zz <= 2 * count;-- Read the second integer from the line temp and--store it in countread (temp, count);-- now count has a value of -3--Multiply by 5 and store in z1z1 <= 5 * count;-- Read the third integer from the line temp and--store it in countread (temp, count);-- now count has a value of 5--Multiply by 3 and store in z2z2 <= 3 * count;--Read the second line and store it in tempreadline (infile, temp);--temp has only the second line--Read the first integer of the second line and store it in countread (temp, count);--Multiply by 4 and store in Z3z3 <= 4 * count;--close the infilefile_close (infile);end process;end integer_proc;

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EEGN-CSCI 660 Introduction to VLSI Design Lecture 8