EE247 Lecture 27 - EECS Instructional Support Group … 247 Lecture 27: Oversampling Data Converters © 2007 H. K. Page 3 EE247 Lecture 27 Oversampled ADCs (continued) –2nd order

EECS 247 Lecture 27: Oversampling Data Converters © 2007 H. K. Page 1

EE247Lecture 27

• Administrative–EE247 Final exam:

– Date: Wed. Dec. 19th

– Time: 12:30pm-3:30pm– Location: 70 Evans Hall– Extra office hours: Thurs. Dec. 13th, 10:am-12pm

• Closed course notes/books• No calculators/cell phones/PDAs/computers• Bring two 8x11 paper with your own notes• Final exam covers the entire course material unless

specified otherwise


EE247Lecture 27

• Administrative–Project submission:

• Deadline postponed to Thurs. Dec. 13th

• If you have chosen to do the project, please make an appointment with the instructor: – Thurs. Dec. 13th, After 12:30 for 15mins each project

report to present the results


EE247Lecture 27

Oversampled ADCs (continued)–2nd order ΣΔ modulator

• Practical implementation– Effect of various building block nonidealities on the ΣΔ

performanceIntegrator maximum signal handling capability (last lecture)Integrator finite DC gain (last lecture)Comparator hysteresis (last lecture)Integrator non-linearity (last lecture)

• Effect of KT/C noise• Finite opamp bandwidth• Opamp slew limited settling

– Implementation example–Higher order ΣΔ modulators

• Cascaded modulators (multi-stage)• Single-loop single-quantizer modulators with multi-order filtering in

the forward path


2nd Order ΣΔEffect of Integrator KT/C noise

• For the example of digital audio with 16-bit (96dB) & M=256 (110dB SQNR)Cs=1pF 7μVrms noiseIf FS=2Vp-p-d then thermal noise @ -101dB degrades overall SNR by ~10dBCs=1pF, CI=2pF much smaller capacitor area (~1/M) compared to Nyquist ADCSince thermal noise provides some level of dithering better not choose much larger capacitors!

Vi

-

+

φ1 φ2

Vo

Cs

CI2

2

2

2

1/ 2 4/ 2

Total in-band noise:

4

2

n

n

n Binput referred

KTvCs

kT kTv fCs fs Cs fs

kTv fCs fs

kTCs M

−

=

= × =×

= ××

=×


2nd Order ΣΔEffect of Finite Opamp Bandwidth

Input/Output z-transformVi+

Cs-

+ Vo

CIφ1 φ2

Vi-Unity-gain-freq.= fu =1/τ

Vo

φ2

T=1/fs

settlingerror

time

Assumptions: Opamp does not slewOpamp has only one pole exponential settling


2nd Order ΣΔEffect of Finite Opamp Bandwidth

ΣΔ does not require high opamp bandwidth T/τ >2 or fu > 2fs adequateNote: Bandwidth requirements significantly more relaxed compared to Nyquist rate ADCs

Ref: B.E. Boser et. al, “The Design of Sigma-Delta Modulation A/D Converters,” JSSC, Dec. 1988.


2nd Order ΣΔEffect of Slew Limited Settling

φ1

φ2

Vo-real

Vo-ideal

Clock

Slewing Slewing


2nd Order ΣΔEffect of Slew Limited Settling

Assumption: Opamp settling includes a single-pole setting of τ =1/2fs + slewing

Low slew rate degrades SNR rapidly- increases quantization noise and also causes signal distortionMinimum slew rate of SR

min~1.2 (Δ x fs) required

Input Signal = -5dBT/τ =2

Ref: B.E. Boser et. al, “The Design of Sigma-Delta Modulation A/D Converters,” JSSC, Dec. 1988.


2nd Order ΣΔImplementation Example: Digital Audio Application

• In Ref.: 5V supply, Δ = 4Vp-p-d, fs=12.8MHz M=256 theoretical quantization noise @-110dB

• Minimum capacitor values computed based on -104dB noise wrt maximum signal

Max. inband KT/C noise = 7μVrms ( thermal noise dominates provide dithering & reduce limit cycle oscillations)C1=(2kT)/(M vn

2 )=1pF C2=2C1Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal

acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618 - 627, April 1991.


2nd Order ΣΔImplementation Example: Integrator Opamp

Class A/B type opamp High slew-rate S.C. common-mode feedback

Input referred noise (both thermal and 1/f) important for high resolution performance

Minimum required DC gain> M=256 , usually DC gain designed to be much higher to suppress nonlinearities (particularly, for class A/B amps)

Minimum required slew rate of 1.2(Δ.fs ) 65V/usec

Minimum opamp settling time constant 1/2fs~30nsec

Ref: B. P. Brandt, et. al, "Second-order sigma-delta modulation for digital-audio signal acquisition," IEEE Journal of Solid-State Circuits, vol. 26, pp. 618 - 627, April 1991.


2nd Order ΣΔImplementation Example: Comparator

Comparator simple design

Minimum acceptable hysteresis or offset (based on analysis) Δ/25 ∼ 160mV

Since offset requirement not stringent No preamp needed, basically a latch with reset



2nd Order ΣΔImplementation Example: Subcircuit Performance

Our computed Over-Design Factorminimum requiredDC Gain 48dB x8 (compensates non-linear open-loop gain)Unity-gain freq =2fs=25MHz x2Slew rate = 65V/usec x5

Output range 1.7Δ=6.8V! X0.9

Settling time constant= 30nsec x4

Comparator offset 160mV x12



2nd Order ΣΔImplementation Example: Digital Audio Applications


Measured SNDRM=256, 0dB=4Vp-p-dfsampling: 12.8MHzSignal Frequency: 2.8kHz

Note: The Nyquist ADC tests such as INL and DNL test do not apply to ΣΔ modulator type ADCS

MaximumSNR @ -3dB

wrt to Δ




Measured Performance Summary(Does Not Include Decimator)






Measured & simulated spurious tones performance as a function of DC input signal Sampling rate=12.8MHz, M=256



Measured & simulated noise tone performance for near zero DC worst case input 0.00088Δ


Sampling rate=12.8MHz, M=256




Measured & simulated worst-case noise tone @ DC input of 0.00088ΔBoth indicate maximum tone @ 22.5kHz around -100dB level



Higher Order ΣΔ Modulator Dynamic Range

2X increase in M (6L+3)dB or (L+0.5)-bit increase in DR

( )

( )

( )

( )

1 1

2

2 2

2 1

2 12

2 12

2

( ) ( ) 1 ( ) , order

1 sinusoidal input, 12 2

12 1 123 2 1

2

3 2 110log

2

3 2 110log 2

2

L

X

L

Q L

LXL

Q

LL

L

LY z z X z z E z

S STF

SL M

LS MS

LDR M

LDR

π

π

π

π

− −

+

+

+

⎛ ⎞⎜ ⎟⎝ ⎠

⎡ ⎤⎢ ⎥⎢ ⎥⎣ ⎦

⎡ ⎤⎢ ⎥⎢ ⎥⎣ ⎦

= + − → ΣΔ

Δ= =

Δ=+

+=

+=

+= + ( )1 10 logL M+ × ×


ΣΔ Modulator Dynamic RangeAs a Function of Modulator Order

• Potential stability issues for L >2

L=2

L=3

L=1


Higher Order ΣΔ Modulators

• Extending ΣΔ Modulators to higher orders by adding integrators in the forward path (similar to 2nd order)

Issues with stability

• Two different architectural approaches used to implement ΣΔ modulators of order >2

1. Cascade of lower order modulators (multi-stage)2. Single-loop single-quantizer modulators with

multi-order filtering in the forward path


Higher Order ΣΔ Modulators(1) Cascade of 2-Stages ΣΔ Modulators

• Main ΣΔ quantizes the signal • The 1st stage quantization error is then quantized by the 2nd quantizer • The quantized error is then subtracted from the results in the digital domain


2nd Order (1-1) Cascaded ΣΔ Modulators

2nd order noise shaping


3rd Order Cascaded ΣΔ Modulators(a) Cascade of 1-1-1 ΣΔs

• Can implement 3rd

order noise shaping with 1-1-1

• This is also called MASH (multi-stage noise shaping)


3rd order noise shaping

Advantages of 2-1 cascade:

• Low sensitivity to precision matching of analog/digital paths

• Low spurious limit cycle tone levels

• No potential instability

3rd Order Cascaded ΣΔ Modulators(b) Cascade of 2-1 ΣΔs


Sensitivity of Cascade of (1-1-1) ΣΔ Modulatorsto Matching of Analog & Digital Paths

Matching of ~ 0.1%2dB loss in DR

Matching of ~ 1%28dB loss in DR


Sensitivity of Cascade of (2-1) ΣΔ Modulatorsto Matching Error

Accuracy of < +−3%2dB loss in DR

Main advantage of 2-1 cascade compared to 1-1-1 topology:• Low sensitivity to matching of analog/digital paths (in excess of one

order of magnitude less sensitive compared to (1-1-1)!)


2-1 Cascaded ΣΔ Modulators

Accuracy of < +−3%2dB loss in DR

Ref: L. A. Williams III and B. A. Wooley, "A third-order sigma-delta modulator with extended dynamic range," IEEE Journal of Solid-State Circuits, vol. 29, pp. 193 - 202, March 1994.


2-1 Cascaded ΣΔ Modulators

Effect of gain parameters on signal-to-noise ratio


Comparison of 2nd order & Cascaded (2-1) ΣΔ Modulator

5.2mm2 (1μ tech.)0.39mm2 (1μ tech.)Active Area47.2mW13.8mWPower Dissipation

8Vppd5V supply

4Vppd5V supply

Differential input range

128 (theoretical SNR=128dB)

256 (theoretical SNR=109dB)

Oversampling rate98dB94dBPeak SNDR104dB (17-bits)98dB (16-bits)Dynamic Range(2+1) Order2nd orderArchitectureWilliams, JSSC 3/94Brandt ,JSSC 4/91Reference

Digital Audio Application, fN =50kHz(Does not include Decimator)


2-1 Cascaded ΣΔ ModulatorsMeasured Dynamic Range Versus Oversampling Ratio

Ref: L. A. Williams III and B. A. Wooley, "A third-order sigma-delta modulator with extended dynamic range," IEEE Journal of Solid-State Circuits, vol. 29, pp. 193 - 202, March 1994.

3dB/Octave

Theoretical21dB/Octave


Higher Order ΣΔ Modulators(1) Cascaded Modulators Summary

• Cascade two or more stable ΣΔ stages

• Quantization error of each stage is quantized by the succeeding stage and subtracted digitally

• Order of noise shaping equals sum of the orders of the stages

• Quantization noise cancellation depends on the precision of analog/digital signal paths

• Quantization noise further randomized less limit cycle oscillation problems

• Typically, no potential instability


Higher Order ΣΔ Modulators(2) Multi-Order Filter

• Zeros of NTF (poles of H(z)) can be strategically positioned to suppress in-band noise spectrum

• Approach: Design NTF first and solve for H(z)

( ) 1( ) ( ) ( )1 ( ) 1 ( )

H zY z X z E zH z H z

= ++ +

Σ

E(z)

X(z) Y(z)( )H z Σ

Y( z ) 1NTF

E( z ) 1 H( z )= =

+


Example: Modulator Specification

• Example: Audio ADC– Dynamic range DR 18 Bits– Signal bandwidth B 20 kHz– Nyquist frequency fN 44.1 kHz– Modulator order L 5– Oversampling ratio M = fs/fN 64– Sampling frequency fs 2.822 MHz

• The order L and oversampling ratio M are chosen based on– SQNR > 120dB


Noise Transfer Function, NTF(z)% stop-band attenuation Rstop=80dB, L=5 ... L=5; Rstop = 80;B=20000; [b,a] = cheby2(L, Rstop, B, 'high');

% normalize b = b/b(1); NTF = filt(b, a, ...);

104 106-100

-80

-60

-40

-20

0

20

Frequency [Hz]

NTF

[dB

]Chebychev 2 filter chosen

zeros in stop-band


Loop-Filter CharacteristicsH(z)

( ) 1NTF( ) 1 ( )

1( ) 1

Y zE z H z

H zNFT

= =+

→ = −

104 106-20

0

20

40

60

80

100

Frequency [Hz]

Loop

filte

r H

[dB

]


Modulator TopologySimulation Model

Q

I_5I_4I_3I_2I_1

Y

b2b1

a5a4a3a2a1

K1 z -1

1 - z -1

I1

gDAC Gain Comparator

X

-1

1 - z -1

I2

K2 z -1

1 - z -1

I3

K3 z -1

1 - z -1

I4

K4 z -1

1 - z -1

I5

K5 z

+1-1

Filter


Filter Coefficients

a1=1;

a2=1/2;

a3=1/4;

a4=1/8;

a5=1/8;

k1=1;

k2=1;

k3=1/2;

k4=1/4;

k5=1/8;

b1=1/1024;

b2=1/16-1/64;

g =1;

Ref: Nav Sooch, Don Kerth, Eric Swanson, and Tetsuro Sugimoto, “Phase Equalization System for a Digital-to-Analog Converter Using Separate Digital and Analog Sections”, U.S. Patent 5061925, 1990, figure 3 and table 1


5th Order Noise ShapingSimulation Results

• Mostly quantization noise, except at low frequencies

• Let’s zoom into the baseband portion…

0 0.1 0.2 0.3 0.4 0.5-160

-140

-120

-100

-80

-60

-40

-20

0

20

40

Frequency [ f / fs ]

Out

put S

pect

rum

[dB

WN

]/ In

t. N

oise

[dB

FS]

Output SpectrumIntegrated Noise (20 averages)

Signal

Notice tones around fs/2


5th Order Noise Shaping

0 0.2 0.4 0.6 0.8 1-160

-140

-120

-100

-80

-60

-40

-20

0

20

40

Out

put S

pect

rum

[dB

WN

] /

Int.

Noi

se [d

BFS

]

Output SpectrumIntegrated Noise (20 averaged)

Quantization noise -130dBFS @ band edge!Signal

Band-Edge

Frequency [ f / fN ]

• SQNR > 120dB

• Sigma-delta modulators are usually designed for negligible quantization noise

• Other error sources dominate, e.g. thermal noise are allowed to dominate & thus provide dithering to eliminate limit cycle oscillations


0 0.2 0.4 0.6 0.8 140

60

80

100

120

140M

agni

tude

[dB

] Loop Filter

0 0.2 0.4 0.6 0.8 1-100

0

100

200

300

400

Frequency [f/fN]

Phas

e [d

egre

es]

In-Band Noise Shaping

• Lot’s of gain in the loop filter pass-band

• Forward path filter not necessarily stable!

• Remember that:

NTF ~ 1/H small within passband since H is large

STF=H/(1+H) ~1 within passband

0 0.2 0.4 0.6 0.8 1-160

-120

-80

-40

0

40

Frequency [f/fN]

Out

put S

pect

rum

Output SpectrumIntegrated Noise (20 averages)

|H(z)| maxima align up with noise minima


-40 -35 -30 -25 -20 -15 -10 -5 0

-20

-15

-10

-5

0

5

10

i1i2i3i4i5q

Input [dBV]

Loop

filte

r pea

k vo

ltage

s [V

]

Internal Node Voltages

• Internal signal amplitudes are weak function of input level (except near overload)

• Maximum peak-to-peak voltage swing approach +-10V! Exceed supply voltage!

• Solutions:• Reduce Vref ??• Node scaling

Integrator outputs

Quantizer input


Node Scaling Example:3rd Integrator Output Voltage Scaled by α

K3 * α, b1 /α, a3 / α, K4 / α, b2 * αVnew=Vold* α

Q

I_5I_4I_3I_2I_1

Y

b2b1

a5a4a3a2a1

K1 z -1

1 - z -1

I1


X

-1

1 - z -1

I2

K2 z -1

1 - z -1

I3

K3 z -1

1 - z -1

I4

K4 z -1

1 - z -1

I5

K5 z


Node Voltage Scaling

-40 -35 -30 -25 -20 -15 -10 -5 0-1.5

-1

-0.5

0

0.5

1

1.5

Input [dBV]

Loop

filte

r pea

k vo

ltage

s [V

]

α=1/10

k1=1/10;k2=1;k3=1/4;k4=1/4;k5=1/8;a1= 1; a2=1/2;a3=1/2; a4=1/4;a5=1/4;b1=1/512;b2=1/16-1/64;g =1;

• Integrator output range reasonable for new parameters• But: maximum input signal limited to -5dB (-7dB with safety) – fix?


Input Range ScalingIncreasing the DAC levels by using higher value for g reduces the analog to digital conversion gain:

Increasing vIN & g by the same factor leaves 1-Bit data unchanged

gzgHzH

zVzD

IN

OUT 1)(1

)()()( ≅

+=

Loop FilterH(z)ΣvIN

dOUT+1 or -1Comparator

g


Scaled Stage 1 Model

g modified:From 1 to 2.5;

Overload input shifted up by 8dB

-40 -35 -30 -25 -20 -15 -10 -5 0-1.5

-1

-0.5

0

0.5

1

1.5

Input [dBV]

Loop

filte

r pea

k vo

ltage

s [V

]


Stability Analysis

• Approach: linearize quantizer and use linear system theory!• One way of performing stability analysis use RLocus in Matlab with

H(z) as argument and Geff as variable• Effective quantizer gain

• Can obtain Geff from simulation

222

yGeff q

=

H(z)Σ Σ

Quantizer Model

e(kT)

x(kT) y(kT)Geffq(kT)

Ref: R. W. Adams and R. Schreier, “Stability Theory for ΔΣ Modulators,” in Delta-Sigma Data Converters- S. Norsworthy et al. (eds), IEEE Press, 1997


Stability Analysis

• Zeros of STF same as zeros of H(z)• Poles of STF vary with G• For G=0 (no feedback) poles of the STF same as poles of H(z)• For G=large, poles of STF move towards zeros of H(z)

Ref: R. W. Adams and R. Schreier, “Stability Theory for ΔΣ Modulators,” in Delta-Sigma Data Converters- S. Norsworthy et al. (eds), IEEE Press, 1997

( )( )

( ) ( )( )

( )( ) ( )

1G H zSTF

G H zN zH zD z

G N zSTFD z G N z

⋅=+ ⋅

=

⋅→ =+ ⋅


Modulator z-Plane Root-Locus

• As Geff increases, poles of STF move from

• poles of H(z) (Geff = 0) to • zeros of H(z) (Geff = ∞)

• Pole-locations inside unit-circle correspond to stable STF and NTF

• Need Geff > 4.5 for stability

Geff = 4.5

z-Plane Root Locus

0.6 0.7 0.8 0.9 1 1.1-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4 Increasing Geff

Unit Circle


-40 -35 -30 -25 -20 -15 -10 -5 0 50

1

2

3

4

5

6

7

8

Input [dBV]

Effe

ctiv

e Q

uant

izer

Gai

n

Geff=4.5stable unstable

• Large inputs comparator input grows

• Output is fixed (±1)Geff dropsmodulator unstable for large inputs

• Solution:• Limit input amplitude• Detect instability (long

sequence of +1 or -1) and reset integrators

• Note that signals grow slowly for nearly stable systems use long simulations

Effective Quantizer Gain, Geff


5th Order ModulatorFinal Parameter Values

±2.5V

Stable input range ~ ±1V

1/10 1 1/4 1/4 1/8

1/512 1/16-1/64

1 12 1/2 1/4 1/4

Stable input range~ ±1V

Q

I_5I_4I_3I_2I_1

Y

b2b1

a5a4a3a2a1

K1 z -1

1 - z -1

I1


X

-1

1 - z -1

I2

K2 z -1

1 - z -1

I3

K3 z -1

1 - z -1

I4

K4 z -1

1 - z -1I5

K5 z

1


Summary• Oversampled ADCs decouple SQNR from circuit

complexity and accuracy

• If a 1-Bit DAC is used, the converter is to 1st order, inherently linear—independent of component matching

• Typically, used for high resolution & low frequency applications – e.g. digital audio

• 2nd order ΣΔ used extensively due to lower levels of limit cycle related spurious tones compared to 1st order

• ΣΔ modulators of order greater than 2:– Cascaded (multi-stage) modulators– Single-loop, single-quantizer modulators with multi-order

filtering in the forward path


Bandpass ΔΣ Modulator

+

_vIN

dOUT

∫

DAC

• Replace the integrator in 1st order lowpass ΣΔ with a resonator

2nd order bandpass ΣΔ

Resonator

∫

∫


Bandpass ΔΣ ModulatorExample: 6th Order

Measured output for a bandpass ΣΔ (prior to digital filtering)

Key Point:

NTF notch type shape

STF bandpass shape

Ref: Paolo Cusinato, et. al, “A 3.3-V CMOS 10.7-MHz Sixth-Order Bandpass Modulator with 74-dB Dynamic Range “, ΙΕΕΕ JSSCC, VOL. 36, NO. 4, APRIL 2001

Input SinusoidQuantization Noise


Bandpass ΣΔ Characteristics

• Oversampling ratio defined as fs/2B where B = signal bandwidth

• Typically, sampling frequency is chosen to be fs=4xfcenter where fcenter bandpass filter center frequency

• STF has a bandpass shape while NTF has a notch shape

• To achieve same resolution as lowpass, need twice as many integrators


Bandpass ΣΔ Modulator Dynamic RangeAs a Function of Modulator Order (K)

• Bandpass ΣΔ resolution for order K is the same as lowpass ΣΔ resolution with order L= K/2

K=415dB/Octave

K=621dB/Octave

K=29dB/Octave


Example: Sixth-Order Bandpass ΣΔ Modulator


Simulated noise transfer function Simulated signal transfer function


Example: Sixth-Order Bandpass ΣΔ Modulator


Features & Measured Performance Summary

fs=4xfcenter

BOSR=fs /2B


SummaryOversampled ADCs

• Noise shaping utilized to reduce baseband quantization noise power

• Reduced precision requirement for analog building blocks compared to Nyquist rate converters

• Relaxed transition band requirements for analog anti-aliasing filters

• Utilizes low cost, low power digital filtering

• Speed is traded for resolution

• Typically used for lower frequency applications compared to Nyquist rate ADCs

Documents

EE247 Lecture 27 - EECS Instructional Support Group … 247 Lecture 27: Oversampling Data Converters © 2007 H. K. Page 3 EE247 Lecture 27 Oversampled ADCs (continued) –2nd order