EE 560 SEQUENTIAL MOS LOGIC CIRCUITSLOGIC CIRCUITS COMBINATIONAL SEQUENTIAL (non-regenerative) (regenerative) BISTABLE MONOSTABLE ASTABLE. Kenneth R. Laker, University of Pennsylvania

EE 560 SEQUENTIAL MOS LOGICCIRCUITS

Kenneth R. Laker, University of Pennsylvania

1


2

LOGIC CIRCUITS

COMBINATIONAL SEQUENTIAL

(non-regenerative) (regenerative)

BISTABLE MONOSTABLE ASTABLE


3

COMBINATIONALLOGIC CIRCUIT

V1

V2

V3

Vout1

M

Vout2

M

MEMORY


4

1

2V

i2V

o2

Vi1 V

o1

Vo1

Vi2

Vi1

Vo2

INV2 VTC

INV1 VTC

ENERGY

BISTABLE BEHAVIOR

Vo/V

in < 1

Vo/V

in < 1

Vo/V

in >> 1


5

Vo1

S

G

D

B

B

D

G

S

VDD

S

G

D

B

B

D

G

S

VDD

Vi1

Vo2

Vi2

t

VOH

VOL

Vth

Vo1

Vo2


6SMALL SIGNAL ANALYSIS

1

2

vg1

id1

ig1

id2 v

g2

ig2

vo1

vo2

ASSUME: Cg >> C

d

Cg

Cg

ig1

= id2

= gmv

g2

ig2

= id1

= gmv

g1

where

where

and vo1

= vg2

and vo2

= vg1

=> for i = 1, 2

vo1

(0) = vo2

(0) = Vth


7

for i = 1, 2

≈ 0 for t >> τ0

ΝΟΤΕ ΤΗΑΤ

vo1

: Vth -> V

OH or V

OL

vo2

: Vth -> V

OL or V

OH

vo1

vo2

Vth

Vth

VOH

VOL

VOH

VOL

≈ 0 for t >> τ0


8As BISTABLE circuit settles from UNSTABLE Op-Pt toSTABLE Op-Pt, signal travels around 2 INV loop n times

1

2vo2

vo1

loop

If during interval t = T, signal travels around the loop n times

t

VOH

VOL

Vth

vo1

vo2

T

et/τ

loop 1 loop 2 loop n

A1 A2 An


9FULL CMOS SR LATCHV

DD

M1 M2

VDD

M3 M4

QQ

S R

STATE OF LATCH can be EXTERNALLY SWITCHED between the 2 STABLE STATES

SET STATE: S = 1, R = 0 => Q = 1,RESET STATE: S = 0, R = 1 => Q = 0,HOLD: S = 0, R = 0 (like two cross-coupled Inverters)NOT ALLOWED: S = 1, R = 1

Q = 0

Q = 1


10

NOR-basedSR Latch

S

R Q

Q

S R Qn+1 Operation

0 0 Qn hold

1 0 1 0 set 0 1 0 1 reset 1 1 0 0 NOT allowed

S

QR

Q

Q n

Q n +1


11VDD

M1 M2

VDD

M3 M4

QQ

S R

S R Qn+1 Operation

VOH

VOL

VOH

VOL

M1, M2 ON, M3, M4 OFF V

OL V

OH V

OL V

OH M1, M2 OFF, M3, M4 ON

VOL

VOL

VOH

VOL

M1, M4 OFF, M2 ON or V

OL V

OL V

OL V

OH M1, M4 OFF, M3 ON

Q n +1


12VDD

M1 M2

VDD

M3 M4

QQ

S R

M5

M6

M7

M8

CQ

CQ

CQ = C

gb2 + C

gb5 + C

db3 + C

db4 + C

db7 + C

sb7 + C

db8

CQ = C

gb3 + C

gb7 + C

db1 + C

db2 + C

db5 + C

sb5 + C

db6

Estimate time to simultaneously switch : solution of twocoupled differential equations.

Pessimistic Estimate: Assume switch in sequence

For S = 1, R = 0

Q & Q

Q & Q

τrise,Q SR− latch( ) = τrise,Q NOR2( ) + τfall,Q NOR 2( )


13

VDD

M1

M2

VDD

M3

M4

Q Q

S R

S R Qn+1

Operation

0 0 0 0 NOT allowed 0 1 1 0 set 1 0 0 1 reset 1 1 Q

n hold

NAND BASED SR LATCH

Q n +1

Q n


14

S R Qn+1

Operation

0 0 0 0 NOT allowed 0 1 1 0 set 1 0 0 1 reset 1 1 Q

n hold

NAND-basedSR Latch

S

R

Q

Q

SQ

RQ

NOTE: S, R (NAND2) = S, R (NOR2)

active low S, R active high S, R

Q n +1

Q n


15

CLOCKED LATCH AND FLIP-FLOP CIRCUITS

CLOCKED SR LATCH:

S

Q

R

Q

CK

SR LATCH

WHEN CK = 0, S, R HAVE NO INFLUENCE OF => HOLD

SET STATE: CK = 1, S = 1, R = 0RESET STATE: CK = 1, S = 0, R = 1NOT ALLOWED: CK = 1, S = 1, R = 1

ACTIVE “HIGH”

Q , Q


16HOLD STATE: CK = 0, S = X, R = XSET STATE: CK = 1, S = 1, R = 0RESET STATE: CK = 1, S = 0, R = 1NOT ALLOWED: CK = 1, S = 1, R = 1

CK

S

R

Q

“GLITCH”

WHEN “GLITCH” ON S (OR R) OCCURS DURING CK = 1,Q IS SET (OR RESET)

LEVEL SENSITIVE: WHEN CK = 1, ANY CHANGES IN S, R WILLEFFECT Q.


17

VDD

VDD

M1 M2 M3 M4

QQ

S R

CK CK

CK

CMOS IMPLEMENTATION OF CLOCKED NOR BASED SRLATCH


18

WHEN CK = 1, S, R HAVE NO INFLUENCE OF => HOLD

SET STATE: CK = 0, S = 0, R = 1RESET STATE: CK = 0, S = 1, R = 0NOT ALLOWED: CK = 0, S = 0, R = 0

ACTIVE “LOW”

CK

SR LATCH

S

Q

R

Q

Q , Q


19

VDD

VDD

M1

M2

M3

M4

Q Q

S R

CK

CK

CMOS IMPLEMENTATION OF CLOCKED NAND BASED SRLATCH


20CLOCKED JK LATCH:

NANDSR

S

R

Q

Q

J

K

CK

JKLATCH

J

K

Q

Q

CK

NO NOT ALLOWEDINPUT COMBINATION

NAND BASED CLOCKED JK LATCH


21

J

K

CK

SR LATCH

Q

QR

S

CK = 1

CK = 0 => hold

CK = 1=> active

OSC

J K Qn S R Q

n+1 Operation

0 0 0 1 1 1 0 1 hold0 0 1 0 1 1 1 0 hold0 1 0 1 1 1 0 1 reset0 1 1 0 1 0 0 1 reset1 0 0 1 0 1 1 0 set1 0 1 0 1 1 1 0 set1 1 0 1 0 1 1 0 toggle1 1 1 0 1 0 0 1 toggle

Q n Q n +1


22

J

K

CK

SR LATCH

Q

Q

R

S

NOR BASED CLOCKED JK LATCH

TO PREVENT OSICLLATION WHEN J = K = 1:

τJKP

> T1

CKCK T1

τJKP

= INPUT-OUTPUT PROP DELAY OF JK LATCH


23

VDD

VDD

QQ

K J

CK CK

CK

CMOS AOI IMPLEMENTATION NORBASED CLOCKED JK LATCH


24

JKLATCH

J = 1

K = 1

Q

Q

CK

JK TOGGLE SWIITCHJ = K = 1

Q

OUTPUT Q CHANGES ONLY ONCE PER CLOCK PERIOD

IFF τJKP

> T1

CKCK T1


25

CK

Qs

J

K

NANDSR

S

R

NANDSR

S

RQ

s

Qm

Qm

CK

MASTER-SLAVE FLIP-FLOP

USING NAND-BASED JK LATCHES

CK

Qs

J

K

Qm

Qm

CK

Qs


26

CK

QSJ

K

QM

QM

CK

QS

J

K

QM

“GLITCH”

QM

CK

QS

QS

“one’scatching”

J K Qn S R Qn+1 Operation

0 0 0 1 1 1 0 1 hold0 0 1 0 1 1 1 0 hold0 1 0 1 1 1 0 1 reset0 1 1 0 1 0 0 1 reset1 0 0 1 0 1 1 0 set1 0 1 0 1 1 1 0 set1 1 0 1 0 1 1 0 toggle1 1 1 0 1 0 0 1 toggle

Q n Q n +1

QMn = 0

QMn+1

= 1

QSn = 0 QS

n+1 = 0

This Latch is Level Sensitive!


27CMOS D-LATCH AND EDGE-TRIGGERED FLIP-FLOP

D

CK

SR LATCH

Q

QR

S

D -LATCH

D

CK Q

Q

Q

VDD V

DD

Q

CK

CK

CK

CKD-Latch Version 1

D

If CK = 1: Qn+1

= DIf CK = 0: Q

n+1 = Q

n


28

D

CK = 1

QQ

D

CK = 0

QQ


29cycle time T

tsetup

- time before the negative-CLK edge the D-input has to be stable.

thold

- time after negative-CLK edge that the D-input has to remain stable.

tclock-to-Q

- Delay from the negative-CLK edge to new value of Q output.

CLK

tsetup

thold

tclock-to-Q

D

Q

data stable


30METASTABILITY AND SYNCRONIZATION FAILURES

If data and clock do not satisfy the setup & hold time constaints of a register,then syncronization failure may occur. This due to inherent analog nature ofstorage elements.

METASTABLE STATE - indeterminate state between "1" & "0", i.e. latch isperfectly balanced between making decision for "1" or "0". In practice noisewill eventually arbitrarily push latch output to "0" or "1".

Example: register entering metastable state (shown for negative edge trigger case)

CLK

D = data4nsdelay

2 nstime

Q

timedelay = 2.2 ns

metastable point

timedelay = 2.3 ns

Q

timedelay = 2.4 ns Q

metastable point

Q

QQ


31

D

CLK

Q

D Q

CLK = 0

D Q

CLK

CLK = 1

D Q

D Q

D Q

CLK

CLK

CLK = 1

CLK = 0

Negative D - Latch

Positive D - Latch


32

D-Latch Version 2

Q

VDD

Q

VDD

CK

CK

VDD

CK

CK

D


33

DQ

m Qs

master slaveCLK

CLK CLK

CLKQ

m Qs

POSITIVE EDGE - TRIGGERED MASTER-SLAVE D FLIP-FLOP

D

FOR CLK = 0

D

1. CLK = 0: master Qm tracks current D;

slave Qs = previous D sample (Q

s is

transparent to variations in D).

2. CLK = 0 -> 1: master stores Qm = D (new

D sample).

3. CLK = 1: master passes Qm = D to slave

output Qs (Q

m and Q

s are transparent to

variations in D).

4. CLK = 1 -> 0: slave locks in new D, andmaster Q

m begins tracking D.

Qm Q

s

FOR CLK = 1Q

sQ

m


34

Negative Latch

Positive Latch

D Q

D Q

LEVEL/EDGE-SENSITIVE LATCH/REGISTER TIMING

CLK

CLK

Q

D

Q stored and available when CLK high

CLK

CLK

CLK

Q

D

Q stored and available when CLK low

CLK


35

master slave

D Qs

CLK

Qs

Qm

CLK

CLK CLK

D

Qs

Qm

CLK

Qs stored when CLK high and available when CLK high and low

Documents

EE 560 SEQUENTIAL MOS LOGIC CIRCUITSLOGIC CIRCUITS COMBINATIONAL SEQUENTIAL (non-regenerative) (regenerative) BISTABLE MONOSTABLE ASTABLE. Kenneth R. Laker, University of Pennsylvania