ECL VLSI ASIC 100K Circuit Design Optimization - HP .ECL VLSI ASIC lOOK CIRCUIT DESIGN OPTIMIZATION

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  • 1JTANDEMCOMPUTERS

    ECL VLSI ASIClOOK Circuit DesignOptimization

    Aurangzeb KhanDucLeDong NguyenBipolar VLSI Design GroupTandem VLSI

    Technical Report 88.7August 1988Part Number 16257

  • ECL VLSI ASIC

    lOOK CIRCUIT DESIGN

    OPTIMIZATION

    Aurangzeb Khan Duc Le Dong Nguyen

    Bipolar VLSI Design Group, Tandem VLSI

    Technical Report 88.7August 1988Part Number: 16257

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  • ECL VLSI ASIC lOOK' CIRCUITDESIGN OPTIMIZATION

    Aurangzeb Khan Due Le Dong Nguyen

    June 1988

    This paper illustrates the complex, inter-related design optimization choices required to achieveefficient, high speed silicon bipolar ECL VLSI ASICs. We present three possible design choicesfor ECL internal circuit design, and briefly discuss the trade-offs involved in our final choice. Wethen show the impact of this optimization on output driver circuit design, and for example, the needfor a new analytical framework to understand the lOOK performance of the chosen output circuitdesign. An analytical framework for the lOOK temperature compensation of an effective three-level series-gated ECL output driver is then presented. This analysis was developed during thedesign of the output cell of a bipolar VLSI gate array IC. Results from this analysis have beenshown to agree quite well with actual measurements and computer-aided simulations.

    Table of Contents

    Overview

    Internal Comparator DesignOutput Driver DesignCircuit Design Choices - Overview

    Input Receiver Circuit Design

    Input Receiver Circuit

    Internal Comparator Circuit Design

    Optimal ECL Internal Logic SwingStandard VBB-based Internal ComparatorCommon Mode VBB-based Internal ComparatorVrl-based Internal Comparator

    lOOK Output Driver Design - Diode Stacking Considerations

    Circuit Design Optimization - Conclusions

    lOOK Output Temperature Compensation

    ECL lOOK VOH and dVOH/dT Equations

    ECL lOOK VOL and dVOL/dT Equations

    RC/RCM Optimization

    Conclusions

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  • OVERVIEW

    Silicon bipolar ECL circuits attain fast switching speeds partially due to their small, well-controlledlogic voltage swing. Since the delay perfonnance of a digital circuit is proportional to its' logicswing, we note that excessive logic swing creates a delay penalty. However, if the logic voltageswing is too small compared to the total potential noise losses, we can attain marginal noisemargins, and consequently suffer from poor signal integrity. Thus a well-balanced logic voltageswing is optimized to provide reliable high speed operation with assured signal integrity.

    Internal Comparator Design: System level electrical signals usually contain transient noisedue to a variety of sources such as, impedance variation, reflection, crosstalk, etc. This designexample illustrates how internal circuit design can have a major impact on output driver design.Let us define input receiver and internal comparator circuit functions. An IC input receiver circuitreceives off-chip signal inputs and provides buffered output signals with well-defined voltagelevels. It also provides good driving capability for driving other circuits within the IC. This circuituses the standard ECL first level comparator reference voltage, called VBB, to arbitrate high andlow level signals from inputs. Since the incoming system level signals are coded around thisreference voltage, our design choices are restricted to utilizing to VBB reference only. On theother hand, internal comparator circuits are used to perfonn a variety of logic functions within theIC. Such circuits receive signals from, and source signals to, other logic circuits within the IC.Since we have control of both the source and destination circuits, we can design any appropriatelogic swing, high and low levels, and comparator reference voltages. There are three options forinternal comparator circuit design:

    1. Use standard VBB as Vr1. (Fig 1)

    2. Use standard VBB and a common mode resistor offset. (Fig 2)

    3. Use non-standard Vrl optimized to provide comparable VN1vIH, VNML. (Fig 3)

    The first choice ensures signal compatibility with off-chip inputs. This enables a gate arrayarchitecture design which can accept off-chip inputs to any arbitrary location within the Ie, thusproviding usage flexibility, and reduced output driver cells' utilization. However, this techniquemakes the total logic swing too large, thus incurring a delay penalty.

    The second choice also ensures signal compatibililty with off-chip inputs, thus providing usageflexibility, etc., as discussed above. Since the common mode offset resistor is used to tune thetotal logic swing to an optimal level, this technique does not incur a delay penalty. However, theneed for an extra component raises the silicon real estate cost of this solution, and also adds torouting complexity.

    In the third design choice, we develop and use a non-standard ECL reference voltage, called Vrl,to optimize the total voltage swing without requiring a common mode offset resistor. This .:hoicehas the added benefit of facilitating three-level lOOK series-gating, thus providing enhanced circuitfunctionality at no incremental power. However, this choice restricts the ability of the arrayarchitecture to allow off-chip signal inputs to any location inside the IC, unless suitable CADprograms are developed to provide appropriate reference voltages which depend upon the source ofinput signals. Further, this technique requires two separate voltage regulators, versus one in theftrst two cases.

    However, this approach ensures an optimal logic swing, eliminates the need for repetitive commonmode resistors, and provides an improved ECL three-level series-gating perfonnance. Our choicein this regard was further strengthened by our ability to get CAD software support which madeappropriate reference selection an automated function. Consequently, we reduced the total logic

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  • swing by 30%. This reduction is achieved without any loss in noise margin. It leads to a fasterpropagation time for no incremental power.

    Output Driver Design: Having selected the non-standard Vrl-based circuit as our internal ECLdesign, we find that this significantly channels our output driver design choices, especially for aseries-gated lOOK ECL output driver.

    In the lOOK output driver (Fig 3), Vrl cannot be applied directly to the output current switch firstlevel reference transistor, since this introduces a base/collector saturation hazard for the inputtransistor. Thus Vr2, which is the internal second level reference, is applied as the first levelreference voltage.

    Vr2 =Vr1 - Vbe(Q9)Therefore Vr3 becomes the second-level reference. However, note that Vr3 is offset from Vrl by2 Vbe, and thus represents a true third-level series-gating reference.

    Vr3 =Vr2 - Vbe(Q13)In a conventional ECL output driver design, Vr3 is not a viable voltage reference because threelevel deep series gating is not allowable. This follows from diode stacking considerations, asdescribed later. We are able to overcome this constraint only because we developed a currentmirror based comparator current mechanism. This allows an acceptable diode stacking, since acurrent mirror reduces ECL VEE min. requirements by -600 mV under nominal condition.

    Diode stacking refers to a minimum ECL VEE requirement which depends on the number of seriesgating stages utilized in comparator design. In ECL, all reference voltage - Vrl, Vr2, Vr3, etc. -are developed with respect to ECL VCC. Further, all current source voltages are developed withrespect to ECL VEE. The current source transistor is set-up so that its' base follows ECL VEE,while its' collector follows ECL VCe. If ECL VCC - ECL VEE falls below a critical minimum,defined as the diode stack, the current source can saturate. Such saturation causes unacceptablecircuit behaviour. Fig. 4 represents the conventional lOOK current source based approach. In thiscase,

    ECL VEE min. = -4.48 V - 0.12 V = -4.60 VWhere 4.48V is the ECL VEE applied to the IC and 0.l2V is the Ohmic voltage loss in the Iepackage.

    Fig. 3 represents our lOOK current mirror based approach. In this case,

    ECL VEE min. =-3.92 V - 0.12 V = -4.04 Vwhich is well below the ECL VEE min. requirement for commercial range lOOK ECL VLSI ICs,and therefore represents an acceptable design.

    Circuit Design Choices Overview: In this section, the basic theme of this paper - designoptimization inter-relationships - has been presented in overview form. The following sectionsdiscuss the design trade-offs in more detail.

    INPUT RECEIVER CIRCUIT DESIGN

    ECL signals transmitted across digital systems' interconnect media follow well-defmed, standardECL VOH and VOL levels. On the driving side, ECL output drivers deliver digital informationencoded within specific high and low level voltage ranges. Usually however, such signals alsopick up unwanted transient noise spikes due to PCB impedance variation, reflection, crosstalk, etc.

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  • On the receiving side, ECL receiverlbuffer circuits decode incoming system voltages and providebuffered driving capability within an IC. The receiverlbuffer comparator circuits arbitrate high andlow level inputs with respect to a reference voltage centred around the nominal ECL logic voltageswing. This voltage level, commonly called VBB, ensures adequate high and low level noisemargins, when nominal VIR, Vn... levels are input to the IC.

    Input Receiver Circuit: A conventional ECL input receiver is presented in Fig. 1. This ECLswitch performs a buffer/driver function. It receives off-chip signal in

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