ECE301 - Course Introduction.ppt

ECE 301 - VLSI System Design(Fall 2012)

Course Information

VITU N I V E R S I T Y

Course Information

Prof.S.SivananthamSchool of Electronics Engineering

VIT UniversityVellore, Tamilnadu. India

E-mail: [email protected]

Course outline

CMOS Logic Design

Circuit Characterization and Performance estimation

Verilog HDL Basics

Digital System Design using Verilog HDL

Introduction to Timing Analysis

ECE301 VLSI System Design FALL 2012 S.Sivanantham

CMOS Logic Design

Circuit Characterization and Performance estimation

Verilog HDL Basics

Digital System Design using Verilog HDL

Introduction to Timing Analysis

Course Outcome (i)

ability to apply knowledge of mathematics, science, and engineering in thedesign, and analysis and modeling of digital integrated circuits.

ability to describe and model digital design using a hardware descriptionlanguage.

ability to design and conduct experiments in digital design using VerilogHDL and able to illustrate the outcome of the design.

ability to design and analyze the performance (speed, Power, Area) ofCMOS digital integrated circuits for different design specifications.

knowledge on Verilog HDL constructs and operators accepted in logicsynthesis and show how logic synthesis tool interprets these constructs.

After successful completion of this course, you will have the


ability to apply knowledge of mathematics, science, and engineering in thedesign, and analysis and modeling of digital integrated circuits.

ability to describe and model digital design using a hardware descriptionlanguage.

ability to design and conduct experiments in digital design using VerilogHDL and able to illustrate the outcome of the design.

ability to design and analyze the performance (speed, Power, Area) ofCMOS digital integrated circuits for different design specifications.

knowledge on Verilog HDL constructs and operators accepted in logicsynthesis and show how logic synthesis tool interprets these constructs.

Course Outcome (ii)

Ability to compute gate sizes on a path to optimize the path delay usinglogic effort.

Ability to analyze a given problem in Verilog HDL

Ability to develop problem-solving skills in order to be able to successfullyapproach a digital design project of medium to high complexity in the finalsemester.

Ability to identify career paths and requisite knowledge and skills forcareer change/higher studies towards Microelectronics Engineering.

Ability to gain knowledge of contemporary issues on modern VLSI Designthrough various websites.

Ability to use modern EDA tools to Simulate and Synthesize the digitaldesigns to verify their functionality and analysis its performance.


Ability to compute gate sizes on a path to optimize the path delay usinglogic effort.

Ability to analyze a given problem in Verilog HDL

Ability to develop problem-solving skills in order to be able to successfullyapproach a digital design project of medium to high complexity in the finalsemester.

Ability to identify career paths and requisite knowledge and skills forcareer change/higher studies towards Microelectronics Engineering.

Ability to gain knowledge of contemporary issues on modern VLSI Designthrough various websites.

Ability to use modern EDA tools to Simulate and Synthesize the digitaldesigns to verify their functionality and analysis its performance.

Prerequisite

Semiconductor Devices and Circuits

Digital Logic Design


Course Resources

Course materials are available in VIT intranet(http://intranet.vit.ac.in)

Resource Syllabus Course updates Tutorials Lecture notes, supplemental readings Homework assignments

Stay connected with to get updates and more usefulinfo related to the course.

Facebook group: (VLSI System Design Fall2012-13) Link to the group: http://www.facebook.com/groups/vsd2012/

CHECK IT OFTEN


Course materials are available in VIT intranet(http://intranet.vit.ac.in)

Resource Syllabus Course updates Tutorials Lecture notes, supplemental readings Homework assignments

Stay connected with to get updates and more usefulinfo related to the course.

Facebook group: (VLSI System Design Fall2012-13) Link to the group: http://www.facebook.com/groups/vsd2012/

CHECK IT OFTEN

Course Plan

Lectures

Problem Solving

Home Assignments

Lab assignments to Simulate and synthesize the Digitalcircuits using EDA tools like Modelsim, Xilinx ISE andAltera Quartus II d by Verilog HDL using EDA tools

Group Project


Lectures

Problem Solving

Home Assignments

Lab assignments to Simulate and synthesize the Digitalcircuits using EDA tools like Modelsim, Xilinx ISE andAltera Quartus II d by Verilog HDL using EDA tools

Group Project

Evaluation and Grading

CAT– 1 (15 %) – Module 3 and 4

CAT – 2 (15 %) – Modules 1 and 5

Lab assignments (20%) - (individual or group of 2-3students, depends on assignments)

• Assignment -1 (5 %)



TEE (50 %)


CAT– 1 (15 %) – Module 3 and 4

CAT – 2 (15 %) – Modules 1 and 5

Lab assignments (20%) - (individual or group of 2-3students, depends on assignments)




TEE (50 %)

No Re-exam will be conducted for Absentees

Assignment

Assignments will either be individual or in pairs

Read the assignment to see!

Assignment due at beginning of class

10% penalty for each late period of 24 hours

Not accepted >72 hours after deadline

ECE301 VLSI System Design FALL 2012 S.Sivanantham 9

Lab Assignments

Lab Assignments using the Xilinx/Altera VLSI designsoftware will be an integral part of this course.

There are no separate lab times.

Details of each assignment will be posted on the coursewebsite/intranet course page.


Our Policy

Attendance and Conduct in Class: Students are expected toattend class and be bright and cheerful with lots of questions.It will be difficult to perform well in this class withoutattending the lectures.

Cheating in any form will not be tolerated! This includescopying homework, copying circuit design files, cheating onexams, or any other form of unethical behavior.


Attendance and Conduct in Class: Students are expected toattend class and be bright and cheerful with lots of questions.It will be difficult to perform well in this class withoutattending the lectures.

Cheating in any form will not be tolerated! This includescopying homework, copying circuit design files, cheating onexams, or any other form of unethical behavior.

Course Tools

Industry-standard design tools:

Modelsim HDL Simulation Tools (Mentor)/ XilinxISE/Altera Quartus II for FPGA based Design andImplementation (for Lab assignments)

[optional] Virtuoso, Spectre and Assura from Cadence(based on module 1 and 2)

Tutorials will be available for all the tools

These tools will be required as part of homework/ Labassignments

Can do it on own time (within deadline)

ECE301 VLSI System Design FALL 2012 S.Sivanantham 12

Industry-standard design tools:

Modelsim HDL Simulation Tools (Mentor)/ XilinxISE/Altera Quartus II for FPGA based Design andImplementation (for Lab assignments)

[optional] Virtuoso, Spectre and Assura from Cadence(based on module 1 and 2)

Tutorials will be available for all the tools

These tools will be required as part of homework/ Labassignments

Can do it on own time (within deadline)

Required Text Books

Neil H. E. Weste and David Harris, CMOSVLSI Design: A Circuits and SystemsPerspective, Pearson Education, 3/e2006


Samir Palnitkar, Verilog® HDL: A Guide toDigital Design and Synthesis, PHI, SecondEdition,2004.

References

Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic,Digital Integrated Circuits: A Design Perspective, PrenticeHall India, 2nd Ed, 2002.

Sung-Mo Kang & Yusuf Leblebici, “CMOS DigitalIntegrated Circuits –Analysis and Design”, Tata McGraw-Hill, New Delhi, 2005

John P.Uyemura, “CMOS Logic Circuit Design” , SpringerInternational Edition.2005

J. Bhasker, “A Verilog HDL Primer”, BP Publications.


Jan M. Rabaey, Anantha Chandrakasan, Borivoje Nikolic,Digital Integrated Circuits: A Design Perspective, PrenticeHall India, 2nd Ed, 2002.

Sung-Mo Kang & Yusuf Leblebici, “CMOS DigitalIntegrated Circuits –Analysis and Design”, Tata McGraw-Hill, New Delhi, 2005

John P.Uyemura, “CMOS Logic Circuit Design” , SpringerInternational Edition.2005

J. Bhasker, “A Verilog HDL Primer”, BP Publications.

Study Guidelines

Active Participation in the class

Doing Home Assignments on time

Utilize the FPGA/SOPC Lab (Room No:TT237) and ASICDesign Laboratory (Room No:TT237A) to simulate andsynthesize the Digital Design described by Verilog HDL andAnalyze the CMOS circuits using Cadence EDA tools.

The students are encouraged to use various kind of EDA toolsavailable in the lab.


Active Participation in the class

Doing Home Assignments on time

Utilize the FPGA/SOPC Lab (Room No:TT237) and ASICDesign Laboratory (Room No:TT237A) to simulate andsynthesize the Digital Design described by Verilog HDL andAnalyze the CMOS circuits using Cadence EDA tools.

The students are encouraged to use various kind of EDA toolsavailable in the lab.

Study Guidelines

Participation in guest lectures will help the students tounderstand the contemporary issues

Students are encouraged to refer the following website inaddition to their class participation and reading required textsand reference books.• http://www.vlsi-design.net/• www.asic-world.com• http://www.vlsichipdesign.com• http://nptel.iitm.ac.in/ ( A video course on “VLSI Circuits” by Prof.

S.Srinivasan, A web course on “VLSI Design” by Prof. A.N.Chandorkar will be really helpful)

• http://ocw.mit.edu/courses/ (MIT OpenCourseWare is a freepublication of MIT course materials that reflects almost all theundergraduate and graduate subjects taught at MIT)


Participation in guest lectures will help the students tounderstand the contemporary issues

Students are encouraged to refer the following website inaddition to their class participation and reading required textsand reference books.• http://www.vlsi-design.net/• www.asic-world.com• http://www.vlsichipdesign.com• http://nptel.iitm.ac.in/ ( A video course on “VLSI Circuits” by Prof.

S.Srinivasan, A web course on “VLSI Design” by Prof. A.N.Chandorkar will be really helpful)

• http://ocw.mit.edu/courses/ (MIT OpenCourseWare is a freepublication of MIT course materials that reflects almost all theundergraduate and graduate subjects taught at MIT)


Documents

ECE301 - Course Introduction.ppt