27
Charlie Charlie Chung Chung-Ping Chen -Ping Chen ECE 902 Simulation, Modeling, and Optimization for VLSI ECE 902 Simulation, Modeling, and Optimization for VLSI ECE 902 ECE 902 Instructor: Instructor: Charlie Charlie Chung Chung-Ping Chen, -Ping Chen, chen chen@engr engr.wisc wisc.edu edu Office hour: 3-4pm T,R, 3421 Office hour: 3-4pm T,R, 3421 Engr Engr Hall Hall TA: TA: Ting Ting- Yuan Yuan Wang, Wang, wangt wangt@cae cae.wisc wisc.edu edu Class Web Site: Class Web Site: http http:// :// www www.cae cae.wisc wisc.edu edu /~ece902/ /~ece902/ Text: Text: “Introduction to Algorithms (MIT Electrical Engineering and Computer Science Series)" by Thomas H. “Introduction to Algorithms (MIT Electrical Engineering and Computer Science Series)" by Thomas H. Cormen Cormen, Charles E. , Charles E. Leiserson Leiserson , Ronald L. , Ronald L. Rivest Rivest. "Electronic Circuit and System Simulation Methods”, by Lawrence T. Pillage, Ronald A. "Electronic Circuit and System Simulation Methods”, by Lawrence T. Pillage, Ronald A. Rohrer Rohrer, Chandramouli Visweswariah Chandramouli Visweswariah

ECE 902 Simulation, Modeling, and Optimization for VLSIhomepages.cae.wisc.edu/~ece902/LectureNotes/Introduction/slides1.… · Simulation, Modeling, and Optimization for VLSI

  • Upload
    dinhnhi

  • View
    223

  • Download
    2

Embed Size (px)

Citation preview

CharlieCharlie Chung Chung-Ping Chen-Ping Chen

ECE 902Simulation, Modeling, andOptimization for VLSI

ECE 902Simulation, Modeling, andOptimization for VLSI

ECE 902ECE 902

ää Instructor:Instructor:ää Charlie Charlie ChungChung-Ping Chen,-Ping Chen, chen chen@@engrengr..wiscwisc..edueduää Office hour: 3-4pm T,R, 3421 Office hour: 3-4pm T,R, 3421 Engr Engr HallHall

ää TA:TA:ää TingTing--Yuan Yuan Wang, Wang, wangtwangt@@caecae..wiscwisc..eduedu

ää Class Web Site: Class Web Site: http http://://wwwwww..caecae..wiscwisc..eduedu/~ece902//~ece902/

ää Text:Text:ää “Introduction to Algorithms (MIT Electrical Engineering and Computer Science Series)" by Thomas H.“Introduction to Algorithms (MIT Electrical Engineering and Computer Science Series)" by Thomas H.

CormenCormen, Charles E., Charles E. Leiserson Leiserson, Ronald L., Ronald L. Rivest Rivest..ää "Electronic Circuit and System Simulation Methods”, by Lawrence T. Pillage, Ronald A."Electronic Circuit and System Simulation Methods”, by Lawrence T. Pillage, Ronald A. Rohrer Rohrer,,

Chandramouli VisweswariahChandramouli Visweswariah

Conferences & JournalsConferences & Journals

ää IEEE Transactions on VLSI Systems:IEEE Transactions on VLSI Systems:httphttp://://ieeexploreieeexplore..ieeeieee..orgorg//lpdocslpdocs/epic03//epic03/

ää IEEE Transactions on CAD of IC’sIEEE Transactions on CAD of IC’sää IEEE Journal of Solid State CircuitsIEEE Journal of Solid State Circuitsää IEEE VLSI Circuits SymposiumIEEE VLSI Circuits Symposiumää Journal of Electronic TestingJournal of Electronic Testingää ACM Design Automation Conference: ACM Design Automation Conference: httphttp://://wwwwww..acmacm..orgorgää IEEE International Conference on CADIEEE International Conference on CADää IEEE Solid State Circuits ConferenceIEEE Solid State Circuits Conferenceää International symposium on Low-Power Electronics & DesignInternational symposium on Low-Power Electronics & Designää IEEE Conference on Computer IEEE Conference on Computer DeisngDeisngää IEEE International Test ConferenceIEEE International Test Conference

ECE 902ECE 902

ää TutorialsTutorialsää There will be a few tutorial sessions at CPLEX SoftwareThere will be a few tutorial sessions at CPLEX Software

ää AssignmentsAssignmentsää Approximated 6-10 assignments will be given. The assignments will be Approximated 6-10 assignments will be given. The assignments will be

due at the beginning of the class the due date specified. No latedue at the beginning of the class the due date specified. No lateassignments will be accepted expect under extreme non-academicassignments will be accepted expect under extreme non-academiccircumstances.circumstances.

ää Preparing for heavy coding lifePreparing for heavy coding life

ää Quiz: Around one for every two weeksQuiz: Around one for every two weeksää Project:Project:

ää One final project performed by a student is required.One final project performed by a student is required.ää Topics open but need to discuss with meTopics open but need to discuss with me

ECE 902ECE 902

ää Exams: There will be no midterm and final exam.Exams: There will be no midterm and final exam.

ää Grading: Homework 30%, Project 30%, Quiz 40%Grading: Homework 30%, Project 30%, Quiz 40%

ää Any form of cheating will be heavily penalized and reported toAny form of cheating will be heavily penalized and reported tothe Dean of students and may result in a failing grade and more.the Dean of students and may result in a failing grade and more.

ää Instructor reserves the right to change project requirements.Instructor reserves the right to change project requirements.

Course OutlineCourse Outline

You will learnYou will learn

ää VLSI Modeling, Simulation, and OptimizationVLSI Modeling, Simulation, and Optimizationää Modeling: RLC Parameter Extraction, Finite element method Full-Modeling: RLC Parameter Extraction, Finite element method Full-

wave Simulationwave Simulationää Simulation: Matrix skills and SPICE stuffSimulation: Matrix skills and SPICE stuffää Optimization: Algorithm and mathematical programmingOptimization: Algorithm and mathematical programming

ää Application: Physical design applications such as routing andApplication: Physical design applications such as routing andpartitioningpartitioning

Work hard?Work hard?

ää Good job opportunities: M.S. Salary > 65k in Silicon ValleyGood job opportunities: M.S. Salary > 65k in Silicon Valleyää Good research opportunities: VLSI is a very active research area, UniversityGood research opportunities: VLSI is a very active research area, University

job & Research centers (IBM, Intel, Lucent), job & Research centers (IBM, Intel, Lucent), PhPh.D. salary ~95K.D. salary ~95Kää Why do you need to do exceptional well in this courseWhy do you need to do exceptional well in this course

ää You can claim you are good in VLSI during interviewYou can claim you are good in VLSI during interview

ää You will have overall understanding and practical design experience in VLSIYou will have overall understanding and practical design experience in VLSIdesigndesign

ää You are in good position to get a recommendation letter from meYou are in good position to get a recommendation letter from me

ää You will learn more than what’s in the textbookYou will learn more than what’s in the textbook

ää You can maintain your straight “A” family traditionYou can maintain your straight “A” family tradition

ää ......

How to succeedHow to succeed

ää Work hard, study hardWork hard, study hardää Team workTeam work

ää Learning, discussion, join projectLearning, discussion, join project

ää Do it (not only study it)- run simulationsDo it (not only study it)- run simulationsää Do some researchDo some research

ää Journals or conferenceJournals or conferenceää Read magazines: EETIMES, EDN, ….Read magazines: EETIMES, EDN, …. www www..eetimeseetimes..comcom

ää Look at stock newsLook at stock news

Course projectsCourse projects

ää There will be several potential topics to choose and will beThere will be several potential topics to choose and will beannounced soonannounced soon

ää You can also suggest a project you likeYou can also suggest a project you like

Project proposalProject proposal

ää Project proposal (includes paper survey) by 15 Oct, 30% finalProject proposal (includes paper survey) by 15 Oct, 30% finalgradegrade

ää Project presentation in the last week of classProject presentation in the last week of classää 12-15 minute presentation12-15 minute presentationää 25% of final grade25% of final grade

ää Project report due by the last day of class Project report due by the last day of classää 45% of final grade45% of final grade

Microprocessor Design Challenges

ää High performance ( > 500 High performance ( > 500 MhzMhz))ää Low cost (< $100)Low cost (< $100)

ää Low power consumption (< 10W mobile)Low power consumption (< 10W mobile)

ää More functionality (KNI MMX)More functionality (KNI MMX)ää Shorter time to market (< 18 months)Shorter time to market (< 18 months)

ää Satisfies different market segments (server, sub-Satisfies different market segments (server, sub-$1000)$1000)

ää CompetitionCompetitionää ….….

Mission Impossible!

Mission Impossible!

Deal With It!

ää Higher clock frequenciesHigher clock frequenciesää New processes: 0.18 micron, copperNew processes: 0.18 micron, copper

ää Architecture levelArchitecture levelää SuperscalarSuperscalar, super-pipeline, out-of-order execution,, super-pipeline, out-of-order execution,

speculative execution, EPIC, VLIW, ILP, speculative execution, EPIC, VLIW, ILP, multimulti-thread-thread

ää Circuit levelCircuit levelää Aggressive dynamic circuits synthesisAggressive dynamic circuits synthesisää Sizing, parallel re-powering, logic minimizationSizing, parallel re-powering, logic minimization

ää Physical DesignPhysical Designää Performance-driven place and route, floorplaningPerformance-driven place and route, floorplaning

ää Wire-sizing, buffer-sizing, buffer-insertionWire-sizing, buffer-sizing, buffer-insertion

Size of Team ExplodesSize of Team Explodes

Process Overview

ää New process (0.18 um)New process (0.18 um)ää High High aspectaspect ratio ratioää Low sheet rho (resistance)Low sheet rho (resistance)ää Low-Low-εε dielectric (capacitance) (3.55 vs. 4.10) dielectric (capacitance) (3.55 vs. 4.10)ää Good Good ElectromigrationElectromigration property propertyää 6 metal layers6 metal layers

ää M1 tight pitch for density (X-cap)M1 tight pitch for density (X-cap)ää M2-M3 middle pitch for density & performance (X-cap)M2-M3 middle pitch for density & performance (X-cap)ää M4-M6 high pitch (low resistance) for performance (Inductance)M4-M6 high pitch (low resistance) for performance (Inductance)

ää FutureFutureää Copper - Less resistance more inductance effectCopper - Less resistance more inductance effectää SOI - the M1 coupling strangeSOI - the M1 coupling strange

0.25 Micron, 5 Layer Technology0.25 Micron, 5 Layer Technology

IEDM 96IEDM 96

M6

M5

M4

M3

M2

M1

0.18 Micron, 6 Layer Technology0.18 Micron, 6 Layer Technology

IEDM 99IEDM 99

Analyze this!!Analyze this!!

5

10

15

20

25

120 130 140 150 160 170 180 190 200LGATE (nm)

Ga

te D

ela

y (p

sec)

Vdd = 1.5V

Vdd = 1.3V

Gate Delay .v.s. ScalingGate Delay .v.s. Scaling

IEDM 99IEDM 99

0

20

40

60

80

100

120

0.0 0.5 1.0 1.5 2.0 2.5 3.0Pitch ( µ m)

She

et R

ho (

moh

m/s

q)

Al, 0.25um, ref [6]Al, 0.18um, this workCu, 0.22um, ref [7]

Interconnect Resistance GrowsSuper LinearlyInterconnect Resistance GrowsSuper Linearly

IEDM 99IEDM 99

Interconnect Delay Trend

IEDM 95

0

0.5

1

1.5

2

2.5

3

0.35 0.6 0.8 1 1.5

Technology Generation (micron)

Rel

ativ

e R

C D

elay

IEDM 99IEDM 99

2929

Interconnect Complicated DesignFlow

ArchitectureArchitecture

RTLRTL

LogicLogic

GateGate

LayoutLayout

Over tens ofOver tens ofiterations!iterations!

Signal IntegrityA new design challenge

CrossCapCrossCap

1

2

CrosstalkCrosstalk

Inductance effect emerging

ää An old clock treeAn old clock treeää FreqFreq domain up to 1Ghz domain up to 1Ghzää PVL and PRIMA with orderPVL and PRIMA with order

16 find the exact16 find the exact

ää A newerA newer ckt ckt, a section of, a section ofpower gridpower gridää Has L’sHas L’sää PVL and PRIMA with 60thPVL and PRIMA with 60th

orderorderää Frequencies more than 0.6Frequencies more than 0.6

GhzGhz are not covered are not covered

Frequency (Ghz)

0 0.5 1 1.5 2-3

PRIMA

PVL|H(jw)|

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

|H(jw)|

PRIMA=PVL=EXACT

EXACT

Model order reduction

ää We need We need efficient toolsefficient tools to analyze the interconnect to analyze the interconnectdominant circuits (power grids, packages etc.) accuratelydominant circuits (power grids, packages etc.) accuratelyin a reasonable amount of timein a reasonable amount of time

⇒⇒ Promising Promising Model Order ReductionModel Order Reduction (MOR) techniques (MOR) techniques

Nonlinear Elements

Linear Elements

Nonlinear Elements

Reduced Model

Power ConsumptionPower Consumption

ääP P ∼∼ C V C V22 f, where f, whereääC = Capacitance ~ AreaC = Capacitance ~ Area

ääV = Supply VoltageV = Supply Voltageääf = Operation Frequencyf = Operation Frequency

Power TrendPower Trend

Supply Voltage TrendsSupply Voltage Trends

Deal With It!

ää InterconnectInterconnectää Wire- and Repeater- SizingWire- and Repeater- Sizing

ää Repeater InsertionRepeater Insertion

ää Performance-driven noise-aware routingPerformance-driven noise-aware routingää New material: Low resistance (Cooper), Low k materialNew material: Low resistance (Cooper), Low k material

(SiN2)(SiN2)

ää GatesGatesää Gate SizingGate Sizing

ää New Circuit Exploration - Dynamic Circuit, Dual VtNew Circuit Exploration - Dynamic Circuit, Dual Vt

ää ….….

Standby Power TrendStandby Power Trend

Threshold Voltage v.s. Supply VoltageThreshold Voltage v.s. Supply Voltage

Vt v.s. Delay

Dual Vt circuitDual Vt circuit

High High VtVt

Low Low VtVt

Aggressive circuit stylesAggressive circuit styles

Clock delayed and Self-resettingdynamic circuitsClock delayed and Self-resettingdynamic circuits

Process limitations

Intel 4004 Micro-Processor Intel 4004 Micro-Processor

Manual design

Intel Pentium (II) microprocessorIntel Pentium (II) microprocessor

With Design

Automation

Silicon in 2010Silicon in 2010

Die Area: 2.5x2.5 cmVoltage: 0.6 VTechnology: 0.07 µµ m

Density Access Time(Gbits/cm2) (ns)

DRAM 8.5 10DRAM (Logic) 2.5 10SRAM (Cache) 0.3 1.5

Density Max. Ave. Power Clock Rate(Mgates/cm2) (W/cm2) (GHz)

Custom 25 54 3Std. Cell 10 27 1.5

Gate Array 5 18 1Single-Mask GA 2.5 12.5 0.7

FPGA 0.4 4.5 0.25

Deal with complexityDeal with complexity

ää More handsMore handsää Abstraction and design reuseAbstraction and design reuse

ää Use logic gates instead of simple transistorsUse logic gates instead of simple transistors

ää Build library which can be repeatedly reused (standard cell)Build library which can be repeatedly reused (standard cell)

ää Design AutomationDesign Automationää Mapping logic specification to library: Logic SynthesisMapping logic specification to library: Logic Synthesis

ää Automatic Layout: Physical designAutomatic Layout: Physical design

Next WeekNext Week

ää Read Chapter 1,2 of the simulation bookRead Chapter 1,2 of the simulation bookää Read Simulation Note #1, #2Read Simulation Note #1, #2

Homework #1Homework #1

ää Write a C or C++ code toWrite a C or C++ code toää Randomly generate matrices from 2x2 to 400x400 and aboveRandomly generate matrices from 2x2 to 400x400 and above

ää Solve it by Solve it by GaussianGaussian elimination elimination

ää Report the runtime v.s. matrix size on SUN machinesReport the runtime v.s. matrix size on SUN machinesää Run SPICE for Figure 6.12 in the simulation book and report the transientRun SPICE for Figure 6.12 in the simulation book and report the transient

response response waveformwaveformää Use ~Use ~chenchen/spice3 or /spice3 or hspice hspice on CAE Sun workstationson CAE Sun workstations

ää Due next Wednesday by the class startDue next Wednesday by the class startää Homework submission:Homework submission:

ää You should submit a paper version and and electronic version to TAYou should submit a paper version and and electronic version to TA