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ECE 6050: Advanced Microprocessor Applications

Final Project Report

Fall 2010

Prof. Bradley Bazuin

David VandeBunte, Hussein Kassem, Yuan Gao

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MPC to VME Board Interface Unit1

Features Supporting IP

• Bridges the gap between a fully- synchronous

MPC563 interface and the asynchronous

VME64x bus.

• MPC563 to VME64x bus interface capable of

acting as an interrupter or bus master.

• VME Geographical Addressing, Bus Arbitration,

and Priority Interrupts

• VME A32, D32 memory accesses.

• Dual port SDRAM memory controller for the

Micron MT48LC32M8A2

• Nine tests to verify the operation of the BIU and

connected components.

• VME64x bus master emulator runs four of the

BIU tests.

• MPC 563 bus master emulator initiates five of

the nine BIU tests.

SDRAM

Controller

MPC-VME BIUMPC 563

Processor

VME

BUS

MT48LC32M8A2

Figure 1: Basic System Block Diagram

1 This report is partially modeled after the MT48LC32M8A2 SDRAM datasheet, further specifications in

DesignDocumentation.pdf, and occasional considerations for completeness.

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Pin Designations Table 1: MPC 563 Master Emulator Pin Descriptions (detailed)

Pin Name Type Description

CLK in This clock is used by the MPC563 to drive the tests in this master and run

the test counter.

ADDR out Bus address. Bus operation is determined by Freescale.2

DATA inout Data bus. Bus operation is determined by Freescale.

RDWR out Read Write. Bus operation is determined by Freescale.

CHIP_SEL out Chip Select. Bus operation is determined by Freescale.

BURST_N out Start Burst Transfer. Bus operation is determined by Freescale.

BDIP_N out Continue Burst Transfer. Bus operation is determined by Freescale.

TS_N in Transfer Start. Bus operation is determined by Freescale.

TA_N in Transfer Acknowledge. Bus operation is determined by Freescale.

TEA_N in Transfer Error Acknowledge. Bus operation is determined by Freescale.

RST_N in Reset signal for this device, active low.

TEST_CNT out The current test count, used by the VME master to decide what test

signals to output

Table 2: BIU Pin Descriptions (general)

Pin Name Type Description

MAIN_CLK in The 100 MHz clock used by most components in the BIU.

MPC_CLK in The interface to the MPC is treated as source-

synchronous, as discussed in class.

MPC_563_ADDR

MPC_563_DATA_IN

MPC_563_DATA_OUT

MPC_563_RDWR

MPC_563_CS

MPC_563_BURST_N

MPC_563_BDIP_N

MPC_563_TS_N

MPC_563_TA_N

MPC_563_TEA_N

MPC_563_OE

in

out

in

in

in

in

in

in

out

out

in

The interface from the MPC563 to the BIU. This interface

is specified by the MPC563 datasheet.

MPC_VME_DATA_IN

MPC_VME_DATA_OUT

MPC_VME_DATA_OE

MPC_VME_DS_N

MPC_VME_DTACK_N

MPC_VME_ADDR

MPC_VME_AS_N

in

out

out

out

in

out

out

The interface from the MPC563 to the VME bus, set by the

VME bus specification. Unlike the VME interface to the

SDRAM, this set of pins allows the MPC563 to act as an

interrupter on the VME priority interrupt bus.

2 See the manual “MPC561/MPC563 Reference Manual” distributed by Freescale for further details.

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MPC_VME_AM

MPC_VME_WRITE_N

MPC_VME_LWORD_N

MPC_VME_RETRY_N

MPC_VME_BERR_N

MPC_VME_BUS_OE

MPC_VME_BUSC_BBUSY_N

MPC_VME_BUSC_BBUSY_OE_N

MPC_VME_BUSC_BG_N

MPC_VME_BUSC_BR_N

MPC_VME_IACK_N

MPC_VME_IRQ_N

MPC_VME_IACKIN_N

MPC_VME_IACKOUT_N

MPC_VME_ADDR_IN

MPC_VME_DTACK_OUT_N

MPC_VME_SLV_BUS_OE

out

out

out

in

in

out

out

out

in

out

in

out

in

out

in

out

out

SDRAM_VME_DATA_IN

SDRAM_VME_DATA_OUT

SDRAM_VME_DATA_OE

SDRAM_VME_DS_N

SDRAM_VME_DTACK_N

SDRAM_VME_ADDR

SDRAM_VME_AS_N

SDRAM_VME_AM

SDRAM_VME_WRITE_N

SDRAM_VME_IACKIN_N

SDRAM_VME_IACKOUT_N

SDRAM_VME_LWORD_N

SDRAM_VME_RETRY_N

SDRAM_VME_BERR_N

SDRAM_VME_BUS_OE

in

out

out

in

out

in

in

in

in

in

out

in

out

out

out

The interface between the SDRAM Controller and the VME

bus.

SDRAM_BA

SDRAM_DATA_IN

SDRAM_DATA_OUT

SDRAMC_DATA_OE

SDRAM_DQM

SDRAM_CKE

SDRAM_ADDR

SDRAM_WE_N

SDRAM_RAS_N

SDRAM_CAS_N

SDRAM_CS_N

out

in

out

out

out

out

out

out

out

out

out

The pins that connect the SDRAM Controller to the

MT48LC32M8A2 SDRAM.

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Table 3: VME Components Pin Descriptions (general)

Pin Name Type Description

CLK In The 16 MHz clock that the VME master runs on.

VME_MSTR_DATA_IN

VME_MSTR_DATA_OUT

VME_MSTR_DATA_OE

VME_MSTR_DS_N

VME_MSTR_DTACK_N

VME_MSTR_ADDR

VME_MSTR_AS_N

VME_MSTR_AM

VME_MSTR_WRITE_N

VME_MSTR_IACK_N

VME_MSTR_IRQ_N

VME_MSTR_IACKIN_N

VME_MSTR_IACKOUT_N

VME_MSTR_LWORD_N

VME_MSTR_RETRY_N

VME_MSTR_BERR_N

VME_MSTR_BBUSY_N

VME_MSTR_BBUSY_OE_N

VME_MSTR_BG_N

VME_MSTR_BR_N

in

out

out

out

in

out

out

out

out

out

in

in

out

out

in

in

out

out

in

out

The interface to the VME bus from the VME master. These pins

allow the master to act as an interrupt handler.

TEST_CNT In From the MPC563, to determine what test to run, or wait.

BUSC_CLK

BUSC_BBUSY_N

BUSC_BG_N

BUSC_BR_N

RST_N

in

in

out

in

in

The pins for the dedicated VME bus controller (arbiter of bus

control).

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Functional Block Diagram

Figure 2: Conceptual Block Diagram

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Functional Description

VME Bus

The operation of the VME Bus is based on several sources, including Grantner’s notes, online sources,

and the original VME Spec. For the single read and write cycles, the basic VME dialog is available online,

with the minimal timing constraints available there:

Figure 3: Single Word VME Read and Write3

For the more detailed VME bus Block Transfer Operations, we referenced both an online source and the

VME64x Spec. From an online source4 we had the basics of the VME bus block cycle transfer available,

but our primary source for the operation of this bus was Section 2.3.7 of the VME64 spec (also available

online) .

3 http://www.vita.com/vme-faq/readwritecyc.html

4 http://www.interfacebus.com/Design_Connector_VME.html

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Figure 4: VME BLT Transfer5

For the bus arbitration, we worked off both an online source6 and the VME64 spec (see Chapter 3).

Near the end of the project we were working directly off of the VEM64 spec, and the design of the VME

Priority Interrupt Bus and the test that was based on the interrupt bus only used the VME64 spec.

MPC563 Bus

The primary source for the operation of the MPC563 was the MPC563 spec. available online7. We used

Section 10.2 "Memory Controller Architecture" for assigning our chip select based on the internal

address in the processor. For the burst operations see section 9.5.5 “Burst Mechanism” and in

particular Figure 9-13, and for the single quad-byte operations see Sections 9.5.2.1 and 9.5.2.2.

See the attached source files for details

5 http://www.interfacebus.com/Design_Connector_VME.html

6 http://www.interfacebus.com/Design_Connector_VME.html “VME Bus Access Timing Diagram”

7 http://www.freescale.com/files/microcontrollers/doc/ref_manual/MPC561RM.pdf

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Operational Performance The system’s operation was based on the performance of nine tests (zero-index numbering). Each of these tests exercised

specific aspects of the system, and two (test two and seven) exercised a large part of the system in single tests. For more

detailed information about the sources (datasheets, websites, and notes) that were used to define the tests, see the tests in the

code.

A test counter moves the system to the next test after a configurable amount of time has run for the current test. The first three

and the last two tests are driven by the MPC563 master bus emulator, and four in the middle are driven by the VME master

emulator. The following diagrams point out some important features in each of these tests.

In the first test (test zero), the MPC563 bus master performed a burst read from the SDRAM directly through the SDRAM

controller. In this test, the startup of the SDRAMC meant the master emulator had to be capable of bouncing back after

receiving an error. A separate state machine in the SDRAMC manages the interface to the MPC563 (only returning TEA_N) until

the SDRAM is initialized. This test took advantage of the most complex component in the system right away, the SDRAMC. See

Figure 5 for a more detailed breakdown of the first test in post-route simulation.

Figure 5: Test Zero Post-Route Simulation

In the second test, the MPC563 initiates a burst (quad word) write to the SDRAMC. After creating this test, there was some

reflection about whether it is valid operation for a bus – it assumes a quad-word byte (which it may know) but then only writes

the four pieces of data after the fourth has been received. If power were to go down, the processor may erroneously believe

that the first few words of the burst were written. This scenario assumes the processor does not count the first few words of an

incomplete burst as written. See Figure 6 for a more detailed breakdown of this test.

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Figure 6: Test One Post-Route Simulation

All the major components of the system are tested in the third test, which performs a read through both the MPC563 to VME

interface and the VME to SDRAMC interface. In this test the MPC and VME bus have to operate on top of each other, handling

the interface between the asynchronous and synchronous buses. See Figure 7 for more details on test two in post-route

simulation.

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Figure 7: Test Two Post-Route Simulation

Test three is the first test that is initiated by the VME bus master emulator. In this test the VME master performs a single word

(quad-byte) read from the SDRAM through the SDRAM controller and the VME to SDRAMC interface. See Figure 8 for more

details.

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Figure 8: Test Three Post-Route Simulation

In test four, we perform a single word write to the SDRAM through the VME to SDRAM interface. See Figure 9 for more details.

Figure 9: Test Four Post-Route Simulation

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In test five, the VME master performs a Block Length Transfer (BLT) from the SDRAM, through the SDRAM Controller and the

VME to SDRAM interface. Because of the nature of the VME BLT, we can perform an arbitrary number of reads before we finish

this transaction. In this case, we performed six reads. See Figure 10 for more details.

Address strobe low indicates a

burst read is continuing.

Second read from the SDRAM (only four words

were received after the first command)

First of the six data

words being read.

Figure 10: Test Five Post-Route Simulation

In test six, the VME master executes a Block Length Transfer to the SDRAM through the SDRAM Controller and the VME to

SDRAMC interface. See Figure 11 for more details.

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Figure 11: Test Six Post-Route Simulation

In test seven, initiated by the MPC563 bus master emulator, we exercise almost all the components in the BIU, similar to test

two. In this test we write a single word to the SDRAM through both the MPC to VME interface and the VME to MPC interface.

See Figure 12 for more details.

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Figure 12: Test Seven Post-Route Simulation

The final test exercises the VME priority interrupt bus. The MPC563 writes to a register in the MPC to VME interface to initiate

and interrupt cycle on the VME bus, with the MPC to VME interface acting as the interrupter and the VME bus master emulator

acting as the interrupt handler. See Figure 13 for more details.

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Figure 13: Test Eight Post-Route Simulation

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Summary Although we didn’t get to debug the board in detail on hardware, we did get through creating the

clocks, pin constraints, and wiring for the interface, but unfortunately eventually lost to the clock on the

wall. One important lesson we learned was about the importance of setting standards for writing VHDL

early in the project so there isn’t any need to try to convert state machines or counters at the end of the

project when there is an incredible amount of code to manage. Although post-route simulation was

working by the end, the files in the project use different styles for their state machines and other sub-

components, leading to a feeling of inconsistency as you moved from file to file.

Overall, the final project went well, and the team was satisfied with the results we were able to achieve.

Using Subversion for version control, we were able to collaborate well, while developing in different

areas. This project was in particular a good opportunity for our individual team members to talk and

pass off some of our experience to each other. Knowing each of the other teammate’s specialties is also

important to setting a good timeline, and after this brief project together (in the future, it might be

better to make teams earlier) we’d be able to plan the timeline of another project much better.

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Appendix A: Description of Important Source Files

ece6050_project_testbench.vhd Includes all the other files in the project. This is the file that is

simulated in post-route simulation. When wiring up the board,

we used this file as the guidance for how we were going to

connect the components.

mpc_563_external_bus_interface.vhd The MPC 563 master emulator. Drives five of the nine

functional tests, and keeps track of the current test count.

ece6050_project.vhd The BIU, center of the tests.

mt48lc32m8a2_controller.vhd Part of the BIU, the SDRAM controller. This component has an

external interface to the MPC563 and an internal interface to

the VME64x to SDRAM interface.

vme64x_sdram_intf.vhd Part of the BIU, the VME64x bus to SDRAM Controller

interface.

mpc563_vme64x_interface.vhd Part of the BIU, the MPC563 bus to VME64x bus interface

vme64x_components.vhd Conglomeration of VME components

vme64x_bus_controller.vhd Part of vme64x_components, this component controls the

VME bus by arbitrating who can write on it.

vme64x_master.vhd Part of vme64x_components, the VME bus master emulator,

that also acts as the VME bus interrupt handler.

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Appendix B: Behavioral Simulation

Figure 14: Test Zero Behavioral Simulation

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Figure 15: Test One Behavioral Simulation

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Figure 16: Test Two Behavioral Simulation

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Figure 17: Test Three Behavioral Simulation

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Figure 18: Test Four Behavioral Simulation

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Figure 19: Test Five Behavioral Simulation

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Figure 20: Test Six Behavioral Simulation

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Figure 21: Test Seven Behvioral Simulation

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Figure 22: Test Eight Behavioral Simulation