E3 Mapper MegaCore Function E3MAP - · PDF fileE3 Mapper MegaCore Function 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 ... example: c:\max2work\tutorial\chiptrip.gdf. Also,

$Page 1: E3 Mapper MegaCore Function E3MAP - · PDF fileE3 Mapper MegaCore Function 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 ... example: c:\max2work\tutorial\chiptrip.gdf. Also,$
A-UG-IPE3MAPPER-01

E3MAP

E3 Mapper MegaCore Function

101 Innovation DriveSan Jose, CA 95134(408) 544-7000http://www.altera.com

March 9, 2001 User GuideVersion 1.0

ii Altera Corporation

E3 Mapper MegaCore Function (E3MAP) User Guide

Altera, APEX, APEX 20K, APEX 20KE, MegaCore, MegaWizard, OpenCore, Quartus, and Quartus II are trademarks and/orservice marks of Altera Corporation in the United States and other countries. Altera Corporation acknowledges the trademarksof other organizations for their respective products or services mentioned in this document, including the following: Verilog is aregistered trademark of Cadence Design Systems, Incorporated. Java is a trademark of Sun Microsystems Inc. Microsoft is aregistered trademark and Windows is a trademark of Microsoft Corporation. Altera products are protected under numerous U.S.and foreign patents and pending applications, maskwork rights, and copyrights. Altera warrants performance of itssemiconductor products to current specifications in accordance with Altera’s standard warranty, but reserves the right to makechanges to any products and services at any time without notice. Altera assumes no responsibility or liabilityarising out of the application or use of any information, product, or service described herein except as expresslyagreed to in writing by Altera Corporation. Altera customers are advised to obtain the latest version of devicespecifications before relying on any published information and before placing orders for products or services.

Copyright 2001 Altera Corporation. All rights reserved.

Altera Corporation iii

About this User Guide

User Guide

This user guide provides comprehensive information about the Altera® E3 Mapper MegaCore® Function (E3MAP).

Table 1 shows the user guide revision history.

How to Find Information

■ The Adobe Acrobat Find feature allows you to search the contents of a PDF file. Click on the binoculars icon in the top tool bar to open the Find dialog box, or click the right mouse button for a pull-down menu.

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provide a link to the pages.■ Numerous links, shown in green text, allow you to jump to related

information.

Table 1. Revision History

Revision Date Description

1.0 March 9, 2001 Initial release of this document

iv Altera Corporation

About this User Guide E3 Mapper MegaCore Function (E3MAP) User Guide

How to Contact Altera

For the most up-to-date information about Altera products, go to the Altera world-wide web site at http://www.altera.com.

For additional information about Altera products, consult the sources shown in Table 2.

Note:(1) You can also contact your local Altera sales office or sales representative.

Table 2. How to Contact Altera

Information Type Access USA & Canada All Other Locations

Altera Literature Services

Electronic mail [email protected] (1) [email protected] (1)

Non-technical customer service

Telephone hotline (800) SOS-EPLD (408) 544-7000 (7:30 a.m. to 5:30 p.m. Pacific Time)

Fax (408) 544-7606 (408) 544-7606

Technical support Telephone hotline (800) 800-EPLD(6:00 a.m. to 6:00 p.m. Pacific Time)

(408) 544-7000 (1)(7:30 a.m. to 5:30 p.m. Pacific Time)

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Electronic mail [email protected] [email protected]

FTP site [email protected] [email protected]

General product information

Telephone (408) 544-7104 (408) 544-7104 (1)

World-wide web site http://www.altera.com http://www.altera.com

http://www.altera.com



mailto:[email protected]




mail to:[email protected]

mail to: [email protected]

Altera Corporation v

E3 Mapper MegaCore Function (E3MAP) User Guide About this User Guide

Typographic Conventions

The E3 Mapper MegaCore Function (E3MAP) User Guide uses the typographic conventions shown in Table 3.

Table 3. Conventions

Visual Cue Meaning

Bold Type with Initial Capital Letters

Command names, dialog box titles, checkbox options, and dialog box options are shown in bold, initial capital letters. Example: Save As dialog box.

Bold type External timing parameters, directory names, project names, disk drive names, filenames, filename extensions, and software utility names are shown in bold type. Examples: fMAX, \maxplus2 directory, d: drive, chiptrip.gdf file.

Bold italic type Book titles are shown in bold italic type with initial capital letters. Example: 1999 Device Data Book.

Italic Type with Initial Capital Letters

Document titles are shown in italic type with initial capital letters. Example: AN 75 (High-Speed Board Design).

Italic type Internal timing parameters and variables are shown in italic type. Examples: tPIA, n + 1.Variable names are enclosed in angle brackets (< >) and shown in italic type. Example: <file name>, <project name>.pof file.

Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters. Examples: Delete key, the Options menu.

“Subheading Title” References to sections within a document and titles of Quartus II and MAX+PLUS II Help topics are shown in quotation marks. Example: “Configuring a FLEX 10K or FLEX 8000 Device with the BitBlaster™ Download Cable.”

Courier type Signal and port names are shown in lowercase Courier type. Examples: data1, tdi, input. Active-low signals are denoted by suffix _n, e.g., reset_n.

Anything that must be typed exactly as it appears is shown in Courier type. For example: c:\max2work\tutorial\chiptrip.gdf. Also, sections of an actual file, such as a Report File, references to parts of files (e.g., the AHDL keyword SUBDESIGN), as well as logic function names (e.g., TRI) are shown in Courier.

1., 2., 3., and a., b., c.,... Numbered steps are used in a list of items when the sequence of the items is important, such as the steps listed in a procedure.

■ Bullets are used in a list of items when the sequence of the items is not important.

v The checkmark indicates a procedure that consists of one step only.

1 The hand points to information that requires special attention.

r The angled arrow indicates you should press the Enter key.

f The feet direct you to more information on a particular topic.

vi Altera Corporation

About this User Guide E3 Mapper MegaCore Function (E3MAP) User Guide

Abbreviations & Acronyms

AHDL Altera Hardware Description LanguageAIRbus Access to Internal Registers interfaceAU-3 Administrative Unit level 3ATM Asynchronous Transfer ModeCPU Central processing unitCDR Clock Data RecoveryEDA Electronic Design AutomationESB Embedded System BlockFIFO First In First OutIP Intellectual PropertyLE Logic ElementLSb Least Significant bitLSB Least Significant ByteMbps Megabits per secondMSb Most Significant bitMSB Most Significant ByteNDF New Data FlagOOF Out Of FramePC Personal computerPOH Path OverheadRX ReceiveSDH Synchronous Digital HierarchySONET Synchronous Optical NetworkSPE Synchronous Payload EnvelopeSTS-1 Synchronous Transport Signal level 1E3FRM E3 Framer MegaCore FunctionTOH Transport OverheadTX TransmitUTOPIA Universal Test & Operations Physical Interface for ATMVC-3 Virtual Container level 3VCO Voltage Controlled OscillatorVHDL VHSIC Hardware Description LanguageVHSIC Very High Speed Integrated Circuit

Altera Corporation vii

Contents

User Guide

SpecificationsGeneral Description .........................................................................................................................9

MegaWizard Generated Files .................................................................................................9Features ...........................................................................................................................................10

EXTRACT ................................................................................................................................10INSERT ....................................................................................................................................10

Functional Description ..................................................................................................................12EXTRACT ................................................................................................................................12

E3 Data Rate ....................................................................................................................12Data Byte Acceptance ....................................................................................................13Destuffing ........................................................................................................................13E3 Extraction ...................................................................................................................13

INSERT ....................................................................................................................................13Asynchronous Mapping ...............................................................................................13Stuffing ............................................................................................................................13

Interfaces & Protocols ....................................................................................................................14Midbus .....................................................................................................................................14

Receive Direction ...........................................................................................................14Transmit Direction .........................................................................................................15

AIRbus .....................................................................................................................................16E3 Mapper Interface ..............................................................................................................16

Receive .............................................................................................................................16Transmit ..........................................................................................................................16

Performance ....................................................................................................................................17I/O Signals ......................................................................................................................................17Software Interface ..........................................................................................................................19

Memory Map ..........................................................................................................................19Registers ..................................................................................................................................20

Insert Register Description ...........................................................................................20INS_CTRL - MAP_INSERT Control - ’h0 .................................................. 20INS_STAT - MAP_INSERT Status - ’h1 ..................................................... 20INS_IS - MAP_INSERT Interrupt Status - ’h2 ........................................... 21INS_IE - MAP_INSERT Interrupt Enable - ’h3 ......................................... 21INS_RESERVED1 - Reserved For Future Use - ’h4 .................................. 21

Extract Register Description .........................................................................................21EXT_CTRL - MAP_EXTRACT Control - ’h5 ............................................. 21EXT_STAT - MAP_EXTRACT Status - ’h6 ............................................... 21EXT_IS - MAP_EXTRACT Interrupt Status - ’h7 ...................................... 22EXT_IE - MAP_EXTRACT Interrupt Enable - ’h8 .................................... 22

viii Altera Corporation

Contents E3 Mapper MegaCore Function (E3MAP) User Guide

EXT_RESERVED2 - Reserved For Future Use - ’h9 ................................. 22EXT_FIFO_HIGH - MAP_EXTRACT FIFO High Mark - ’hA ................ 22EXT_FIFO_LOW - MAP_EXTRACT FIFO Low Mark - ’hB .................... 22

Getting StartedTest-Drive an E3MAP ....................................................................................................................23Design Walkthrough .....................................................................................................................23Obtaining & Installing the E3MAP .............................................................................................24

Installing the MegaCore Files ...............................................................................................24Generating a Custom E3MAP ......................................................................................................25Implementing the System .............................................................................................................25Compiling & Performing Place & Route ....................................................................................25

Performing Synthesis Compilation & Post-Routing Simulation .....................................25Using Third-Party EDA Tools ......................................................................................26Using the Quartus II Software .....................................................................................26Functional Simulations Using Visual IP Models .......................................................27Downloading & Installing Visual IP Software ..........................................................27

Licensing & Configuring a Device ..............................................................................................27

Altera Corporation 9

Specifications

User Guide

1

Specifications

General Description

The E3 Mapper MegaCore® Function (E3MAP) uses the MegaWizard® Plug-In—within the Quartus™ II software to generate variants in VHDL, AHDL, or Verilog HDL, which you can instantiate into your design.

Table 1 shows the optional features available for the E3MAP.

Note:(1) The numbers for LEs and ESBs are approximate as of March 9, 2001. Users are strongly advised to run the

MegaWizard Plug-In and Quartus II software to see exact numbers for the E3MAP.

MegaWizard Generated Files

When you finish going through the wizard, it generates the following files:

■ One of the following files—depending on your EDA tool selection— is used to instantiate an E3MAP into your design:– An AHDL text design file (.tdf);– A VHDL design file (.vhd);– A Verilog design file (.v);

■ Sample Verilog instantiation of Black Box (_inst.v);■ Black Box module (_bb.v);■ Symbol files (.bsf) for the Quartus II software are used to instantiate

the E3MAP into a schematic design;■ An encrypted HDL netlist file (.e.vqm.v).

Table 1. Optional Features Note (1)

Options Parameters Choices LEs ESBs

Basic Configuration – – 950 2

10 Altera Corporation

Specifications E3 Mapper MegaCore Function (E3MAP) User Guide

Features The E3MAP interfaces to a data bit stream at a data rate of 34.368 Mbps +/- 687 bps—via bit stuffing—to accommodate standard E3 rates. While it is expected that the E3 input stream will be within the standard limits of 34.368 Mbps +/- 687 bps, the E3MAP supports rates between 34.344 Mbps and 34.392 Mbps.

The E3MAP asynchronously maps clear channel synchronous and asynchronous E3 signal over SONET/SDH STS-1/AU-3.

The E3MAP supports STS-1, STS-3, and STS-12 data paths (via AU-3). It comprises two major blocks, EXTRACT and INSERT—illustrated in Figure 1.

EXTRACT

■ Supports the standard E3 rate via adaptive control of the external VCO—illustrated in Figure 2. The FIFO buffer is 32 bytes deep.

■ Accepts data bytes from a SONET/SDH framer■ Performs destuffing■ Extracts E3 stream, and forwards it optionally to an E3 framer

INSERT

■ Performs asynchronous mapping■ Performs payload bit stuffing■ Uses a 32-byte FIFO buffer■ Provides payload bytes to a SONET/SDH framer ■ Accepts an E3 bit stream that is either raw or from an E3 framer

The E3MAP complies with all applicable standards, including:

– International Telecommunication Union, Network node interface for the synchronous digital hierarchy (SDH), ITU-T G. 707, March 1996

1 The E3MAP does not support the following features: – E3 to AU-4 mapping via TU-3 and TUG-3;– SONET/SDH line and path overhead processing; – E3 framing, including overhead processing;– Translation of maintenance signals between E3 and AU-3

(translation should be performed by software between the E3 framer and the AU-3 overhead blocks);

– Automatic resynchronization after AU-3 new pointer or NDF events (The E3MAP requires a soft restart.)


E3 Mapper MegaCore Function (E3MAP) User Guide Specifications

1

Specifications

Figure 1. Block Diagram

sel

read

addr

[3:0

]

wda

ta[7

:0]

rdat

a[7:

0]irq

AIRbus

vco_

incr

ease

vco_

decr

ease

mtxdat[7:0]

mtxena

mrxdat[7:0]

mrxena

e3_rxdata

e3_rxclk

e3_txdataEXTRACT

e3_txclk

Midbus

txclktxreset_n

rxclkrxreset_n

dtac

k

E3 Mapper Interface

E3 Mapper Interface Midbus

mrxfohmrxeoh

mtxfoh

mtxeoh

mrxval

mtxval

txclk_en

rxclk_en

mrxefp

mtxefp

E3MAP (E3 Mapper)

INSERT



Figure 2. Core Clocking

Note:(1) For a more detailed view of the Midbus see Figure 1.

Functional Description

EXTRACT

E3 Data Rate

The E3MAP provides support of the standard E3 rates by maintaining adaptive control of an external VCO. In this case, a Phase Lock Loop (PLL) is formed using the FIFO fill status as the phase comparator. The FIFO stores extracted E3 data from the VC-3. The low-pass filter and VCO are external to the core. Software programmable thresholds—EXT_FIFO_HIGH and EXT_FIFO_LOW—assert either vco_increase or vco_decrease, when violated. This indicates a change is required in the E3 clock rate, e3_txclk. See “Core Clocking” on page 12.

■ vco_increase indicates the 32-byte FIFO buffer is filling and the clock should increase.

■ vco_decrease indicates the 32-byte FIFO buffer is emptying and the clock should decrease.

VCO

e3_txclk

E3MAP

INSERT

EXTRACT e3_txdata

e3_rxclk

e3_rxdata

vco_

decr

ease

vco_

incr

ease

Low-PassFilter

STS1FRM (SONET STS-1

Framer)

RX

TX

rxclk

txclk

mrxdat(2)

mtxdat (2)

(E3 Mapper )



1

Specifications

Data Byte Acceptance

The E3MAP accepts data bytes from a SONET/ SDH framer via a Midbus interface. See “Midbus” on page 14 for more details.

Destuffing

The destuffing mechanism compensates for the frequency differences between the SONET/SDH and E3 data paths.

E3 Extraction

The E3MAP extracts an E3 bit stream from the input SONET STS-1/ SDH AU-3, and outputs the raw E3 bit stream. (E3MAP forwards the E3 bit stream optionally to an E3FRM.) The EXTRACT block synchronizes with the Midbus when the EXTRACT software enable (CTRL_ENABLE) register is asserted.

INSERT

Asynchronous Mapping

In order to generate an output conforming to E3-VC-3 mapping, the INSERT block takes data from an internal 32 byte deep FIFO containing E3 data collected from the E3 Mapper interface. The INSERT block synchronizes with the Midbus when the INSERT software enable (CTRL_ENABLE) register is asserted.

Stuffing

The E3MAP bit stuffing mechanism compensates for the frequency differences between E3 and SONET/SDH data. The E3MAP also handles SONET/SDH positive and negative stuffing. This stuffing action is performed in the SONET/SDH network to compensate for frequency differences within the SONET/SDH network.

SONET/SDH positive/negative stuffing, and E3MAP stuffing mechanisms are independent of each other.

1 A SONET/SDH NDF or new pointer event requires a soft restart of the E3MAP. To do a soft restart you need to toggle the INSERT block control enable register , “INS_CTRL - MAP_INSERT Control - 'h0” on page 20, and the EXTRACT clock control enable register, “EXT_CTRL - MAP_EXTRACT Control - 'h5” on page 21. This state (NDF) is not detected by the E3MAP. An NDF event reflects a major movement in the position of the mapped data in the SONET/SDH stream and requires that the E3MAP resynchronize itself to the payload.



Interfaces & Protocols

Three interfaces support the E3MAP: the Middle interface (Midbus), the Access to Internal Registers (AIRbus) interface, and the E3 Mapper interface. These interfaces are illustrated in Figure 1.

Midbus

The Midbus interface is a simple synchronous full-duplex data path bus. The E3MAP Midbus transports data over a single-byte lane in each direction. The required frequency of the Midbus varies depending on the SONET/SDH framer supported—see Table 2.

Note:(1) In the case of higher bandwidth interfaces, the signals, txclk_en and rxclk_en,

are used to match the data rate with the clock rate. This column shows the expected nominal duty cycle of the enable signal.

In the receive direction (RX), data is transferred from the Midbus master to the slave (E3MAP). In the transmit direction (TX), data is transferred from the slave (E3MAP) to the Midbus master. In each direction, the Midbus can carry eight bits per clock cycle. Midbus receive data (mrxdat[7:0]) and midbus receive enable (mrxena) lines indicate a valid data transfer in the RX direction. Midbus transmit data (mtxdat[7:0]) and midbus transmit enable (mtxena) lines indicate a valid data request in the TX direction.

Receive Direction

Figure 3 shows the Midbus signals in the receive direction. The E3MAP reads data on mrxdat, on the rising edge of rxclk. The following position indicators are also presented with the data.

■ mrxval indicates that the following strobes are valid, see Figure 3.– mrxena indicates mrxdat is user payload (PL).– mrxfoh indicates mrxdat is a fixed frame overhead (A1, A2, J0,

Z0, B1, E1, F1) this includes all section and line overhead, and undefined/growth.

– mrxeoh indicates mrxdat is an embedded frame overhead (J1, B3) this includes all path overhead.

– mrxefp indicates an embedded frame pulse.

Table 2. Midbus Clocks

Configuration Clock Rate (MHz) Clock Nominal Enable Rate (1)txclk_en or rxclk_en

STS-1 6.48 Held active every clock

STS-1x3 19.44 Active: 1 in 3 clocks

STS-1x12 77.76 Active: 1 in 12 clocks



1

Specifications

Transmit Direction

Figure 4 shows the Midbus signals in the transmit direction, which provide position commands (listed below) that indicate the type of byte being processed on the next clock pulse.

■ mtxval indicates that the following strobes are valid, see Figure 4.– mtxena indicates user payload.– mtxfoh indicates a fixed frame overhead (A1, A2, J0, Z0, B1, E1,

F1) this includes all section and line overhead, and undefined/growth.

– mtxeoh indicates an embedded frame overhead (J1, B3) this includes all path overhead.

– mtxefp indicates an embedded frame pulse.

The E3MAP puts valid data on mtxdat on the rising edge of txclk, following an asserted high mtxval.

Figures 3 and 4 illustrate the Midbus timing for the E3MAP interfacing to an STS-1 framer.

Figure 3. E3MAP Receive Midbus Timing Diagram

Figure 4. E3MAP Transmit Midbus Timing Diagram

mrxdat

mrxena

mrxeoh

rxclk

A1 A1 A1 A2

mrxval

mrxfoh

A2 PL

mrxefp

A2 J0 Z0 Z0 PL J1 PL B1 U U E1 U PL U F1 U U B3 PL PL

mtxdat

mtxena

mtxeoh

txclk

A1 A1 A1 A2

mtxval

mtxfoh

A2 PL

mtxefp

A2 J0 Z0 Z0 PL J1 PL B1 U U E1 U PL U F1 U U

…

B3 PL PL



AIRbus

The AIRbus interface provides access to internal registers using a simple synchronous internal processor bus protocol. This consists of separate read (rdata) and write (wdata) data buses, a data transfer acknowledge (dtack) signal, and a select (sel) signal. An address bus (addr[3:0]) and read (read) signal indicate the location and type of access within the block. The rdata buses and dtack signals can be merged from multiple blocks using a simple OR function. The dtack signal is sustained until the block sel is removed (four-way handshaking) meaning the AIRbus can cross clock domain boundaries. The E3MAP is an AIRbus slave with a data width of eight bits.

f For more detailed information on the Midbus and AIRbus refer to the Altera web site at http://www.altera.com/IPmegastore.

E3 Mapper Interface

The E3 Mapper interface is used to convey full E3 data.The E3MAP also provides users with the option of receiving and transmitting E3 framed data from/to an E3 framer. The E3 bit stream, including overhead bits, is then mapped into a SONET/SDH VC-3 asynchronously.

Receive

A new E3 bit is expected to be present on the e3_rxdata signal at the rising edge of e3_rxclk.

Figure 5. Receive E3 Mapper Timing Diagram

Transmit

A new E3 bit is expected to be present on the e3_txdata signal at the rising edge of e3_txclk.

Figure 6. Transmit E3 Mapper Timing Diagram

In+1

e3_rxclk

e3_rxdat In

e3txclk

e3_txdat In In+1

http://www.altera.com/ipmegastore

http://www.altera.com/IPmegastore



1

Specifications

Performance Table 3 shows the required speed and estimated gate count of the E3MAP in an APEX 20KE device.

Notes:(1) All LE and ESB numbers are approximate as of March 9, 2001.(2) If the E3MAP interfaces to an STS-12 line rate the fMAX will be 77.76 MHz.

I/O Signals Table 4 lists the I/O signals for the E3MAP.

Table 3. Performance Note (1)

LEs ESBs fMAX (MHz) (2)

950 2 34.392 required

Table 4. Port List

Port Direction Description

RX Signals

rxclk Input Receive data clock

rxreset_n Input Receive active low reset

rxclk_en Input Receive clock enable

TX Signals

txclk Input Transmit data clock

txreset_n Input Transmit active low reset

txclk_en Input Transmit clock enable

Midbus RX Signals

mrxdat[7:0] Input Midbus receive data

mrxena Input Midbus receive enable

mrxfoh Input Midbus receive fixed overhead

mrxeoh Input Midbus receive embedded overhead

mrxval Input Midbus receive valid data

mrxefp Input Midbus receive embedded frame pulse

Midbus TX Signals

mtxdat[7:0] Output Midbus transmit data

mtxena Input Midbus transmit enable

mtxfoh Input Midbus transmit fixed overhead

mtxeoh Input Midbus transmit embedded overhead

mtxval Input Midbus transmit valid data

mtxefp Input Midbus transmit embedded frame pulse



AIRbus Signals

sel Input Select signal. When this signal goes high, it selects internal registers.

read Input Read/write control signal:High: Reads data from data busLow: Writes data to data bus

irq Output Interrupt request signal. When the signal is ‘1’, this indicates an interrupt request.

dtack Output Data transfer acknowledge signal that comes from the internal registers to indicate the internal registers are ready to send or accept data.

rdata[7:0] Output Read data signals from internal register.

addr[3:0] Input Register address

wdata[7:0] Input Write data signals to internal register.

E3 Mapper Interface Signals

e3_rxclk Input E3 Mapper Interface receive clock at 34.368

e3_rxdata Input E3 Mapper Interface receive data—serial bit stream

e3_txclk Input E3 Mapper Interface transmit clock at 34.368 MHz. This clock is controlled by the E3 Mapper via external VCO.

e3_txdata Output E3 Mapper Interface transmit data—serial bit stream.

vco_decrease Output This pin indicates the extract block FIFO buffer is emptying and the E3 clock rate should be decreased.

vco_increase Output This pin indicates the extract block FIFO buffer is filling and the E3 clock rate should be increased.

Table 4. Port List

Port Direction Description



1

Specifications

Software Interface

Memory Map

All addresses are 8-bit accesses and are shown as hex values. Note that the access addresses for each register increment by units of 1, since the accesses are 8 bits wide.

Address Register Description

’h0 INS_CTRL MAP_INSERT Control ’h1 INS_STAT MAP_INSERT Status ’h2 INS_IS MAP_INSERT Interrupt Status ’h3 INS_IE MAP_INSERT Interrupt Enable ’h4 INS_RESERVED1 Reserved For Future Use

’h5 EXT_CTRL MAP_EXTRACT Control ’h6 EXT_STAT MAP_EXTRACT Status ’h7 EXT_IS MAP_EXTRACT Interrupt Status ’h8 EXT_IE MAP_EXTRACT Interrupt Enable ’h9 EXT_RESERVED2 Reserved For Future Use ’hA EXT_FIFO_HIGH MAP_EXTRACT FIFO High Mark ’hB EXT_FIFO_LOW MAP_EXTRACT FIFO Low Mark



Registers

The following table lists the access codes used to describe the type of register bits.

Insert Register Description

Code Description

RW Read/Write RO Read-Only RW1C Read/Write 1 to Clear RW0S Read/Write 0 to Set RTC Read to Clear RTS Read to Set RTCW Read to Clear/Write RTSW Read to Set/Write RWTC Read/Write any value to Clear RWTS Read/Write any value to Set RWSC Read/Write Self-Clearing RWSS Read/Write Self-Setting UR0 Unused bits/Read as 0 UR1 Unused bits/Read as 1

INS_CTRL - MAP_INSERT Control - ’h0

Field Bits Access Function Default

ENABLE 0 RW When ’0’, MAP_INSERT produces static undefined output (’b1111 1111). Initially, after rising edge, MAP_INSERT will synchronize to mtxeoh, then produce valid output.

0

INS_STAT - MAP_INSERT Status - ’h1


MAP_SYNC 0 RO When asserted, the E3MAP has been synchronized to the mtxeoh pulse.

0



1

Specifications

Extract Register Description

INS_IS - MAP_INSERT Interrupt Status - ’h2


FIFO_CORRUPT 1 RTC A ’1’ indicates the MAP_INSERT internal FIFO buffer has either underflowed or overflowed.

0

STS_CORRUPT 0 RTC A ’1’ indicates MAP_INSERT has received an mtxena pattern that it could not handle (90 ticks between poh strobes with 84 enable intermediate). A software resynchronization is required.

0

INS_IE - MAP_INSERT Interrupt Enable - ’h3


FIFO_CORRUPT 1 RW This is the MAP_INSERT FIFO_CORRUPT interrupt enable.

0

STS_CORRUPT 0 RW This is the MAP_INSERT STS_CORRUPT interrupt enable. 0

INS_RESERVED1 - Reserved For Future Use - ’h4


RES1 7:0 UR0 This register is reserved for future use. 0

EXT_CTRL - MAP_EXTRACT Control - ’h5


ENABLE 0 RW When ’0’, MAP_EXTRACT produces static undefined output (’b0). Initially, after rising edge, MAP_EXTRACT will synchronize to mrxeoh, then produce valid output.

0

EXT_STAT - MAP_EXTRACT Status - ’h6


MAP_SYNC 0 RO When asserted, the E3MAP has been synchronized to the mrxeoh pulse.

0



EXT_IS - MAP_EXTRACT Interrupt Status - ’h7


FIFO_CORRUPT 1 RTC A ’1’ indicates the the MAP_EXTRACT internal FIFO buffer has either underflowed or overflowed.

0

STS_CORRUPT 0 RTC A ’1’ indicates MAP_EXTRACT has received a mrxeoh/mrxena pattern that it could not handle. A software resynchronization is required.

0

EXT_IE - MAP_EXTRACT Interrupt Enable - ’h8


FIFO_CORRUPT 1 RW This is the MAP_EXTRACT FIFO_CORRUPT interrupt enable.

0

STS_CORRUPT 0 RW This is the MAP_EXTRACT STS_CORRUPT interrupt enable.

0

EXT_RESERVED2 - Reserved For Future Use - ’h9


RES2 7:0 UR0 This register is reserved for future use. 0

EXT_FIFO_HIGH - MAP_EXTRACT FIFO High Mark - ’hA


MARK 4:0 RW This is a threshold value for the number of bytes in the FIFO buffer. When the number of bytes in the FIFO buffer exceeds this value, the FIFO buffer is getting full. The vco_increase signal is then toggled and the e3_txclk is increased.

0

EXT_FIFO_LOW - MAP_EXTRACT FIFO Low Mark - ’hB


MARK 4:0 RW This is the threshold value for the number of bytes in the FIFO buffer. When the number of bytes in the FIFO buffer falls below this value, the FIFO buffer is getting empty. The vco_decrease signal is then toggled and the e3_txclk is decreased.

0


Getting Started

User Guide

2

Getting Started

Test-Drive an E3MAP

This section describes how to obtain a variant from the E3 Mapper MegaCore® Function (E3MAP). It explains how to install the E3MAP on your PC, and walks you through the process of implementing the variant in a design.

You can test-drive an E3MAP using the Altera® OpenCore™ feature—within the Quartus™ II software—to instantiate it, to perform place-and-route, to perform static timing analysis, and to simulate it using a third party simulator, within your custom logic.

Only when you are ready to generate programming files, do you need to obtain licenses through your local Altera sales representative.

Design Walkthrough

This design walkthrough involves the following steps:

1. Obtaining and installing the E3MAP.

2. Generating a custom E3MAP for your system using the MegaWizard® Plug-In.

3. Implementing the rest of your system using the AHDL, VHDL, or Verilog HDL.

4. Compiling your design and performing place-and-route.

5. Licensing the E3MAP to configure the device.

The instructions assume that:

■ You are using a PC■ You are familiar with Quartus II software■ The most current available version of Quartus II software is installed

in the default location■ You are using the OpenCore feature to test-drive a E3MAP, or you

have licensed it.


Getting Started E3 Mapper MegaCore Function (E3MAP) User Guide

Obtaining & Installing the E3MAP

In order to start using the E3MAP, you need to obtain the MegaCore package from your local Altera representative. The package includes:

■ MegaWizard Plug-In– Encrypted gate level netlist– Place-and-route constraints (where necessary)– Secure RTL simulation model

■ Sanity testbench■ Midbus and AIRbus Interface Functional Specifications■ Data Sheet■ User Guide

Installing the MegaCore Files

Use the MegaWizard Plug-In to generate the files and install them on your PC. The following instructions describe this process.

1 Before you can use the MegaWizard Plug-In, your PC must have Java runtime environment version 1.2.2 installed. This file can be downloaded from the Java web site http://www.java.sun.com.

For Windows, follow the instructions below:

1. Click Run (Start Menu).

2. Type <path name>\<filename>.exe, where <pathname> is the location of the downloaded E3MAP, and <filename> is the filename of the E3MAP. Click OK.

3. The MegaCore Installer dialog box appears. Follow the wizard instructions to finish the installation.

4. After you have finished installing the files, you must specify the directory in which you installed them as a user library in the Quartus II software. Search for “User Libraries” in Quartus II Help for instructions on how to add these libraries.

http://www.java.sun.com






E3 Mapper MegaCore Function (E3MAP) User Guide GettingGetting Started

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Getting Started

Generating a Custom E3MAP

This section describes the design flow using the Altera E3MAP and the Quartus II development system. The MegaWizard Plug-In Manager—used within the Quartus II software— allows you to create or modify design files to meet the needs of your application. You can use them to instantiate the E3MAP in your design file.

To create a custom E3MAP using the wizard, follow these steps:

1. Start the MegaWizard Plug-In by choosing the MegaWizard Plug-In Manager command (File menu) in the Quartus II software. The MegaWizard Plug-In Manager dialog box is displayed.

1 Refer to Quartus II Help for detailed instructions on how to use the MegaWizard Plug-In Manager.

2. Specify that you want to create a new custom variant and click Next.

3. On the second page of the wizard, select E3MAP from the E3 folder.

4. Choose the type of output files, specify the folder and name for the files the wizard creates, and click Next.

5. Select the optional parameters and choices that you require.

6. The final screen lists the design files that the wizard creates. Click Finish.

Implementing the System

Once you have created your custom E3MAP, you are ready to implement it. You can use the files generated by the MegaWizard in your design. You can use the Quartus II software, or other EDA tools to create your design.

Compiling & Performing Place & Route

You can use the Quartus II software to compile and place-and-route your design. Refer to Quartus II Help for instructions on performing compilation. After you have verified that your design is functionally correct, you are ready to perform system verification.

Performing Synthesis Compilation & Post-Routing Simulation

The Quartus II software works seamlessly with tools from all EDA vendors, including: Cadence, Exemplar Logic, Mentor Graphics, Synopsys, Synplicity, and Viewlogic. After you have licensed the E3MAP, you can generate EDIF, VHDL, Verilog HDL, and Standard Delay Output Files from the Quartus II software and use them with your existing EDA tools to perform functional modeling and post-route simulation of your design.


Getting Started E3 Mapper MegaCore Function (E3MAP) User Guide

Using Third-Party EDA Tools

To synthesize your design in a third-party EDA tool and perform post-route simulation, follow these steps:

1. Create your custom design instantiating a E3MAP.

2. Synthesize the design using your third-party EDA tool. Your EDA tool should treat the E3MAP as a black box by either setting attributes or ignoring the instantiation.

3. After compilation, generate a hierarchical netlist file in your third-party EDA tool.

4. Open your netlist file in the Quartus II software.

5. Add the pre-synthesized and encrypted .e.vqm.v file from your working directory.

Using the Quartus II Software

1. Select the Compile mode (Processing menu).

2. Specify the Compiler settings in the Compiler Settings dialog box (Processing menu), or use the Compiler Settings wizard.

3. Specify the user libraries for the project and the order in which the Compiler searches the libraries.

4. Specify the input settings for the project. Choose EDA Tool Settings (Project menu). Select Custom EDIF in the Design Entry/Synthesis Tool list. Click Settings. In the EDA Tool Input Settings dialog box, make sure that the relevant tool name or option is selected in the Design Entry/Synthesis Tool list.

5. Depending on the type of output file you want, specify Verilog HDL output settings or VHDL output settings in the General Settings dialog box (Project menu). Use the 1993 VHDL Language option.

6. Add the pre-synthesized and encrypted .e.vqm.v file from your working directory.

7. Compile your design. The Quartus II Compiler synthesizes and performs place-and-route on your design, and generates output and programming files.

8. Import your Quartus II-generated output files (.edo, .vho, .vo, or .sdo) into your third-party EDA tool for post-route, device-level, and system-level simulation.


E3 Mapper MegaCore Function (E3MAP) User Guide GettingGetting Started

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Getting Started

Functional Simulations Using Visual IP Models

This section describes Visual IP Model verification and provides instructions for using Visual IP Models. Figure 1 shows an example Visual IP Model arrangement.

Figure 1. General Arrangement

1 The top level of the Visual IP Model can be treated as a sub-block of a design or as the main design unit.

Downloading & Installing Visual IP Software

The Visual IP software facilitates the use of Visual IP simulation models by allowing waveforms to be viewed using third-party simulation tools. To view the simulation model, you must have Visual IP software installed on your system. To download the software, or for instructions on how to use it, refer to the Altera web site, http://www.altera.com/IPmegastore.

Licensing & Configuring a Device

After you have compiled and analyzed your design, you are ready to configure your targeted Altera semiconductor device. If you are evaluating the E3MAP with the OpenCore feature, you must license the function before you can generate programming files. To obtain a licence contact your local Altera sales representative.

1 All current E3MAP variants use a single license with ordering code: PLSM-E3MAP.

Testbench

Hook-Up

Utility 2 Utility 3Utility 1

User Design

Visual IP Model

Black BoxVerilog or VHDL WrapperEmpty I/O Declaration

http://www.altera.com/IPmegastore

Notes:

Documents

E3 Mapper MegaCore Function E3MAP - · PDF fileE3 Mapper MegaCore Function 101 Innovation Drive San Jose, CA 95134 (408) 544-7000 ... example: c:\max2work\tutorial\chiptrip.gdf. Also,