e200Z759N3CRM: e200Z759N3 Core Reference Manual Microarchitecture summary ... 8.3.9 Performance Monitor Counter registers ... e200z759n3 Core Reference Manual, Rev. 2 1 1

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  • e200z759n3 Core Reference Manual, Rev. 2

    Freescale Semiconductor 1

    e200z759n3 Core Reference ManualSupports:

    e200z759n3

    e200z759n3CRMRev. 2

    January 2015

  • e200z759n3 Core Reference Manual, Rev. 2

    Freescale Semiconductor 3

    Chapter 1e200z759n3 Overview

    1.1 Overview of the e200z759n3 ..........................................................................................................231.1.1 Features .............................................................................................................................231.1.2 Microarchitecture summary ..............................................................................................24

    1.1.2.1 Instruction unit features ..................................................................................261.1.2.2 Integer unit features ........................................................................................271.1.2.3 Load/store unit features ..................................................................................271.1.2.4 Cache features .................................................................................................271.1.2.5 MMU Features ................................................................................................281.1.2.6 e200z759n3 system bus features .....................................................................28

    Chapter 2Register Model

    2.1 PowerPC Book E registers ..............................................................................................................332.2 Zen-specific special purpose registers .............................................................................................352.3 Zen-specific device control registers ...............................................................................................372.4 Special-purpose register descriptions ..............................................................................................37

    2.4.1 Machine State Register (MSR) .........................................................................................372.4.2 Processor ID Register (PIR) .............................................................................................392.4.3 Processor Version Register (PVR) ....................................................................................402.4.4 System Version Register (SVR) ........................................................................................412.4.5 Integer Exception Register (XER) ....................................................................................412.4.6 Exception Syndrome Register ..........................................................................................42

    2.4.6.1 PowerPC VLE mode instruction syndrome ....................................................442.4.6.2 Misaligned instruction fetch syndrome ...........................................................44

    2.4.7 Machine Check Syndrome Register (MCSR) ...................................................................452.4.8 Timer Control Register (TCR) ..........................................................................................472.4.9 Timer Status Register (TSR) .............................................................................................482.4.10 Debug registers .................................................................................................................492.4.11 Hardware Implementation Dependent Register 0 (HID0) ................................................502.4.12 Hardware Implementation Dependent Register 1 (HID1) ................................................522.4.13 Branch Unit Control and Status Register (BUCSR) .........................................................532.4.14 L1 Cache Control and Status Registers (L1CSR0, L1CSR1) ...........................................542.4.15 L1 Cache Configuration registers (L1CFG0, L1CFG1) ...................................................542.4.16 L1 Cache Flush and Invalidate registers (L1FINV0, L1FINV1) ......................................552.4.17 MMU Control and Status Register (MMUCSR0) ............................................................552.4.18 MMU Configuration register (MMUCFG) .......................................................................552.4.19 TLB Configuration registers (TLB0CFG, TLB1CFG) .....................................................55

    2.5 SPR register access ..........................................................................................................................552.5.1 Invalid SPR references ......................................................................................................552.5.2 Synchronization requirements for SPRs ...........................................................................562.5.3 Special purpose register summary ....................................................................................57

    2.6 Reset settings ...................................................................................................................................60

  • e200z759n3 Core Reference Manual, Rev. 2

    4 Freescale Semiconductor

    Chapter 3Instruction Model

    3.1 Unsupported instructions and instruction forms .............................................................................653.2 Implementation-specific instructions ..............................................................................................653.3 Book E instruction extensions .........................................................................................................663.4 Memory access alignment support ..................................................................................................663.5 Memory synchronization and reservation instructions ...................................................................663.6 Branch prediction ............................................................................................................................683.7 Interruption of instructions by interrupt requests ............................................................................683.8 New Zen instructions and APUs .....................................................................................................683.9 ISEL APU .......................................................................................................................................693.10 Debug APU .....................................................................................................................................69

    3.10.1 Debug notify halt instructions ...........................................................................................713.11 Machine Check APU .......................................................................................................................733.12 WAIT APU ......................................................................................................................................753.13 Enhanced reservations APU ............................................................................................................763.14 Volatile Context Save/Restore APU ................................................................................................793.15 Unimplemented SPRs and read-only SPRs .....................................................................................873.16 Invalid forms of instructions ...........................................................................................................87

    3.16.1 Load and store with update instructions ...........................................................................873.16.2 Load multiple word (lmw, e_lmw) instruction .................................................................873.16.3 Branch conditional to count register instructions .............................................................873.16.4 Instructions with reserved fields non-zero ........................................................................88

    3.17 Instruction summary ........................................................................................................................883.17.1 Instruction index sorted by mnemonic ..............................................................................893.17.2 Instruction index sorted by opcode .................................................................................102

    Chapter 4Instruction Pipeline and Execution Timing

    4.1 Overview of operation ...................................................................................................................1174.1.1 Control unit .....................................................................................................................1194.1.2 Instruction unit ................................................................................................................1194.1.3 Branch unit ......................................................................................................................1194.1.4 Instruction decode unit ....................................................................................................1194.1.5 Exception handling .........................................................................................................120

    4.2 Execution units ..............................................................................................................................1204.2.1 Integer execution units ....................................................................................................1204.2.2 Load / store unit ..............................................................................................................1204.2.3 Embedded floating-point execution units ........................