e200z4 Power Architecture â„¢ Core - Reference .e200z4 Power Architectureâ„¢ Core Reference Manual,

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e200z4 Power ArchitectureCore Reference Manual

Supportse200z446n3

e200z4RMRev. 0

10/2009

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e200z4 Power Architecture Core Reference Manual, Rev. 0

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ContentsParagraphNumber Title

PageNumber

Contents

Chapter 1 e200z4 Core Complex Overview

1.1 Overview.......................................................................................................................... 1-11.2 Features ............................................................................................................................ 1-31.2.1 Execution Unit Features............................................................................................... 1-31.2.1.1 Instruction Unit Features ......................................................................................... 1-41.2.1.2 Integer Unit Features ............................................................................................... 1-41.2.1.3 Load/Store Unit Features ......................................................................................... 1-41.2.2 L1 Cache Features ....................................................................................................... 1-41.2.3 Memory Management Unit Features ........................................................................... 1-51.2.4 System Bus (Core Complex Interface) Features.......................................................... 1-51.2.5 Nexus 3+ Features ....................................................................................................... 1-61.3 Programming Model ........................................................................................................ 1-61.3.1 Register Set .................................................................................................................. 1-71.3.2 Instruction Set .............................................................................................................. 1-91.3.3 Interrupts and Exception Handling ............................................................................ 1-101.4 Microarchitecture Summary .......................................................................................... 1-12

Chapter 2 Register Model

2.1 Power ISA Embedded Category Registers ...................................................................... 2-32.1.1 User-level Registers ..................................................................................................... 2-32.1.2 Supervisor-level Registers ........................................................................................... 2-42.2 e200-Specific Special Purpose Registers......................................................................... 2-62.2.1 User-Level Registers.................................................................................................... 2-72.2.2 Supervisor-Level Registers.......................................................................................... 2-72.3 e200-Specific Device Control Registers.......................................................................... 2-92.4 Special Purpose Register Descriptions ............................................................................ 2-92.4.1 Machine State Register (MSR) .................................................................................... 2-92.4.2 Processor ID Register (PIR) ...................................................................................... 2-112.4.3 Processor Version Register (PVR)............................................................................. 2-122.4.4 System Version Register (SVR)................................................................................. 2-122.4.5 Integer Exception Register (XER)............................................................................. 2-132.4.6 Exception Syndrome Register ................................................................................... 2-142.4.6.1 Power ISA VLE Mode Instruction Syndrome....................................................... 2-162.4.6.2 Misaligned Instruction Fetch Syndrome................................................................ 2-162.4.7 Machine Check Syndrome Register (MCSR)............................................................ 2-172.4.8 Timer Control Register (TCR)................................................................................... 2-19

e200z4 Power Architecture Core Reference Manual, Rev. 0

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PageNumber

2.4.9 Timer Status Register (TSR)...................................................................................... 2-212.4.10 Debug Registers......................................................................................................... 2-222.4.11 Hardware Implementation Dependent Register 0 (HID0) ......................................... 2-222.4.12 Hardware Implementation Dependent Register 1 (HID1) ......................................... 2-242.4.13 Branch Unit Control and Status Register (BUCSR).................................................. 2-252.4.14 L1 Cache Control and Status Registers (L1CSR0, L1CSR1).................................... 2-262.4.15 L1 Cache Configuration Registers (L1CFG0, L1CFG1)........................................... 2-272.4.16 L1 Cache Flush and Invalidate Register (L1FINV1)................................................. 2-272.4.17 MMU Control and Status Register (MMUCSR0) ..................................................... 2-272.4.18 MMU Configuration Register (MMUCF