DS630 3GPP Downlink Chip Rate v1tem. This includes Channel-to-Stream Mapping and Spread and Scramble Code initialization and gen-eration. It also has the main data processing elements

Chip

IntroductionThe 3GPP Downlink Chip Rate core provides aRelease 6 Compliant, Xilinx FPGA optimized solutionfor Femto-cell, Pico-cell and Macro-cell solutions.

Features• Available for Virtex-4, Virtex-5, Spartan-3A DSP

FPGAs

• Supports all FDD channels

- Slot formatting

- Scrambling, Spreading and Weighting

- System timing (TCELL, TDPCH, etc.)

- Multiple Sectors

- Pilot generation

- Pilot, TFCI, TPC symbol insertion

- STTD Encoding

- Fully Flexible architecture

• Fully optimized for speed and area

• Fully synchronous design with independent interface clocks

• For use with the Xilinx CORE Generator™ software v 9.2i and higher

Functional DescriptionThe 3GPP Downlink Chip Rate core provides a com-plete solution for Femto-cell, Pico-cell, and Macro-cellarchitectures. The architecture has been designed toprovide efficient use of the FPGA while also offering alow bandwidth interface to an external DSP or proces-sor to reduce system-level overhead. Timing criticaloperations are performed by the FPGA which also sim-plifies the software solution. See Figure 1.

This core provides the Physical Layer 1 slot formattingand chip rate processing functions. This includes thegeneration of the Pilots and STTD encoding which canoften be a processor intensive function. The core alsoprovides programmable System Timing where Sub-Slotbased interrupts can be configured by an external DSPallowing logical Channel grouping to be made basedon Channel Offset values.

All parameters and data are doubled buffered wherenecessary and internally synchronized to Slot or Frameboundaries as required by the System.

The interface to the core is OCP compatible and can beeasily attached to any bus-based system. This allowsmultiple cores to be inferred, or alternatively multipleprocessors can be supported. The memory mappedinterface allows for simple integration and validationwithin the system.

0

3GPP Downlink Chip Ratev1.0

DS630 August 8, 2007 0 0 Product Specification

Figure Top x-ref 1

Figure 1: Downlink Chip Rate Core

DSPI/F

SystemBased

Processing

ChannelBased

Processing

SectorBased

Processing

StreamBased

Processing

AntennaI/F

DSP_SRESP

DSP_SINTERRUPT

DSP_SDATA

DSP_CLK

RESET

DSP_MDATA

DSP_MADDR

DSP_MCMD

DSP_MCMDACEPT

ANT_CLK

ANT_MDATA

ANT_MADDR

ANT_MCMD

ANT_MDATAINFO

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© 2007 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. All other trademarks are the property of their respective owners. Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature, application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.

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3GPP Downlink Chip Rate v1.0

2

System DiagramFigure 2 shows the Downlink Chip Rate system diagram.

The FPGA is ideally suited for chip rate processing in both the Downlink and Uplink directions as itoffers fully parallel processing. Since the FPGA is fully programmable, it is possible to use a single HWrelease to support multiple platforms, such as a 32- or 256-Channel 3GPP DL or even other wirelessstandards.

The software and hardware interface to all versions of the core is identical, thus allowing reuse of codeand reduced system integration time. By using the parallel nature of the FPGA, the System can be easilyexpanded to target the most complex of end products. The efficient FPGA targeted coding methodol-ogy also allows the solution to target the low-end cost-critical solution by using Spartan-3 DSP technol-ogy.

Figure Top x-ref 2

Figure 2: Downlink Chip Rate System Diagram

Status Memory

SystemStatus

DS

P In

terf

ace

DataMemory

Channel Data

Config Memory

SectorConfig

Stream Config

Channel Config

Channel Based Processing

Slot Formatter

Symbol Mapper

TPC, TFCI Pilot Insertion

Memory Manager

STTD & Mode1

Encoder

Pilot Generate

Timing Offset

Phase Adjust

Stream Based Processing

Channel to Stream Mapping

Diversity Selection

Scramble Code

Generate

SpreadScramble

SpreadingCode

Generate

Weighting

Sector Based Processing

TcellTiming

TSTD & STDD

Encode

SCHGenerate

Combine

System Based Processing

System Timing

IRQ

Ant

enna

Inte

rfac

e

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System Specification

The System is based on a number of processing engines as shown in Figure 2. The Status Memory, DataMemory, and Configuration Memory use the independent dual feature of the Xilinx block RAM. Thisallows the DSP interface and the Antenna interface used to separate clocks as required. All dynamicallyconfigurable parameters are doubled buffered and internally synchronized within the core. The DataBuffer is a circular Slot based buffer which is dynamically allocated to minimize block RAM usagewithin the core.

The System Based Processing block provides all of the Frame based timing of the System and is used tosynchronize the DSP to the Radio. It also allows the DSP to configure the frequency of the synchronousinterrupts and thus reduce the overall latency of the System. This block also provides the status of theSystem to the DSP.

The Sector Based Processing block provides the generation of the SCH Channels. This includes inde-pendent TCELL timing offsets, diversity encoding, and SCH Channel weighting and combining.

The Channel Based Processing block provides the Slot formatting of the Channels. This includes: TPC,TFCI, and Pilot insertion; STTD and Mode1 encoding and phase rotation; Pilot generation based onChannel type and diversity mode; and one or two Frame Compressed Mode support and symbol map-ping based on QPSK or QAM16 symbol types. Channel Based Timing Offsets are also processed withinthis block.

The Stream Based Processing block provides the remaining Chip rate processing functions of the Sys-tem. This includes Channel-to-Stream Mapping and Spread and Scramble Code initialization and gen-eration. It also has the main data processing elements of Spreading and Scrambling, ChannelWeighting, and Channel Combining.

Table 1 shows the overall specification of the System. The core has three build options based on the tar-get application and target device used. Note that the maximum number of Channels, Cells, and Anten-nas supported is a multiple of the selected clock rate of the Antenna interface of the core. The coresupports all of the relevant requirements defined in the 3GPP standard except those shown in Table 2.

Table 1: System Specifications

Specification Parameter Comments

Maximum Number of Antenna

1, 16, or 32There are three standard build options based on the clock rate and the required number of antenna.

Maximum Number of Cells

1, 8, or 16Only 16 cells with diversity can be supported. Diversity can be supported on a per cell basis.

Maximum Number of Concurrent Channels

32, 128, or 256The channels can be divided into any Channel type.More channels can be added be using two cores.

Maximum Clock Rate64 x CR Virtex-4, Virtex-5 FPGAs

32 x CR Spartan-3A DSP FPGAs

Diversity

STTDMode1TSTDNone

All forms of diversity are supported

SHO Support SupportedAny Channel can be mapped to one or more Antenna allowing for soft handover to be supported.

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Flexibility

The FPGA inherently offers significant flexibility as it can be reconfigured in the field. Thus, futureupgrades can often be performed without the significant cost of upgrading the hardware. In addition,the Downlink Chip Rate architecture has been designed to support virtually any combination of Sec-tor/Channel configurations. It has also been designed to allow for future channels to be incorporatedwithout architectural modifications.

Compressed ModeAB

OFFOne-Frame or two-Frame Compressed Mode is supported.

Supported Channels

HS-DSCH HS-SCCH

DPCH P/S-SCH

P/S-CPICH E-HICH/E-R

CH P/S-CCPCH

AICH PICHMICH

E-AGCH F-DPCH

The actual number of each Channel type can be defined and configured.All Slot formats for all channels are supported. (see Appendix: 3GPP Downlink Channels)

AICH Pre-Combining NATo reduce the Channel usage for AICH, the symbol data can be pre-combined by the external DSP allowing a single HW Channel to support multiple AICH Channels.

Data Buffer Slots

Data is stored per slot to reduce the internal block RAM requirement and also the overall latency through the System. Therefore, it is a requirement of an external processor to service each active Channel on a Slot-by-Slot basis, where the execution of this task can be synchronized to a core generated interrupt.

Sector Initialization SupportedThe Scrambling Code of each Sector can be initialized to support any code within the standard.

Table 2: Omissions

Omission Comments

TDD Mode Not validated

DSCH Not required for FDD Mode

AP-AICH CPCH Access Preamble Acquisition Indicator Channel

CD/CA-ICH Collision Detection/Channel Assignment Indicator Channel

CSICH CPCH Status Indicator Channel

Table 1: System Specifications (Continued)

Specification Parameter Comments

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Scalability

The System can be scaled by selecting alternate build options. A larger System can be created by com-bining multiple cores with the addition of a combiner on the output and a core select on the bus input.

Core DescriptionThe following sections describe the Downlink Chip Rate core functionality.

System Considerations

It is intended that the core be driven by an internal/external processor where the core provides anaddress mapped register interface. The Downlink Antenna Interface is a high-speed streaming inter-face that connects to the digital front end (DFE) logic. See Figure 3.

DSP Interface

The Downlink Chip Rate core incorporates an address-mapped set of registers for configuration and isintended to be connected to an external processor as shown in Figure 1. These registers are classifiedinto four grouping types:

• Global Configuration

• Sector Configuration

• Channel Configuration

• Stream Configuration

Configuration registers are further broken into three timing related register classes:

• Static: Register is set up once before the selected function becomes operational.

• Frame Based: Register contains parameters that are applied on a Frame boundary.

• Slot Based: Register contains parameters that are applied on a Slot boundary.

Figure Top x-ref 3

Figure 3: Intended System Design

FPGA

Processor /DSP

DL-CRCore

ProcessorI/F Logic

Antenna I /F Logic

DFE

(e.g., CPRI)

(e.g., EMIF)

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Frame and slot based registers are double buffered internally within the core to decouple the externalprocessor accesses from the timing critical switchover on a Slot/Frame boundary.

The processor is responsible for updating the alternate buffer location on a per Slot or Frame boundary(Note that if the configuration is not updated, then the previously written configuration is used). Thecore maintains the status of each double buffer with respect to its current fill state. If a new buffer isfound to be available at the switchover point, the core selects the new buffer information. If the proces-sor writes to the currently active buffer, then the event occurs immediately. If the core writes to the inac-tive buffer twice before the switchover point, then the last write is used by the core.

DSP Synchronization

Synchronization between the core and an external processor is obtained by the use of a configurableinterrupt generated by the core. This interrupt is used to align Channel maintenance tasks executing onthe processor to the given channels requirements. (e.g., Channel data, configuration updates).

Antenna Interface

This is a high-speed unidirectional streaming interface producing a TDM data stream of combinedAntenna outputs. This interface also provides the Primary Frame Sync of the System based on Tcell=0.

Clocking Characteristics

The System requires two external clocks. These clocks can be asynchronous or driven from the samesource. DSP_CLK is used to clock memory mapped register accesses while ANT_CLK is used for theinternal Downlink processing and output interface. ANT_CLK is based on a fixed multiple of the basechip rate clock (3.84 MHz) where the multiple set depended on the selected build option. (See Table 18)

Latency

The internal latency of the core processing depends on the build option but, in all cases, is less than 10chips. This latency figure does not take into account the time taken to transfer the information into thecore from the external processor. All configuration information must be written to the core at least 10chips prior to the associated channels Slot or Frame boundary.

OCP Compatibility

The DSP and ANT interfaces are compatible to the OCP standard. The mission of OCP-IP is to addressproblems relating to design, verification, and testing that are common to IP core reuse in plug and playSystem-on-Chip (SoC) products.

More information on OCP can be found at www.ocpip.org.

Antenna and Sector Mapping

The antennas are mapped to sectors as shown in Table 3. The Antenna data is output in a TDM fashionstarting with Antenna 0.

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Channel and Stream Definition

Channel Definition

A Channel refers to any 3GPP Physical Channel.

• A single DPDCH and DPCCH require a single Channel Resource. If multiple DPDCH channels are supported per DPCCH, then multiple Channel Resources are required.

• AICH Pre-Combining is supported. Thus, a single Channel Resource can support all AICH channels within a sector.

• P-SCH and S-SCH use separate resources and are not counted within the Channel Resources.

• A Channel Resource provides both the Main and Diversity formatted data.

Stream Definition

A Stream refers to the resource required to map a Channel to an Antenna.

• If diversity is required on a Channel, then two Stream resources are required.

• If Soft Handover is required on a Channel Resource, then one Stream per Antenna is required.

Table 3: Antenna-to-Sector Mapping

Sector Main Antenna Diversity Antenna

0 0 1

1 2 3

2 4 5

3 6 7

4 8 9

5 10 11

6 12 13

7 14 15

8 16 17

9 18 19

10 20 21

11 22 23

12 24 25

13 26 27

14 28 29

15 30 31

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Channel-to-Stream Mapping

Any Channel can be mapped to any or multiple streams. See Figure 4, Figure 5, and Figure 6.

Setting up the Core

Initializing the System

To initialize the System, the System must be enabled and the interrupts configured. This is described inMain System Configuration Space.

Resetting the System

The core can be reset via the DSP OCP interface. However, this does not clear all registers to a knownstate as many of the registers are held in memory space. These can only be cleared by writing zeroes toall used memory locations within the core. After this has been done, the System is in a fully reset state.

Resetting via the OCP bus clears the System Enable and, thus, the outputs will be disabled.

System Timing and Interrupts

The timing of the System is created from within the core from a multiple of the Chip Rate.

64 x CR = 245.76 MHz

32 x CR = 122.88 MHz

8 x CR = 30.72 MHz

Figure Top x-ref 4

Figure 4: Stream and Channel Example without Diversity

Figure Top x-ref 5

Figure 5: Stream and Channel Example with Diversity

Figure Top x-ref 6

Figure 6: Stream and Channel Example with Diversity and Soft Handover (SHO)

DPDCH Channel

DPDCH Channel

Channel Stream Main Antenna

1 Channel Resource 1 Stream Resource

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DPDCH Channel

Channel Stream Main Antenna

1 Channel Resource 2 Stream Resources

Stream Diversity

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DPDCH Channel

Channel

Stream Main Antenna

1 Channel Resource 3 Stream Resources

Stream DiversityStream SHO Antenna

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A Primary Synchronization pulse is output on the Antenna interface if required.

The Interrupt controller can be configured to output an interrupt up to 10 times per slot (providing aninterrupt every 256 chips). This can be used to read the System status and determine the current Frame,Slot, and Sub-Slot number. This is described in IRQ_REGISTER.

Setting Up a 3GPP Sector

A Sector requires a minimum of a primary scramble code, scramble code group, P-SCH and S-SCHchannels, TCELL, and an Antenna map. The P-SCH and S-SCH channels require gain and diversityinformation.

These parameters are all configured via the Sector configurations registers as described inSECTOR_CFG and SECTOR_CFG_PER_FRAME.

After all sectors have been configured, the scramble code generator must be initialized. This is done bywriting to the SECTOR_INITIALIZE bit in the main System configuration register, as described in MainSystem Configuration Space.

Tearing Down a 3GPP Sector

Once configured, sectors can be disabled by simply clearing the Sector enable bit as described inSECTOR_CFG.

Reconfiguring an Active 3GPP Sector

Sector Reconfiguration Commands

The following configuration parameters are required to be reset to ensure valid operation of the system:

• Primary Scrambling Code• Antenna 1 ID• Antenna 2 ID• TCELL

Figure Top x-ref 7

Figure 7: Section Initialization

Sector Configuration

Set up Primary Scrambling CodesSet up TCELLSet up Antenna MapEnable Sector

All Sectors Configured?

Initialize Sectors

Set up S-SCH GainSet up P-SCH GainSet up Diversity Modes

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Frame Based Sector Configuration

The Frame Based Configuration parameters can be applied at any point during the Frame. The Down-link core applies the update at the next Frame boundary of the associated Sector (i.e., taking intoaccount any timing offset applied to the associated Sector (TCELL)).

All Frame Based Configurations parameters are double buffered. The control of the buffers is done bythe external processor. If the current active buffer is written to, this event occurs in hardware instanta-neously. If the alternate buffer is written to, the event is synchronized to the Frame boundary.

These parameters are described in SECTOR_CFG_PER_FRAME.

Setting up a 3GPP Channel

Any UMTS Channel (except SCH) can be configured using Channel and Stream resources. Each Chan-nel Type requires a different set of configuration parameters. Those parameters that are not required bya particular Channel Type are ignored.

Channels are enabled on a Frame boundary by the hardware so that all parameters must be configuredprior to the appropriate boundary. This can be determined by monitoring the IRQ_REGISTER registerwhich provides information on the Frame Number, Slot Number, and Sub-Slot Number for the System.

Once configured, Data and TPC information must be sent every slot (as necessary). Gain and Phaseinformation can be updated every slot if necessary.

These parameters are described in CHANNEL_CFG, CHANNEL_CFG_PER_FRAME,CHANNEL_CFG_PER_SLOT, CHANNEL_CFG_PER_SLOT, STR_CFG, STR_CFG_PER_FRAME,STR_CFG_PER_SLOT, and CHANNEL_DATA.

Figure Top x-ref 8

Figure 8: Sector Reconfigure

Sector Reconfiguration

Sector based Sync?

Reconfigure S-SCH GainReconfigure P-SCH GainReconfigure Diversity Modes

Yes

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Tearing Down a 3GPP Channel

Once configured, channels can be disabled by simply clearing the Channel Enable bit as described inCHANNEL_CFG.

Reconfiguring an Active a 3GPP Channel

Invalid Channel Reconfiguration Commands

The following Channel configuration parameters require the Channel to be torn down and re-enabledto ensure valid operation of the channel:

• Channel Type

• Channel Offset (TDPCH, TS-CCPCH, TF-DPCH)

Frame Based Configuration

The Frame Based configuration parameters can be applied at any point during the Frame. The Down-link core applies the update at the next Frame boundary of the associated Channel (i.e., taking intoaccount any timing offset applied to the associated Channel (TDPCH)).

All Frame Based Configurations parameters are double buffered. The control of the buffers is done bythe external processor. If the current active buffer is written to, then this event occurs in hardwareinstantaneously. If the alternate buffer is written to, then the event is synchronized to the Frame bound-ary.

Figure Top x-ref 9

Figure 9: Channel Initialization

Channel Initialization

Set up Channel typeSet up TDelayAllocate StreamsSet up Sector Mapping

Send TFCI InformationSend TPCI InformationSend First Slot Data

Wait for Channel FrameService Request

Interrupt

Set up Symbol GainSet up Diversity PhaseSet up Malloc InformationSet up Compressed Mode Params

Set up Slot FormatSet up Scrambling & Spreading codeSet up Diversity ModesSet up Compressed Mode

Enable Channel ResourceEnable Stream Resources

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The following parameters can be updated on a per Frame basis:

• Slot Format

• Channelization Code

• Secondary Scrambling Code

• Alternate Scrambling Code

• Diversity Mode

• Compressed Mode

• Changing the TFCI value

• Soft Handover

This is described in SECTOR_CFG_PER_FRAME, CHANNEL_CFG_PER_FRAME, andSTR_CFG_PER_FRAME.

Slot Based Configuration

The Slot Based configuration parameters can be applied at any point during the Frame. The Downlinkcore applies the update at the next Slot boundary of the associated Channel (i.e., taking into accountany timing offset applied to the associated Channel (TDPCH)).

All Slot Based Configuration parameters are double buffered. The control of the buffers is done by theexternal processor. If the current active buffer is written to, then this event occurs in hardware instan-taneously. If the alternate buffer is written to, then the event is synchronized to the Frame boundary.When changing the gain on the DPCH Channel, the update occurs at the start of the Pilot transmissionrather than the start of the slot.

The following parameters can be updated on a per Slot basis:

• Changing the TPC Value

• Diversity Phase

• Changing the Gain

The appropriate registers are CHANNEL_CFG_PER_SLOT and STR_CFG_PER_SLOT.

Memory Map

The product memory map (Table 4) is designed to support up to 16 Sectors, 256 Channels, and 1024Streams (this allows for future upgrades). Note that only active Sectors, Channels, and Streams will bebuild in hardware and, therefore, these addresses will be reserved and not accessible by the externalprocessor.

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Table 4: Memory Map

Address Offset Register Name Description

0x00000 HW_GENERICSGlobal Hardware Generics.Core VersionCore Type

0x00008 CORE_SPECIFIC_GENERICS

Core GenericsNumber of Supported SectorsNumber of Supported AntennasNumber of Supported StreamsNumber of Supported ChannelsMemory Size

0x00018 MAIN_SYSTEM_CONFIG

System Configuration registersSystem EnableInterrupt ConfigurationDebug Configuration

0x00038 IRQ_REGISTER

Interrupt Status RegisterFrame NumberSlot NumberSub-Slot Number

0x00040 SECTOR_CFG

Sector Configuration Registers (1 per sector)Sector EnablePrimary Scrambling CodeTCELL

0x00100

SECTOR_CFG_PER_FRAME

Sector Configuration per Frame (1 per sector)P-SCH GainS-SCH GainTSTDP-CCPCH STTD Encoded

Double Buffered and updated on a Frame boundary.

0x00180

0x00400 CHANNEL_CFG

Channel Configuration (1 per Channel)Channel EnableChannel TypeChannel Offset (TDPCH)

0x01000

CHANNEL_CFG_PER_FRAME

Channel Configuration per Frame (1 per Channel)Slot FormatDiversity ModeCompressed ModeCompressed Gap StartCompressed Gap EndEncoded TFCI


0x01800

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0x02000

CHANNEL_CFG_PER_SLOT

Channel Configuration per Slot (1 per Channel)TPC ValueDiversity Phase

Double Buffered and updated on a Slot boundary.0x02400

0x02800 CHANNEL_MALLOC_CFGChannel Memory Allocation (1 per Channel)Required MALLOC Space

0x03000 STR_CFG

Stream Configuration (1 per Stream)Stream EnableAssociated Channel IDAssociated Sector ID

0x04000

STR_CFG_PER_FRAME

Stream Configuration per Frame (1 per Stream)Diversity or MainChannelization CodeSecondary Scrambling CodeAlternate Scrambling Code


0x05000

0x08000

STR_CFG_PER_SLOT

Stream Configuration per Slot (1 per Stream)Data GainTPC GainTFCI GainPilot Gain

Double Buffered and updated on a Pilot boundary.0x0A000

0x20000 CHANNEL_DATA

Channel Data2 bit per Symbol16 QAM8 bit per Symbol

8 bit per symbol is used for AICH pre-combining.Before writing to this memory space a CHANNEL_MALLOC_CFG command for the Channel must be sent.

Table 4: Memory Map (Continued)

Address Offset Register Name Description

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HW_GENERICS

The Hardware Generics register provides the core type and the core version. These can be configured atbuild time to provide identification from the software layer of multiple builds and multiple versions.

CORE_TYPE

This provides the Xilinx 3GPP Library Core Type Indication.

The 3GPP Downlink Chip Rate core has CORE_TYPE = 0x0001.

CORE_VER

This provides the Downlink Chip Rate core Version Number.

CORE_SPECIFIC_GENERICS

The Hardware Generics register provides the core build generics. These can be configured at build timeto provide identification from the software layer of multiple configurations.

N_SECTORS

This provides the Number of Sectors Supported by the Downlink Chip Core.

N_ANTENNAS

This provides the Number of Antennas Supported by the Downlink Chip Core.

N_CHANNELS

This provides the Number of Channels Supported by the Downlink Chip Core.

N_STREAMS

This provides the Number of Streams Supported by the Downlink Chip Core.

CHANNEL_DATA_SIZE

This provides the size of the CHANNEL_DATA memory in 32 bit words.

Figure Top x-ref 10

Figure 10: Hardware Generics Register

Figure Top x-ref 11

Figure 11: Core Specific Generic Registers

HW_GENERICS_HEADER0x00000

0x00004

HW_GENERICS (READ ONLY REGISTER)

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

R CORE_VER CORE_TYPE

R

CORE_SPECIFIC GENERICS

CORE_SPECIFIC_HW_GENERICS (READ ONLY REGISTER)

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

0x00010

0x00008

0x0000C

0x00014

CHANNEL_DATA_SIZER

gainWidth N_SECTORSN_ANTENNAS

R N_CHANNELS

R

R

R

N_STREAMS

R

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Main System Configuration Space

The Main System Configuration (Figure 12) is used to enable the System timers and configure the inter-rupts. It also provides a status indicator for Sector initialization and interrupts acknowledgement input

The main System configuration space contains the following fields.

SYS_ENABLE

When set the main System counters are enabled. When clear, all System counters are inactive. There-fore, the core is effectively in a power down state. Note that the System can still be configured with theSystem disabled.

IRQ_ENABLE

When set, the IRQ output pin is enabled. Note that the System must be enabled for interrupts to occur.The timing of the interrupt is configurable using the TIMER_INTERRUPT_MASK.

TIMER_INTERRUPT_MASK

See Table 5. This 10-bit mask is used to individually enable an Interrupt on each 256 Chip Boundary.This enables the System to be configured to provide timing interrupts up to 10 times per slot and thusservice groups can be created based on the Timing Offset of the Channel (e.g., If a Channel Offset hasbeen configured to halfway through a slot the user may wish to allocate processor updates to thisChannel (configuration/Channel data) on TIMER_INTERRUPT(5)). This can be used to reduce theoverall latency of the System. Note that there is a small internal offset within the design to allow forpipeline latency.

Figure Top x-ref 12

Figure 12: Main System Configuration Registers

Table 5: Interrupt Mask Register

Main System Configuration Register Bit

12 11 10 9 8 7 6 5 4 3

TIMER_INTERRUPT(0...9)

9 8 7 6 5 4 3 2 1 0

MAIN_SYSTEM_CFG

SYSTEM_CFG

E: SYS_ENABLEIE: IRQ_ENABLER: ReservedSI: SECTOR_INITIALIZEDIA : IRQ_ACKNOWLEDGE

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

0x00020

0x00018

0x0001C

0x0002C

0x00030

0x00034

0x00038

0x0003C

R R TIMER_INTERRUPT_MASK

R

R

R

R

R

R

R

RSYMBOL_DEBUG_CFG

ANTENNA_DEBUG_CFG

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Note: When the IRQ_ENABLE is not set, no interrupts are produced.

• TIMER_INTERRUPT(0) – When set, this enables an interrupt on the Slot boundary of the System (TCELL=0)

• TIMER_INTERRUPT(1) – When set, this enables an interrupt on the Slot boundary + 256 Chips of the System (TCELL=0)



SECTOR_INITIALIZE

After enabling the Sectors, the scramble code generators must be initialized based on the primaryscramble code. This is done by setting the SECTOR_INITIALIZE bit.

IRQ_ACKNOWLEDGE (WRITE ONLY)

The interrupt is Active Low. After it has been received by the processor, the processor should set this bitto clear the interrupt pin. This bit is cleared by the hardware and, hence, is effectively write only (italways reads a zero).

IRQ_REGISTER

The IRQ Register (Figure 13) provides the status of the System and is read when an interrupt occurs. Itcan be used for System synchronization and for forming Service Groups to reduce overall Systemlatency. This register provides the latest status and not the status when the interrupt occurred. There-fore, it can also be used to validate that all channels have been serviced within the allowed serviceperiod.

Note: This register can be polled at any time to find the current status of the System.

FRAME_NUMBER

This is a 12-bit field providing the current Frame Number of the System. The LSB of this fields providesOdd and Even Frame indication (0=Even, 1=Odd).

SLOT_NUMBER

This is a 4-bit field providing the current Slot Number of the System. This counts from 0-14 (Slot 15 isnot valid).

SUB_SLOT

This is a 4 bit field providing the current Sub-Slot Number of the System. This count provides the 256Chip offset from the Slot boundary. This counts from 0-9 (10 sub-slots per slot).

Figure Top x-ref 13

Figure 13: Interrupt Status Registers

FRAME_NUMBERSLOT_NUMSUB_SLOTReserved

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

IRQ_Register0x00038

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18

SECTOR_CFG

Each Sector can be configured using its Sector Configuration register. All Channels must be disabledbefore sectors are configured. It is not currently possible to configure an individual Sector after a Sectoris active, because during the update process all the current active sectors are momentarily corrupted.

The Sector Configuration Register is used to:

• Enable sectors

• Initialize the primary scrambling code

• Initialize the scramble code group

• Set up TCELL

SECTOR_ENABLE (E)

When set, the Sector is enabled. When a Sector is enabled, P-SCH and S-SCH are both generated.

P_SCR_CODE

This is a 9-bit field providing the current Primary Scrambling Code and, thus, the Primary ScramblingCode Group for the Sector. The top 6 bits provide the Scrambling Code Group used by the S-SCH Chan-nel.

SL_DELAY, SUB_SL_DELAY

These two fields are used to configure the sectors TCELL offset.

SL_DELAY

This is a 4-bit field that sets TCELL offset in units of slots (i.e., 0-14).

Figure Top x-ref 14

Figure 14: Sector Configuration Registers

Figure Top x-ref 15

Figure 15: Scramble Code Field

SECTOR_CFG0x00040

0x00044

0x00048

0x0004C

0x0007C

SECTOR 2 (32)

SECTOR 3 (32)

...

SECTOR 15 (32)

SECTOR_CFG (not Ping/Pong)

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

R EP_SCR_CODESL_DELAYSUB_SL_DELAY

R EP_SCR_CODESL_DELAYSUB_SL_DELAY

9 7 6 5 4 3 2 18

SCRAMBLINGCODE GROUP

PRIMARY SCRAMBLING CODE

DS630_11_061107

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SUB_SL_DELAY

This is a 4-bit field that sets TCELL offset in units of 256 chips (i.e., 0-9). For example, to set TCELL to be2 slots and 1024 chips: SL_DELAY= 2, SUB_SL_DELAY = 4

SECTOR_CFG_PER_FRAME

When a Sector is enabled, P-SCH and S-SCH channels are generated and synchronized to TCELL. TheSCH channels can be updated on a per Frame basis. See Figure 16.

All Frame Based Configuration parameters are double buffered. The write control of the buffers isdown to the external processor. If the current active buffer is overwritten, then this event updates inhardware instantaneously and leads to indeterminate behavior in HW. If the alternate/unused buffer iswritten to, then this event is logged internally in hardware and the switchover to this buffer takes placeon the next Frame boundary.

P_SCH_WEIGHT

This is a 16-bit field which is used to apply a weighting to the P-SCH Channel. All weights are unsignedand of the format 16.15. The maximum weight is, therefore, 1.99. (However, it assumed that the weightswill be <=1.)

S_SCH_WEIGHT

This is a 16-bit field which is used to apply a weighting to the S-SCH Channel. All weight are unsignedand of the format 16.15. The maximum weight is, therefore, 1.99. (However, it assumed that the weightswill be <=1.)

PCCPCH_STTD_ENCODED (A)

This bit should be set to 1 when the associated P-CCPCH of the Sector is STTD Encoded.

TSTD_DIVERSITY (D)

Setting this bit enables TSTD Diversity on the SCH Channel for the Sector.

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20

CHANNEL_CFG

To configure any Channel (except SCH), the CHANNEL_CFG register is used (Figure 17). This pro-vides the Channel Configuration parameters for:

• Channel Enable

• Channel Type

• TDPCH

Figure Top x-ref 16

Figure 16: Sector Configuration per Frame Registers

Figure Top x-ref 17

Figure 17: Channel Configuration Registers

SECTOR_CFG_PER_FRAME Buffer

SECTOR 2

SECTOR 3

SECTOR 15

...

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

S_SCH WEIGHTD

P_SCH_WEIGHTR: Reserved A

R: Reserved

S_SCH WEIGHTD


R: Reserved

0x0011C

0x00178

0x0017C

0x00180

0x00100

0x00104

0x00108

0x0010C

0x00110

0x00114

0x00118

SECTOR 2

SECTOR 3

SECTOR 15

...

S_SCH WEIGHTD


R: Reserved

S_SCH WEIGHTD


R: Reserved

0x0019C

0x001F8

0x001FC

0x00184

0x00188

0x0018C

0x00190

0x00194

0x00198

A : PCCPCH_STTD_ENCODEDD : TSTD_DIVERSITY

Buffer A

Buffer B

Sector 0

Sector 1

Sector 0

Sector 1

CHANNEL_CFG0x00400

0x00404

0x00408

0x0040C

0x007FC

CHANNEL 2 (32)

CHANNEL 3 (32)

...

CHANNEL 255 (32)

CHANNEL_CFG (not Ping/Pong)

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

R ECHANNEL_TYPESL_DELAYSUB_SL_DLYReserved

R ECHANNEL_TYPESL_DELAYSUB_SL_DLYReserved

E: CHANNEL_ENABLE

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DS630 AugProduct Sp

CHANNEL_ENABLE

When set, this enables the Channel. The Channel Enable is synchronized by hardware to become activeon the next Frame boundary of the Channel. This is true when both enabling and disabling the Chan-nel. The other fields in the register should not be modified unless the Channel is disabled. It is valid toenable the Channel at the same time as setting the other fields (i.e., a single write access).

When the Channel is disabled, it cannot be reassigned until the next Frame. If the other fields arealtered while the Channel is enabled, the output of the Channel is unknown for up to 1 Frame.

CHANNEL_TYPE

This 6-bit field is used to define the Channel Type. The Channel Type is encoded as shown in Table 6.

SL_DELAY

This 4-bit field is used to assign TDPCH,TF-DPCH, or TSCCPCH to a Channel. It is also required to allow fora TCELL offset on any channel. The programmed delay.

Delay = TCELL + TDPCH

These are configured in terms of Slot and Sub-Slot Offsets. This field provides the Slot Offset informa-tion (0-14). Note that it is possible to apply an offset to any Channel.

SUB_SL_DLY

This 4-bit field is used to assign TDPCH,TF-DPCH, or TSCCPCH to a Channel. These are configured interms of Slot and Sub-Slot Offsets. This field provides the Sub-Slot Offset information (0-9). Note that tosupport TCELL, a Sub Slot is defined in terms of multiples of 256 Chips.

Table 6: Channel Type Mapping

CHANNEL CODE CHANNEL TYPE

0 Reserved

1 S-CPICH

2 P-CPICH

3 P-CCPCH

4 S-CCPCH

5 AICH

6 PICH

7 HS-SCCH

8 HS-DSCH

9 E-AGCH

10 MICH

11 DPCH

12 ERGCH

13 EHICH

14 F-DPCH

15-31 Reserved

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22

CHANNEL_CFG_PER_FRAME

The Channel Configuration per Frame registers (Figure 18) are set to define the Frame associatedparameters of the Channel, which are:

• Slot Format

• Diversity Mode

• Compressed Mode

• Compressed Mode Parameters (Gap Start and Gap End)

All Frame Based Configuration parameters are double buffered. If the current active buffer is overwrit-ten, this event updates in hardware instantaneously and leads to indeterminate behavior in HW. If thealternate/unused buffer is written to, this event is logged internally in HW and switchover to thisbuffer takes place on the next Frame boundary of the selected channel.

Figure Top x-ref 18

Figure 18: Channel Configuration per Frame Registers

ENCODED TFCI

gapEnd SLOT_FORMATgapSTART DMCM RRRR: Reserved

CHANNEL_CFG_PER_FRAME Buffer

CHANNEL 2

CHANNEL 3

CHANNEL255

...

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

ENCODED TFCI


0x0101C

0x017F8

0x017FC

0x01000

0x01004

0x01008

0x0100C

0x01010

0x01014

0x01018

ENCODED TFCI


CHANNEL 2

CHANNEL 3

CHANNEL255

...

ENCODED TFCI


0x0181C

0x01FF8

0x01FFC

0x01800

0x01804

0x01808

0x0180C

0x01810

0x01814

0x01818

DM : DIVERSITY_MODECM : COMPRESSED_MODE

Buffer A

Buffer B

Channel 0

Channel 1

Channel 0

Channel 1

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DS630 AugProduct Sp

SLOT_FORMAT

This 5-bit field is used to select the current Slot format. The number of alternate Slot formats per Chan-nel is given in the UMTS standard. See Table 7.

DIVERSITY_MODE

This 2-bit field is used to select the current diversity format of the channel. The alternate diversity modeencodings are given in Table 8. Note that the processor is responsible for selected a valid diversity typebased on the Channel type and Slot format.

Table 7: Valid Slot Formats per Channel Type

CHANNEL TYPE VALID SLOT FORMATS

S-CPICH 0

P-CPICH 0

P-CCPCH 0

S-CCPCH 0-17

AICH 0

PICH 0

HS-SCCH 0

HS-DSCH 0-1

E-AGCH 0

MICH 0

DPCH 0-16

ERGCH 0

EHICH 0

F-DPCH 0

Table 8: Diversity Mode Mappings

CODE DIVERSITY TYPE

00 No Diversity

01 Reserved

10 STTD

11 Closed Loop

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24

COMPRESSED_MODE

This 2-bit field is used to select the current Compressed format of the channel. The alternate Com-pressed Mode encodings are given in Table 9. Note that the processor is responsible for selecting a validCompressed mode based on the Channel type and Slot format

GAP_START

This defines the Compressed Gap start within the current Frame. If the Compressed Gap started in theprevious Frame, this field should be set to 15.

GAP_END

This defines the Compressed Gap end within the current Frame. If the Compressed Gap goes into thefollowing Frame, this field should be set to 15.

Note: GAP_START and GAP_END are only valid when in Compressed mode and both cannot be set to 15 at the same time.

CHANNEL_CFG_PER_SLOT

The Channel Configuration per Slot registers (Figure 19) are set to define the Slot associated parametersof the Channel, these are:

• TPC

• Diversity Phase

All Slot Based Configuration parameters are double buffered. The write control of the buffers is downto the external processor. If the current active buffer is overwritten, this event updates in hardwareinstantaneously and leads to indeterminate behavior HW. If the alternate/unused buffer is written to,this event is logged internally in HW and switchover to this buffer takes place on the next Slot bound-ary of the selected channel.

Table 9: Compressed Mode Mapping

CODE COMPRESSED TYPE

00 Normal

01 Reserved

10 Compressed Mode A

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TPC

This field is the TPC field of a DPCH or F-DPCH Channel. This field is ignored on all other Channeltypes. The hardware always transmits the last TPC field that was configured by the Processor.

DIVERSITY_PHASE

This 3-bit field sets the phase of the Diversity Output of the Channel (Table 10), as used by mode 1diversity.

Note: An adjustment to the gain is required when applying a rotation.

Figure Top x-ref 19

Figure 19: Channel Configuration per Slot Registers

Table 10: Diversity Phase Mapping

CODE Complex Multiplier

000 1+0j

001 1+1j

010 0+1j

011 -1+1j

100 -1+0j

101 -1-1j

110 0-1j

111 1-1j

CHANNEL_CFG_PER_SLOT Buffer

DPReserved

CHANNEL 2 (32)

CHANNEL 3 (32)

...

CHANNEL 255 (32)

0x02000

0x02004

0x02008

0x0200C

0x023FC

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

DPReserved

DPReserved

CHANNEL 2 (32)

CHANNEL 3 (32)

...

CHANNEL 255 (32)

0x02400

0x02404

0x02408

0x0240C

0x027FC

DPReserved

TPC

TPC

TPC

TPC

DP : DIVERSITY PHASE

Buffer A

Buffer B

Channel 0

Channel 1

Channel 0Channel 1

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26

CHANNEL_MALLOC_CFG

The Channel MALLOC Configuration registers (Figure 20) are used to define the Memory allocationrequirement of each Channel. This must be configured prior to any Channel data being written and canbe reconfigured every slot if required.

MALLOC_SPACE

This 10-bit field is used to configure the required memory space of the Channel in 32-bit words thathold the raw data for a single slot. The required memory allocation is dependent on the Channel Typeand the Slot format. See Table 11.

By defining the correct allocation of memory for the Slot, the overall memory usage can be balancedacross the System. The MALLOC_SPACE register must be written to before any data is written to theChannel for the current Slot.

Figure Top x-ref 20

Figure 20: Sector Channel Memory Allocation Registers

CHANNEL_MALLOC_CFG

CHANNEL_MALLOC (not Ping/Pong)

0x02800

0x02804

0x02808

0x0280C

0x023FC

MALLOC_SPACEReserved

CHANNEL 2 (32)

CHANNEL 3 (32)

...

CHANNEL 255 (32)

MALLOC_SPACEReserved

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

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DS630 AugProduct Sp

Table 11: Required Memory Allocation per Channel Type and Slot Format

Channel Type Slot FormatData Symbols

Per SlotBits Per Symbol

MALLOC Space

S-CPICH 0 0 0 0

P-CPICH 0 0 0 0

P-CCPCH 0 18 2 2

S-CCPCH

0 20 2 2

1 12 2 1

2 18 2 2

3 10 2 1

4 40 2 3

5 32 2 2

6 38 2 3

7 30 2 2

8 72 2 5

9 64 2 4

10 152 2 10

11 144 2 9

12 312 2 20

13 296 2 19

14 632 2 40

15 616 2 39

16 1272 2 80

17 1256 2 79

AICH 0 32 8 8

PICH 0 20 2 2

HS-SCCH 0 40 2 2

HS-DSCH0 320 2 20

1 640 2 (QAM) 40

E-AGCH 0 20 2 2

MICH 0 20 2 2

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28

DPCH

0

0 4 2 1

A 4 2 1

B 8 2 1

10 2 2 1

B 4 2 1

2

0 16 2 1

A 16 2 1

B 32 2 2

3

0 14 2 1

A 12 2 1

B 28 2 2

4

0 14 2 1

A 14 2 1

B 28 2 2

5

0 12 2 1

A 10 2 1

B 24 2 2

6

0 10 2 1

A 10 2 1

B 20 2 2

7

0 8 2 1

A 6 2 1

B 16 2 1

8

0 34 2 3

A 34 2 3

B 68 2 5

9

0 32 2 2

A 30 2 2

B 64 2 4

10

0 30 2 2

A 30 2 2

B 60 2 4

11

0 28 2 2

A 26 2 2

B 56 2 4

12

0 60 2 4

A 52 2 4

B 120 2 8

13

0 140 2 9

A 132 2 9

B 280 2 18

14

0 288 2 18

A 280 2 18

B 576 2 36

15

0 608 2 38

A 600 2 38

B 1216 2 76

160 1248 2 78

A 1240 2 78

Table 11: Required Memory Allocation per Channel Type and Slot Format (Continued)



MALLOC Space

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DS630 AugProduct Sp

STR_CFG

The Stream Configuration registers (Figure 21) are used to define the Stream mappings:

• Stream Enable

• Channel Mapping

• Sector Mapping

A Stream can be mapped to any Channel and Sector allowing full flexibility of allocation of resources.Thus, a single Channel could be mapped to all of the streams in a broadcast type scenario (in this typeof system, this would be for diversity or handover situations).

A Stream can be reconfigured to another Channel by firstly disabling the Stream and then re-enablingit to a new Channel. A Stream is enabled instantly to the output of the Channel.

STREAM_ENABLE

This bit is set to enable the stream. Enabling or disabling the Stream occurs immediately. If the associ-ated Channel or Sector is not enabled, the output is disabled.

CHANNEL_ID

This 8-bit field assigns a Channel to the associated Stream.

SECTOR_ID

This 4-bit field assigns a Sector to the associated Stream.

ERGCH 0 40 2 2

EHICH 0 40 2 2

F-DPCH 0 0 0 0

Figure Top x-ref 21

Figure 21: Stream Configuration Registers

Table 11: Required Memory Allocation per Channel Type and Slot Format (Continued)



MALLOC Space

STR_MAP

STR_MAP (not Ping/Pong)

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

0x03000

0x03004

0x03008

0x0300C

0x03FFC

STREAM 2 (32)

STREAM 3 (32)

...

STREAM 1023 (32)

ECHANNEL_IDReservedSECTOR_IDReserved

ECHANNEL_IDReservedSECTOR_IDReserved

E: STREAM_ENABLE

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30

STR_CFG_PER_FRAME

The Stream Configuration per Frame registers (Figure 22) are set to define the Frame associated param-eters of the Channel, which are:

• Diversity

• Spreading Code

• Secondary Scrambling Code

• Alternate Scrambling Code

All Frame Based Configuration parameters are double buffered. If the current active buffer is overwrit-ten, this event updates in hardware instantaneously and leads to indeterminate behavior in HW. If thealternate/unused buffer is written to, this event is logged internally in HW and switchover to thisbuffer takes place on the next Frame boundary of the selected channel.

DIVERSITY_SELECT

When set, the Stream is associated with the Diversity Symbols output from the Outer core. When clear,the Stream is associated with the Normal output.

Figure Top x-ref 22

Figure 22: Stream Configuration per Frame Registers

STR_CFG_PER_FRAME Buffer

0x04000

0x04004

0x04008

0x0400C

0x04FFC

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

AC DSSPR_CODEReservedSEC_SCRReserved


STREAM 2

STREAM 3

...

STREAM 1023



STREAM 2

STREAM 3

...

STREAM 1023

0x05000

0x05004

0x05008

0x0500C

0x05FFC

DS : DIVERSITY_SELECTAC : ALTERNATE_CODE

Buffer A

Buffer B

Stream 0Stream 1

Stream 0Stream 1

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DS630 AugProduct Sp

SPR_CODE

This 10-bit field sets the channelization code of the Stream (Table 12). This is configured with the sumof the Spreading Factor + the Channel Code.

Table 12: Spreading Code Mapping

SPR_CODE CHANNEL CODE SPREADING FACTOR

4 0

45 1

6 2

7 3

8 0

89 1

…

15 7

16 0

1617 1

…

31 15

32 0

3233 1

…

63 31

64 0

6465 1

…

127 63

128 0

128129 1

…

255 127

256 0

256257 1

…

511 255

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32

SEC_SCR

This 4-bit field selects one of the 16 secondary scrambling codes for the associated stream.

ALTERNATE_CODE

This 4-bit fields sets the alternate scrambling code of the associated stream. This is used in CompressedMode and the operation is described in the standard. See Table 13.

STR_CFG_PER_SLOT

The Stream Configuration per Slot registers (Figure 23) are set to define the slot associated parametersof the Stream, these are:

• Symbol Gain per slot

All Slot Based Configuration parameters are double buffered. The write control of the buffers is downto the external processor. If the current active buffer is overwritten, this event updates in hardwareinstantaneously and leads to indeterminate behavior in HW. If the alternate/unused buffer is writtento, this event is logged internally in HW and switchover to this buffer takes place on the next PowerControl boundary of the selected channel.

In the case of the DCH Channel, this will be synchronized to the start of the Pilot bits.

The HSDPA Channels will only be updated every third slot synchronous with the Channel timing. Allother Channels are updated every slot.

512 0

512513 1

…

1023 511

Table 13: Alternate Code Mapping

CODE Alternate Code

00 Normal

01 Reserved

10 Left

11 Right

Table 12: Spreading Code Mapping (Continued)

SPR_CODE CHANNEL CODE SPREADING FACTOR

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DS630 AugProduct Sp

GAIN_DATA_STREAM

This 16-bit field is used to apply a weighting to the Data Field of the associated Stream Symbol Data. Allweights are unsigned and of the format 16.15. The maximum weight is, therefore, 1.99. (However, itassumed that the weights will be <=1.) If the associated Channel Type does not contain this symboltype, this field is ignored.

GAIN_TPC_STREAM

This 16-bit field is used to apply a weighting to the TPC Field of the associated Stream Symbol Data. Allweights are unsigned and of the format 16.15. The maximum weight is, therefore, 1.99. (However, it isassumed that the weights will be <=1.) If the associated Channel Type does not contain this symboltype, this field is ignored.

GAIN_TFCI_STREAM

This 16-bit field is used to apply a weighting to the TFCI Field of the associated Stream Symbol Data.All weights are unsigned and of the format 16.15. The maximum weight is, therefore, 1.99. (However,it assumed that the weights will be <=1.) If the associated Channel Type does not contain this symboltype, this field is ignored.

GAIN_PILOT_STREAM

This 16-bit field is used to apply a weighting to the Pilot Field of the associated Stream Symbol Data. Allweights are unsigned and of the format 16.15. The maximum weight is, therefore, 1.99. (However, itassumed that the weights will be <=1.) If the associated Channel Type does not contain this symboltype, this field is ignored.

Figure Top x-ref 23

Figure 23: Stream Configuration per Slot Registers

STR_CFG_PER_SLOT Buffer

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

0x0801C

0x08FF8

0x08FFC

0x08000

0x08004

0x08008

0x0800C

0x08010

0x08014

0x08018

GAIN_TPC STREAM GAIN_DATA STREAM

GAIN_PILOTS STREAM GAIN_TFCI STREAM

STREAM 2

STREAM 3

STREAM 1023

...



0x0A01C

0x0AFF8

0x0AFFC

0x0A0000x0A004

0x0A008

0x0A00C

0x0A010

0x0A014

0x0A018



STREAM 2

STREAM 3

STREAM 1023

...



Buffer A

Buffer B

Stream 0

Stream 1

Stream 0

Stream 1

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34

CHANNEL_DATA

The Channel Data memory space (Figure 24) is used to hold the Data symbols for all of the Channels.The actual space allocated for each channel, in hardware, is set by the CHANNEL_MALLOC_CFG reg-ister. Writing to the Channel outside of its allocated memory can corrupt the memory of another chan-nel.

Writing to the first address of a Channel Data block automatically allocates a new block of memorybased on the CHANNEL_MALLOC_CFG register. Memory is allocated in a circular nature. Thus, theSystem design must ensure that internal memory exists to support the total number of Channels andthe worst case Bandwidth in any given pair of Slots.

Data is written on a per slot basis for all channels except P-CCPCH. P-CCPCH, which is written on a2-slot basis because of it having different slot formatting on consecutive slots.

The Channel Data writes must commence before the end of previous slot. The full block of data doesnot need to be written within the previous slot, but must clearly be available before it is transmitted.

The Channel Data memory space is used to hold the Data symbols for all of the Channels. The actualspace allocated for each channel, in hardware, is set by the CHANNEL_MALLOC_CFG register. Writ-ing to the Channel outside of its allocated memory can corrupt the memory of another channel.

Writing to the first address of a Channel Data block automatically allocates a new block of memorybased on the CHANNEL_MALLOC_CFG register. Memory is allocated in a circular nature (Figure 25).Thus, the System design must ensure that internal memory exists to support the total number of Chan-nels and the worst case Bandwidth in any given pair of slots.

Data is written on a per slot basis for all channels except P-CCPCH. P-CCPCH, which is written on a2-slot basis because of it having different slot formatting on consecutive slots.

The Channel Data writes must commence before the end of previous slot. The full block of data doesnot need to be written within the previous slot but must clearly be available before it is transmitted.

Figure Top x-ref 24

Figure 24: Sector Channel Data Memory

CHANNEL_DATA_CFG0x20000

0x20004

...

0x2001FC

0x2003F8

CHANNEL_CFG (not Ping/Pong)

Data

Data

Data

Data

Data

Data

Data

Data

CHANNEL 2 (128 x 32)

...

CHANNEL 255 (128 x 32)

0x27FFC

...

0x27E00

0x27E04

0x2003FC

0x2005FC

...

0x200400

0x200404

0x200200

...

16 15 14 13 12 11 10 924 23 22 21 20 19 18 1731 30 29 28 27 26 25 7 6 5 4 3 2 18 0

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DS630 AugProduct Sp

Data is written in symbols starting with the LSB of the Channel Data. For all Channel types exceptAICH and HS_DSCH Slot Format 1, 2 bits are required per symbol. This allows for DTX to be transmit-ted if required. SeeTable 14.

The AICH Channels can be pre-combined by the external processor to reduce Channel and Streamresources. These are written in 8-bit signed format and are sent to the inner core as written.

The QAM16 Channel does not require DTX and, thus, is encoded more efficiently. In this case, the sym-bols are written as 2 bit I and 2 bit Q. The symbol bits are written 1 bit per bit and are the first Transmit-ted bit written to the LSB of the Data Register.

All other channels use 2 bit encoding even is DTX is not supported.

Although each Channel is allocated, a fixed area of address space (0x00200) internally the actual spacesetup by CHANNEL_MALLOC_CFG remaps the Channel memory usage transparently into a local cir-cular buffer.

For the two supported hardware configurations, the internal circular buffer size is:

• 32-Channel HW configuration = 512 x 32 bit

• 256-Channel HW configuration = 4096 x 32 bit

The circular buffer can maintain two buffers for each Channel (i.e., slot-based ping-pong buffer).

Table 14: Symbol to Bit Encoding (Non AICH and QAM Channels)

Symbol Bit Encoding

0 01

1 11

DTX 00

Invalid 10

Figure Top x-ref 25

Figure 25: Channel Data Internal Circular Buffer

Illegal Memory Space(Writing to Un-malloced space may corrupt other channels)

Ch 1 Data

Ch 1 Data

Ch 1 Data

Ch 1 Data

Ch 1 Data

0x20000

0x20004

0x2001FC

Internal Circular Buffer

0x20008

...

Channel 0Memory Space

0x2000C0x20010

0x20014

Channel 0Maloc Space = 3

0x20200

0x20204

0x2002FC

0x20208

...

0x2020C0x20210

0x20214

Channel 1Maloc Space = 5

Channel 1Memory Space

Data

Data

Illegal Memory Space(Writing to Un-malloced space may corrupt other channels)

Data

Data

Data

Data

Data

Data

Ch 0 Data

Ch 0 Data

Ch 0 Data

Available

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36

The user must not overfill this buffer. Therefore, the maximum MALLOC space is:

2 x (All channels MALLOC space) internal circular buffer size

Core Pinout

Figure 26 shows the core pinout. The core is based on two main interfaces: the DSP interface (Table 15)and the Antenna Interface (Table 16).

Table 15: DSP OCP Port – Processor Interface

Name Width Direction Description

DSP_CLK 1 Input

Clock signal for the DSP I/F. All DSP interface signals are synchronous to the rising edge of DSP_CLK. 64 x CR: DSP_CLK max = 122.88 MHz32 x CR: DSP_CLK max = 61.44 MHz8 x CR: DSP_CLK max = 61.44 MHzNote that the ANT_CLK and the DSP_CLK do not need to be synchronous.

RESET 1 Input

Active High reset. Note that reset does not clear all registers as they are mainly stored within the Block Memory. These can only be cleared by writing a zero to each address.

DSP_MDATA 32 InputWrite data. This field carries the write data from the master to the slave.

DSP_MADDR 22 InputInput Address. This field carries the address from the master. Note that 32-bit addressing is used and, thus, bit 0 and 1 are ignored.

DSP_MCMD 3 Input

Transfer command. This signal indicates the type of OCP transfer the master is requesting. For this interface, Read, Write, and Idle are supported and, thus, this bus is either:000 (Idle)001 (Write)010 (Read)

DSP_SCMDACCEPT 1 OutputSlave accepts transfer. A value of 1 on the SCMDACCEPT signal indicates that the slave accepts the master’s transfer request.

DSP_SRESP 2 Output

Response field from the slave to a transfer request from the master.00 (denotes a NULL response)01 (denotes a Valid response)The other modes are not supported.

DSP_SDATA 32 OutputThis field carries the requested read data from the slave to the master.

DSP_SINTERRUPT 1 OutputExternal Active Low Interrupt. This is used to provide System timing information for Frames, Slots, and Sub-Slots.

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Core Generator Options

Table 17 contains the user selectable build options.

Note: Larger systems can be created by instantiating multiple cores.

Table 16: OCP Antenna Interface

Port Name Width I/O Description

ANT_CLK 1 Input

Chip rate clock. This is the main System clock and must be clocked at the correct rate as defined by the clock speed generic. Note that the clock rate is defined as a multiple of the 3.84 MHz Chip rate. 64 x CR = 245.76 MHz32 x CR = 122.88 MHz8 x CR = 30.72 MHz

ANT_MDATA 32 Output Fixed point interleaved Antenna I&Q data.

ANT_MADDR 5 Output ID of the Antenna associated with the Antenna Data.

ANT_MCMD 3 OutputSignifies that the output data is valid;000 (Idle)001 (Write)

ANT_MDATAINFO 1 OutputPrimary Frame Sync of the System based on Tcell = 0.This is single pulse every 10 ms which is valid High for the first Chip of each Antenna.

Table 17: User Selectable Build options

Option Antennas SectorsChannels/Streams

Data Buffer Size

Clock Rate

Option 1 1 1 32 512 x 32 8 x CR

Option 2 16 8 128 2048 x 32 32 x CR

Option 3 32 16 256 4096 x 32 64 x CR

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Core Signal Operation

DSP Write Cycle

The DSP I/F is an OCP compatible slave interface. The write interface is a single clock cycle and, thus,can be used to support bursts. See Figure 26.

DSP Read Cycle

The read interface is a multiple clock cycle interface. This is due to the high level of pipelining in thedesign. The read interface of the core is only required when an interrupt occurs or during debug andhence the performance is not as critical as the write interface. The number of clock cycles taken torespond depends on the register being accessed. Data is valid when the DSP_SRESP is High. SeeFigure 27.

Figure Top x-ref 26

Figure 26: DSP IF OCP Write Cycle Waveform

Figure Top x-ref 27

Figure 27: DSP IF OCP Read Cycle Waveform

DSP_MCLK

DSP_MADDR

DSP_MDATA

DSP_MCMD

DSP_SCMDACCEPT

DSP_SRESP

DSP_SDATA

‘001004’h=Addr

OCP_MST_IDLE OCP_MST_WR OCP_MST_IDLE

OCP_SLV_NULL OCP_SLV_DVA

‘12345678’h=Data

‘00000000'h

OCP_SLV_NULL

ds630_27_061507

DSP_MCLK

DSP_MADDR

DSP_MDATA

DSP_MCMD

DSP_SCMDACCEPT

DSP_SRESP

DSP_SDATA

‘001004’h=Addr

OCP_MST_IDLE OCP_MST_RD OCP_MST_IDLE

OCP_SLV_NULL OCP_SLV_DVA

‘00000000'h

OCP_SLV_NULL

‘12345678’h

ds630_28_061507

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Antenna Write Cycle

The Antenna interface is an OCP compatible streaming interface. It cannot be halted by the slave as itis synchronized to the main System Frame timing. Note that the DSP can halt the System by togglingthe main System Enable bit. The output is an interleaved stream of all the antennas starting withAntenna 0. See Figure 28.

Figure 29 shows the 32 x CR Antenna Interface. This shows to initial Primary Frame Sync(ANT_MDATAINFO) of the simulation. Only Sector 1 has TCELL set to zero and, thus, all other sectorsoutput zero in the ANT_MDATA field.

Figure Top x-ref 28

Figure 28: 8 x CR Antennal IF Waveform

Figure Top x-ref 29


ANT_CLK

ANT_MADDR

ANT_MDATA

ANT_MCMD

ANT_MDATAINFO

Data

OCP_MST_IDLE

OCP_MST_WR

OCP_MST_IDLE

‘00'h

‘00000000’h ‘00000000’h Data

OCP_MST_WR

Frame Sync

‘00000000’h

OCP_MST_IDLE

Data Valid every 8th Clk

ds630_2_061507

0 1 2 3 4 5 6 7 8 9 10 11 1215

ANT_CLK

ANT_MADDR

ANT_MDATA

ANT_MCMD

ANT_MDATAINFO

Data‘00000000’h ‘00000000’h Data

Frame Sync

‘00000000’h

13 14 15 0 1 2 3 4

Data Data

Sector 0 Sector 7

I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I

Main, Div Main, Div

ds630_30_061507

I = OCP_MST_IDLEW = OCP_MST_WR

Note:

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Figure 30 shows the 64 x CR Antenna Interface. This shows the initial Primary Frame Sync(ANT_MDATAINFO) of the simulation. Only Sectors 1 and 13 have TCELL set to zero and, thus, allother sectors output zero in the ANT_MDATA field.

Core Resource UtilizationThe solution is 3GPP Release 6 Compliant. All slot formats and modes are supported unless otherwisestated. See Table 18.

Figure Top x-ref 30


Table 18: Core Resource Utilization

OptionTarget Device

FamilySlices

Block RAMs

DSP48s Target Part

32 Channels, 32 Streams

Spartan-3A DSP 3,470 44 2 XC3SD3400A

128 Channels,128 Streams

Spartan-3A DSP 4,935 52 2 XC3SD3400A


Virtex-4 5,855 54 2 XC4VSX25


Virtex-5 3,113 40 2 XC5VSX35

0 1 2 3 4 5 6 731 25 26 27 28 29 30 31

ANT_CLK

ANT_MADDR

ANT_MDATA

ANT_MCMD

ANT_MDATAINFO

Data‘00000000’h ‘00000000’h Data

Frame Sync

‘00000000’h

0 1 2 3 4

Data Data

Sector 0 Sector 15

Main, Div

I = OCP_MST_IDLEW = OCP_MST_WR

I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I W I

Data Data ‘00000000’h

Main, Div Main, Div

Note:ds631_31_061507

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Appendix: 3GPP Downlink Channels

Physical Channels

Physical channels are defined by a specific carrier frequency, scrambling code, channelization code(optional), time start and stop (giving a duration) and, on the uplink, relative phase (0 or p/2). TheDownlink E-HICH and E-RGCH are each further defined by a specific orthogonal signature sequence.Scrambling and channelization codes are specified in TS25.213. Time durations are defined by start andstop instants, measured in integer multiples of chips. Suitable multiples of chips also used in specifica-tion are:

• Radio Frame:A radio Frame is a processing duration which consists of 15 slots. The length of a radio Frame corresponds to 38400 chips.

• Slot:A slot is a duration which consists of fields containing bits. The length of a slot corresponds to 2560 chips.

• Sub-Frame:A sub-Frame is the basic time interval for E-DCH and HS-DSCH transmission and E-DCH and HS-DSCH-related signaling at the physical layer. The length of a sub-Frame corresponds to 3 slots (7680 chips).

The default time duration for a physical Channel is continuous from the instant when it is started to theinstant when it is stopped. Physical channels that are not continuous will be explicitly described.

Transport channels are described (in more abstract higher layer models of the physical layer) as beingcapable of being mapped to physical channels. Within the physical layer itself, the exact mapping isfrom a composite coded transport Channel (CCTrCH) to the data part of a physical channel. In additionto data parts, there also exist Channel control parts and physical signals.

Downlink Transmit Diversity

Table 19 summarizes the possible application of open and closed loop transmit diversity modes on dif-ferent Downlink Physical Channel types. Simultaneous use of STTD and closed loop modes on thesame physical Channel is not allowed. In addition, if Tx diversity is applied on any of the DownlinkPhysical Channels it shall also be applied on P-CCPCH and SCH. Regarding CPICH transmission incase of transmit diversity the same scrambling and channelization codes are used, but a differentsequence is transmitted on each antenna.

Transmit Diversity is activated on a per Channel basis by higher layers.

Associations of channels are described in the TS25.211 specification.

Table 19: Application of Transmit Diversity Mode on Downlink Physical Channel

Physical Channel Type

Open Loop Mode Closed Loop Mode

TSTD STTD Mode 1

P-CCPCH – X –

SCH X – –

S-CCPCH – X –

DPCH – X X

F-DPCH – X –

PICH – X –

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Open Loop Transmit Diversity

Open loop transmit diversity is a simple re-encoding of symbols before Spreading and Scramblingoccur. This is described in full in TS25.211

Closed Loop Transmit Diversity

Closed loop transmit diversity is described in the TS25.214 specification. Channel coding, interleaving,and Spreading are done as in non-diversity mode. The spread complex valued signal is fed to both TXAntenna branches, and weighted with Antenna specific weight factors w1 and w2. The weight factor w1is a constant scalar and the weight factor w2 is complex valued signal.

The weight factor w2 (actually the corresponding phase adjustment) is determined by the UE, and sig-nalled to the UTRAN access point (i.e., cell transceiver) using the FBI field of Uplink DPCCH.

For the closed loop mode 1, different orthogonal dedicated Pilot symbols in the DPCCH are sent on thetwo different antennas.

Dedicated Downlink Physical Channels

There are four types of downlink dedicated physical channels, the Downlink Dedicated Physical Chan-nel (Downlink DPCH), the Fractional Dedicated Physical Channel (F-DPCH), the E-DCH RelativeGrant Channel (E-RGCH), and the E-DCH Hybrid ARQ Indicator Channel (E-HICH).

Downlink DPCCH and DPDCH

Within one Downlink DPCH, dedicated data generated at Layer 2 and above, i.e., the dedicated trans-port Channel (DCH), is transmitted in time-multiplex with control information generated at Layer 1(known Pilot bits, TPC commands, and an optional TFCI). The Downlink DPCH can thus be seen as atime multiplex of a Downlink DPDCH and a Downlink DPCCH.

MICH – X –

HS-PDSCH – X X

HS-SCCH – X –

E-AGCH – X –

E-RGCH – X –

E-HICH – X –

AICH – X –

Notes:

1. “X” = Transmit diversity can be applied.2. “–” = Transmit diversity cannot be applied.

Table 19: Application of Transmit Diversity Mode on Downlink Physical Channel (Continued)

Physical Channel Type

Open Loop Mode Closed Loop Mode

TSTD STTD Mode 1

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Figure 31 shows the Frame structure of the Downlink DPCH. Each Frame of length 10 ms is split into 15Slots, each of length Tslot = 2560 Chips, corresponding to one power-control period.

Full details of the DPCH Channel is described in TS25.211. In summary:

• Spreading factor range from 512 down to 4.

• Number of pilots ranges from 2 to 16. In STTD mode, the Pilots per Antenna differ. In addition, the Pilot bits per Slot also differ and thus can also be used to confirm Frame sync. All the Pilots are generated within the core and inserted into the data stream.

• Number of TPC bits ranges from 2 to 16. All TPC bits have the same value. The TPC value is software programmable on a slot-by-slot basis. TPC insertion is carried out by the core.

• Number of TFCI bits range from 0 to 16. The 32-bit TFCI word is software programmable on a Frame-by-Frame basis. Bit repetition in Compressed Mode and bit insertion is carried out by the core.

• There are basically two types of Downlink Dedicated Physical Channels; those that include TFCI (e.g., for several simultaneous services) and those that do not include TFCI (e.g., for fixed-rate services).

• In compressed Frames, a different slot format is used compared to normal mode.

• Multicode transmission is not supported by this design.

• Power scaling can be performed on all symbol types. These are software programmable on a slot-by-slot basis and updated at the start of the Pilot field.

• A time offset can be applied to the DPCH Channel (TDPCH). Timing synchronization is carried out

by the core basis on the TCELL and TDPCH offset.

Figure Top x-ref 31

Figure 31: Frame Structure for Downlink DPCH

DPDCH DPCCH DPDCH DPCCH

Data 1 TPC TFCI Data2 PilotN bitsdata1 N bitsTPC N bitsTFCI N bitsdata2 N bitspilot

Tslot - 2560 chips, 10 x 2 bits (k - 0...7)k

Slot #0 Slot #4 Slot #i Slot #14

One radio frame, T = 10 msf ds630_33_061107

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Table 20 shows the supported Slot formats of the DPCH channel.

Table 20: DPCCH and DPDCH Fields

Slot Format

#i

Channel Bit Rate (kbps)

Channel Symbol

Rate (ksps)

SFBits per Slot

DPDCHBits per Slot

DPCCHBits per Slot

Transmitted Slots per

Radio Frame

NTrNData1 NData2 NTPC NTFCI NPilot

0 15 7.5 512 10 0 4 2 0 4 15

0A 15 7.5 512 10 0 4 2 0 4 8-14

0B 30 15 256 20 0 8 4 0 8 8-14

1 15 7.5 512 10 0 2 2 2 4 15

1B 30 15 256 20 0 4 4 4 8 8-14

2 30 15 256 20 2 14 2 0 2 15

2A 30 15 256 20 2 14 2 0 2 8-14

2B 60 30 128 40 4 28 4 0 4 8-14

3 30 15 256 20 2 12 2 2 2 15

3A 30 15 256 20 2 10 2 4 2 8-14

3B 60 30 128 40 4 24 4 4 4 8-14

4 30 15 256 20 2 12 2 0 4 15

4A 30 15 256 20 2 12 2 0 4 8-14

4B 60 30 128 40 4 24 4 0 8 8-14

5 30 15 256 20 2 10 2 2 4 15

5A 30 15 256 20 2 8 2 4 4 8-14

5B 60 30 128 40 4 20 4 4 8 8-14

6 30 15 256 20 2 8 2 0 8 15

6A 30 15 256 20 2 8 2 0 8 8-14

6B 60 30 128 40 4 16 4 0 16 8-14

7 30 15 256 20 2 6 2 2 8 15

7A 30 15 256 20 2 4 2 4 8 8-14

7B 60 30 128 40 4 12 4 4 16 8-14

8 60 30 128 40 6 28 2 0 4 15

8A 60 30 128 40 6 28 2 0 4 8-14

8B 120 60 64 80 12 56 4 0 8 8-14

9 60 30 128 40 6 26 2 2 4 15

9A 60 30 128 40 6 24 2 4 4 8-14

9B 120 60 64 80 12 52 4 4 8 8-14

10 60 30 128 40 6 24 2 0 8 15

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Fractional Dedicated Physical Channel (F-DPCH)

The F-DPCH carries control information generated at layer 1 (TPC commands). It is a special case ofDownlink DPCCH where only power control is used. The slot format is fixed. The SF is 256, 2 TPC bitsare transmitted per slot. The rest of the slot the Tx is off. This used in FDD only.

STTD-based open loop transmit diversity can also be applied. The TPC field is software programmableand can be updated on a slot-by-slot basis.

E-DCH Relative Grant Channel (E-RGCH)

The E-RGCH carries a simple signature pattern representing an increment to the terminal's currentgrant rate. There are three valid values: UP, DOWN and HOLD. Serving Node-Bs may transmit any ofthese commands; non-serving Node-Bs may only request HOLD or DOWN. As for the E-HICH, trans-mission is at SF128 (40 ternary values), and the signature is repeated for a whole E-DCH TTI (that is,either 3, 12 or 15 times). E-RGCH signature sequence are defined in TS25.211 and given by higher lay-ers.

STTD-based open loop transmit diversity can also be applied.

10A 60 30 128 40 6 24 2 0 8 8-14

10B 120 60 64 80 12 48 4 0 16 8-14

11 60 30 128 40 6 22 2 2 8 15

11A 60 30 128 40 6 20 2 4 8 8-14

11B 120 60 64 80 12 44 4 4 16 8-14

12 120 60 64 80 12 48 4 8* 8 15

12A 120 60 64 80 12 40 4 16* 8 8-14

12B 240 120 32 160 24 96 8 16* 16 8-14

13 240 120 32 160 28 112 4 8* 8 15

13A 240 120 32 160 28 104 4 16* 8 8-14

13B 480 240 16 320 56 224 8 16* 16 8-14

14 480 240 16 320 56 232 8 8* 16 15

14A 480 240 16 320 56 224 8 16* 16 8-14

14B 960 480 8 640 112 464 16 16* 32 8-14

15 960 480 8 640 120 488 8 8* 16 15

15A 960 480 8 640 120 480 8 16* 16 8-14

15B 1920 960 4 1280 240 976 16 16* 32 8-14

16 1920 960 4 1280 248 1000 8 8* 16 15

16A 1920 960 4 1280 248 992 8 16* 16 8-14

Table 20: DPCCH and DPDCH Fields (Continued)

Slot Format

#i


Channel Symbol

Rate (ksps)

SFBits per Slot

DPDCHBits per Slot

DPCCHBits per Slot

Transmitted Slots per

Radio Frame

NTrNData1 NData2 NTPC NTFCI NPilot

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E-DCH Absolute Grant Channel (E-AGCH)

The E-DCH Absolute Grant Channel (E-AGCH) is a fixed rate (30 kbps, SF=256) Downlink PhysicalChannel carrying the Uplink E-DCH absolute grant. E-AGCH is transmitted over one Frame (10 ms) orone sub-Frame (2 ms) depending on the UEs E-DCH TTI.

E-DCH Hybrid ARQ Indicator Channel (E-HICH)

The E-HICH carries a simple signature pattern representing an ACK or NACK. There are two types ofNAK: a “-1” NAK indicating that a serving Node-B failed to receive the transmission (critical), or a “0”NAK indicating that a non-serving Node-B failed to receive the transmission (informative). Transmis-sion is at SF128, and the signature is repeated for a whole E-DCH TTI (that is, either three or fifteentimes). The E-DCH Hybrid ARQ Indicator Channel (E-HICH) is a fixed rate (SF=128) dedicated Down-link Physical Channel carrying the Uplink E-DCH hybrid ARQ acknowledgement indicator. Function-ally it is the same as the E-RGCH channel.

In each cell, the E-RGCH and E-HICH assigned to a UE shall be configured with the same channeliza-tion code. In each cell, the F-DPCH, E-RGCH, E-HICH and E-AGCH assigned to a UE shall be config-ured with same scrambling code as the P-CPICH.

Common Downlink Physical Channels

These Downlink Physical Channels are defined in full in TS25.211 specification.

Common Pilot Channel (CPICH)

This Channel is used to enable Channel estimation and, along with the SCH, allows estimates forpower control. CPICH uses a predefined sequence with a fixed rate (30 kbps, SF=256). This allows theUE In case transmit diversity on any DL channel, the CPICH shall be transmitted from both antennasas defined in TS25.211.There are two types of Common Pilot Channels, the Primary (only one) and Sec-ondary CPICH (zero or more). The Primary is always transmitted over the whole cell using the primaryscrambling code and using Channelization Code zero (Cch,256,0). The Secondary CPICH can be trans-mitted over all or part of the cell, using any of the 16 scrambling codes and an arbitrary channelizationcode.

There are also Pilot bits in the Data Channels which are used for phase reference.

Primary Common Control Physical Channel (P-CCPCH)

There is only one Primary Common Control Physical Channel within a cell, and it is used to carry syn-chronization and broadcast information (BCH) for users. The Frame structure of the Primary CCPCHdiffers from the Downlink DPCH in that no TPC, TFCI and no Pilot bits are transmitted. The PrimaryCCPCH is not transmitted during the first 256 chips of each slot. Instead, Primary and Secondary SCHare transmitted during this period, the remainder being used for broadcast messages.

• The Primary CCPCH is a fixed rate (30 kbps, SF=256).

• P-CCPCH can be STTD encoded

• P-CCPCH is assigned the Channelization code one (Cch,256,1)

• P-CCPCH always uses the primary scrambling code

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Secondary Common Control Physical Channel (S-CCPCH)

The Secondary CCPCH is used to carry the FACH and PCH. SF=4 up to SF=256 are supported.

The number of pilots (can be zero), TFCI bits (can be zero) and the SF depends on the slot format. Notethat the FACH and PCH can be mapped to the same or to separate Secondary CCPCHs (but not in thesame Frame). The S-CCPCH supports open loop transmit diversity (STTD).

The core provides the following functions

• Pilot generation and insertion

• TFCI Insertion

• Each symbol type can have a separate power weighting

• STTD Encoding

• Power weightings can be updated on a slot-by-slot basis

• TFCI value can be updated on a Frame-by-Frame basis

• Timing synchronization

Table 21 shows the slot formats allowed for the Secondary CCPCH Channel.

Figure Top x-ref 32

Figure 32: Frame Structure for Downlink S-CCPCH

Table 21: Secondary CCPCH Fields

Slot Format

#i


Channel Symbol

Rate (ksps)

SFBits/

FrameBits/ Slot

Ndata1 Npilot NTFCI

0 30 15 256 300 20 20 0 0

1 30 15 256 300 20 12 8 0

2 30 15 256 300 20 18 0 2

3 30 15 256 300 20 10 8 2

4 60 30 128 600 40 40 0 0

5 60 30 128 600 40 32 8 0

6 60 30 128 600 40 38 0 2

DPDCH DPCCH DPDCH DPCCH

TFCI Data PilotN bitsTFCI N bitsdata1 N bitspilot

Tslot 2560 chips, 20 x 2 bits (k =0...6)k

Slot #0 Slot #4 Slot #i Slot #14

One radio frame: T - 10 ms fds630_34_061107

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Synchronization Channel (SCH)

The Synchronization Channel (SCH) is a Downlink signal used for cell search. It consists of two subchannels, the Primary and Secondary SCH, each transmitted during the first 256 chips of each slot.

The P-SCH is always the same. It is used by the UE to detect the primary code of the base station.

The S-SCH varies per slot and uses one of the 64 primary scrambling codes. It is used by the UE toFrame synchronize to the base station.

SCH supports TSTD and STTD encoding as defined in TS25.211.

The SCH channels are generated within the core on a per Sector basis. They are fully configurable bysoftware. The SCH gain and diversity can be updated on a Frame-by-Frame basis.

Acquisition Indicator Channel (AICH)

The AICH is the acknowledgement Channel for receipt of the RACH. It is generated outside of the core.It has a fixed rate (SF=256) and is transmitted during the first 4096 Chips of an access Slot (5120 Chips).It is a known sequence of 4096 chips (32 symbols) based on the RACH Preamble signature received.

If the signature received is not within the Access Service Class (ASC) for the corresponding PRACH noAICH is returned. Otherwise a positive acknowledgement (+1) or negative acknowledge is returned(-1).

• STTD encoding is supported.

• AICH always uses the primary scrambling code

• AICH can use any Channelization code

7 60 30 128 600 40 30 8 2

8 120 60 64 1200 80 72 0 8*

9 120 60 64 1200 80 64 8 8*

10 240 120 32 2400 160 152 0 8*

11 240 120 32 2400 160 144 8 8*

12 480 240 16 4800 320 312 0 8*

13 480 240 16 4800 320 296 16 8*

14 960 480 8 9600 640 632 0 8*

15 960 480 8 9600 640 616 16 8*

16 1920 960 4 19200 1280 1272 0 8*

17 1920 960 4 19200 1280 1256 16 8*

Note: If TFCI bits are not used, then DTX shall be used in TFCI field.

Table 21: Secondary CCPCH Fields (Continued)

Slot Format

#i


Channel Symbol

Rate (ksps)

SFBits/

FrameBits/ Slot

Ndata1 Npilot NTFCI

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The core supports AICH pre-combining which allows multiple AICHs with the same Channelizationand Scrambling Code to be pre-added prior to the core. This means that multiple AICH channels canuse the same hardware and thus less hardware resource is used.

Paging Indicator Channel (PICH)

The Paging Indicator Channel (PICH) is a fixed rate (SF=256) physical Channel used to carry the pag-ing indicators. The PICH is always associated with an S-CCPCH to which a PCH transport Channel ismapped. It is transmitted over the first 288 bits of a 10 ms Frame. The remaining 12 bits are reservedand nothing can be transmitted (DTX). This is described in full in the TS25.211 specification.


• PICH always uses the primary scrambling code.

• PICH can use any Channelization code.

Shared Control Channel (HS-SCCH)

The HS-SCCH is a fixed rate (60 kbps, SF=128) Downlink Physical Channel used to carry Downlink sig-nalling related to HS-DSCH transmission. There are a maximum of 15 HS-SCCH Channels correspond-ing to the 15 HS-PDSCH Channels in order to leave sufficient room for other required control and databearers.

• HS-SCCH is transmitted over one sub-Frame (2ms). This is formed from 3 Slots (7680 Chips).

• The associated HS-PDSCH Channel is transmitted 2 slots after the HS-SCCH.

• More than one HS-SCCH can be assigned to one UE. Up to 4 UEs can share the code resources within the same 2ms TTI. Primarily the code resources are shared in the time domain.

• Modulation is always QPSK (120 bits per sub-Frame).

High Speed Physical Downlink Shared Channel (HS-PDSCH)

The High Speed Physical Downlink Shared Channel (HS- PDSCH) is used to carry the High SpeedDownlink Shared Channel (HS-DSCH). It has an associated HS-SCCH Channel. The Spreading factor isfixed to 16.

• HS-PDSCH is transmitted over one sub-Frame (2 ms). This is formed from 3 Slots (7680 Chips).

• One sub-Frame is formed from 3 Slots (7680 Chips). The HS-PDSCH Channel is transmitted 2 slOts after the associated HS-SCCH.

• More than one HS-PDSCH can be assigned to one UE. Multiple UEs can share the code resources within the same 2 ms TTI.

• Modulation is QPSK (960 bits per sub-Frame) or QAM16 (1920 bits per sub-Frame)

• All relevant Layer 1 information is transmitted in the associated HS-SCCH. (e.g., CQI, H-ARQ, modulation scheme, transport block size, UE identity)

MBMS Indicator Channel (MICH)

The Multimedia Broadcast/Multicast Service (MBMS) Indicator Channel (MICH) is a fixed rate(SF=256) physical Channel used to carry the MBMS notification indicators. The MICH is always asso-ciated with an S-CCPCH to which a FACH transport Channel is mapped. It is transmitted over the first288 bits of a 10 ms Frame. The remaining 12 bits are reserved and nothing can be transmitted (DTX).This is described in full in the TS25.211 specification.


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• MICH always uses the primary scrambling code

• MICH can use any Channelization code

Channel Timing

The P-CCPCH, on which the cell SFN is transmitted, is used as timing reference for all the physicalchannels, directly for Downlink and indirectly for Uplink.

Figure 33 describes the Frame timing of the Downlink Physical Channels. For the AICH the access slottiming is included. Transmission timing for Uplink Physical Channels is given by the received timingof Downlink Physical Channels.

The following applies:

• SCH (primary and secondary), CPICH (primary and secondary), P-CCPCH, and PDSCH have identical Frame timings.

• The S-CCPCH timing may be different for different S-CCPCHs, but the offset from the P-CCPCH Frame timing is a multiple of 256 chips.

• The PICH timing is PICH = 7680 chips prior to its corresponding S-CCPCH Frame timing, i.e. the

Figure Top x-ref 33

Figure 33: Radio Frame Timing and Access Slot Timing of Downlink Physical Channels

k:th S-CCPCH

AICH access slots

Secondary SCH

Primary SCH

τS-CCPCH,k

10 ms

τ PICH

#0 #1 #2 #3 #14#13#12 #11 #10 #9#8#7#6#5#4

Radio frame with (SFN modulo 2) = 0 Radio frame with (SFN modulo 2) = 1

τ DPCH,n

P-CCPCH

Any CPICH

PICH for k:th S-CCPCH

Any PDSCH

n:th DPCH

10 ms

Subframe #0

HS-SCCH Subframes

Subframe # 1

Subframe#2

Subframe#3

Subframe#4

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timing of the S-CCPCH carrying the PCH transport Channel with the corresponding paging information, see also subclause 7.2.

• AICH access slots #0 starts the same time as P-CCPCH Frames with (SFN modulo 2) = 0.

• The relative timing of associated PDSCH and DPCH is described in subclause 7.5.

• The DPCH timing may be different for different DPCHs, but the offset from the P-CCPCH Frame timing is a multiple of 256 chips, i.e., DPCH, n = Tn ¥ 256 chip, Tn Œ {0, 1, …, 149}.

• The F-DPCH timing may be different for different F-DPCHs, but the offset from the P-CCPCH Frame timing is a multiple of 256 chips, i.e., F-DPCH, p = Tp ¥ 256 chip, Tp Œ {0, 1, …, 149}.

The start of HS-SCCH sub-Frame #0 is aligned with the start of the P-CCPCH Frames.

Support Xilinx provides technical support for this LogiCORE product when used as described in the productdocumentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented indevices that are not defined in the documentation, if customized beyond that allowed in the productdocumentation, or if changes are made to any section of the design labeled DO NOT MODIFY.

Ordering InformationThis Xilinx LogiCORE™ module is provided under the SignOnce IP Site License. A free evaluation ver-sion of the module is available.

Once purchased, the core may be downloaded from the Xilinx IP Center for use with the Xilinx COREGenerator software v9.2i and higher. The Xilinx CORE Generator software is bundled with the ISE™Foundation software at no additional charge.

Contact your local Xilinx sales representative for pricing and availability on Xilinx LogiCORE modulesand software. Information on additional Xilinx LogiCORE modules is available on the Xilinx IP Center.

Revision HistoryThe following table shows the revision history for this document.

Date Version Revision

08/08/07 1.0 Initial Xilinx release.

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