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NJU26226 -1- Ver.2011-12-26 Dolby Virtual Speaker / Dolby Headphone with Dolby Pro Logic IIx Decoder ! General Description NJU26226 expand stereo or 5.1 surround signal to 6.1 or 7.1 channel surround sound by Dolbyfi Pro Logicfi IIx technology. NJU26226 provides a highly realistic multi channel speaker surround sound listening environment from as few as headphone or two speakers using Dolbyfi Pro Logicfi IIx and Dolbyfi Headphone / Dolbyfi Virtual Speaker technology. NJU26226 is suitable for Gaming Headsets, digital TVs, stereo mini-components, PCs, and any audio/visual products. ! Features -Software # Dolby Pro Logic IIx (Max 7.1ch Output) # Dolby Virtual Speaker * # Dolby Headphone # Bass Management system * # Pink Noise Generator # Multi-channel signals input (Max 7.1ch Input) *: Dolby Virtual Speaker and Bass Management effective only up to 5.1 channels. -Hardware # 24bit Fixed-point Digital Signal Processing # Maximum Clock Frequency : 12.288MHz(Standard), built-in PLL Circuit # Digital Audio Interface : 4 Input ports / 4 Output ports # Digital Audio Format : I 2 S 24bit, left-justified, right-justified, BCK : 32fs/64fs # Master / Slave Mode - In Master mode, MCK : 256fs @fs=48kHz / 384fs @fs=32kHz # Microcomputer Interface - I 2 C Bus (Standard-mode/100kbps, Fast-mode/400kbps) - 4 -Wire Serial Bus (4-Wire: Clock, Enable, Input data, Output data) # Operating Voltage : V DD = V DDPLL = 1.8V : V DDIO = 3.3V # Input Terminal : 5.0V Input tolerant # Package : SSOP44 (Pb-Free) * The detail hardware specification of the NJU26226 is described in the NJU26200 Series Hardware Data Sheet. Package NJU26226V

Dolby Virtual Speaker / Dolby Headphone with Dolby Pro ... · Dolby Virtual Speaker / Dolby Headphone with Dolby Pro Logic IIx Decoder ... Dolby Virtual Speaker / Bass Management

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  • NJU26226

    - 1 -Ver.2011-12-26

    Dolby Virtual Speaker / Dolby Headphone

    with Dolby Pro Logic IIx Decoder ! General Description NJU26226 expand stereo or 5.1 surround signal to 6.1 or 7.1 channel surround sound by Dolby Pro Logic IIx technology. NJU26226 provides a highly realistic multi channel speaker surround sound listening environment from as few as headphone or two speakers using Dolby Pro Logic IIx and Dolby Headphone / Dolby Virtual Speaker technology. NJU26226 is suitable for Gaming Headsets, digital TVs, stereo mini-components, PCs, and any audio/visual products. ! Features -Software # Dolby Pro Logic IIx (Max 7.1ch Output) # Dolby Virtual Speaker * # Dolby Headphone # Bass Management system * # Pink Noise Generator # Multi-channel signals input (Max 7.1ch Input) *: Dolby Virtual Speaker and Bass Management effective only up to 5.1 channels.

    -Hardware # 24bit Fixed-point Digital Signal Processing # Maximum Clock Frequency : 12.288MHz(Standard), built-in PLL Circuit # Digital Audio Interface : 4 Input ports / 4 Output ports # Digital Audio Format : I2S 24bit, left-justified, right-justified, BCK : 32fs/64fs # Master / Slave Mode

    - In Master mode, MCK : 256fs @fs=48kHz / 384fs @fs=32kHz # Microcomputer Interface

    - I2C Bus (Standard-mode/100kbps, Fast-mode/400kbps) - 4 -Wire Serial Bus (4-Wire: Clock, Enable, Input data, Output data)

    # Operating Voltage : VDD = VDDPLL = 1.8V : VDDIO = 3.3V

    # Input Terminal : 5.0V Input tolerant # Package : SSOP44 (Pb-Free)

    * The detail hardware specification of the NJU26226 is described in the NJU26200 Series Hardware Data Sheet.

    Package

    NJU26226V

  • NJU26226

    - 2 - Ver.2011-12-26

    ! Block Diagram

    TIMINGGENERATOR

    / PLL

    PROGRAMCONTROL

    ALU

    24-BIT x 24-BITMULTIPLIER

    ADDRESS GENERATION UNIT

    FIRMWAREROM

    DATARAM

    SERIALHOST

    INTERFACE

    General I/OINTERFACE

    SDO0

    SDO3

    BCKI

    SCL/SCK

    SDA/SDOUT

    AD1/SDIN AD2/SSb

    CLK

    CLKOUT

    RESETb

    24bit Fixed-point DSP Core

    SDO1

    LRI

    MCK

    BCKO

    LRO

    NJU26226

    SDO2

    WDC

    SEL

    MUTEb

    PROC

    SERIAL AUDIOINTERFACE SDI0

    SDI3

    SDI1

    SDI2

    Fig. 1 NJU26226 Hardware Block Diagram

    ! Function Block Diagram

    NJU26226 Features Overview

    Pink NoiseGenerator

    L/R

    C/SW

    Ls/Rs

    Lb/Rb

    L/R

    C/SW

    Ls/Rs

    Lb/Rb

    Pro Logic IIx

    Dolby VirtualSpeaker (5.1ch)

    /D

    olby Headphone (7.1ch)

    Output Trim

    mer

    (Master &

    L/R/C

    /Ls/Rs/Lb/R

    b/Sw)

    Dolby Virtual Speaker / Bass Management are only effective for 5.1ch signal

    Input Trimm

    er

    Bass M

    anagement

    Fig. 2.1 NJU26226 Block Diagram (Outline)

  • NJU26226

    - 3 -Ver.2011-12-26

    SDI2

    SDI3

    MUTE

    SDI0

    SDI1

    L/R

    SDI2

    SDI3

    MUTE

    SDI0

    SDI1

    C/SW

    SDI2

    SDI3

    MUTE

    SDI0

    SDI1

    Ls/Rs

    SDI2

    SDI3

    MUTE

    SDI0

    SDI1

    Lb/Rb

    Ls/Rs

    Lb/Rb

    MUTE

    L/R

    C/SW

    SDO0

    Ls/Rs

    Lb/Rb

    MUTE

    L/R

    C/SW

    SDO1

    Ls/Rs

    Lb/Rb

    MUTE

    L/R

    C/SW

    SDO2

    Ls/Rs

    Lb/Rb

    MUTE

    L/R

    C/SW

    SDO3

    Input signal select Output signal select

    Fig. 2.2 NJU26226 Block Diagram (Input Select block, Output Select block)

  • NJU26226

    - 4 - Ver.2011-12-26

    ProLogic IIx

    Input Trimm

    er

    Lb

    Sw

    Rb

    Ls

    Rs

    L

    R

    C

    Dolby H

    eadphone

    + LPF +

    ++

    L out

    R out

    Ls/Rs delay

    input mode = 2.1chDolbyHeadphone enable

    Lb/Rb delay

    Sw out

    PLIIx SW

    LFE Gen. SW

    SW Downmix SW

    Fig. 2.3 NJU26226 Block Diagram (detail)

    ProLogic IIx

    Input Trimm

    er

    Lb

    Sw

    Rb

    Ls

    Rs

    L

    R

    C

    Dolby H

    eadphone

    + LPF +

    ++

    L out

    R out

    input mode = 5.1chDolbyHeadphone enable

    Ls/Rs delay

    Lb/Rb delay

    Sw out

    L/R/C

    delay

    PLIIx SW

    LFE Gen. SW

    SW Downmix SW

    Fig. 2.4 NJU26226 Block Diagram (detail)

    Ls/Rs delay

    Lb/Rb delay

    Input Trimm

    er

    Lb

    Sw

    Rb

    Ls

    Rs

    L

    R

    C

    Dolby H

    eadphone

    + LPF +

    ++

    L out

    R out

    input mode = 7.1chDolbyHeadphone enable

    Sw out

    LFE Gen. SW

    SW Downmix SW

    Fig. 2.5 NJU26226 Block Diagram (detail)

  • NJU26226

    - 5 -Ver.2011-12-26

    ProLogic IIx

    Input Trimm

    er

    Lb

    Sw

    Rb

    Ls

    Rs

    L

    R

    C

    + LPF +

    input mode = 2.1chDolby Headphone / Dolby Virtual Speaker disable

    Lb out

    Sw out

    Rb out

    Ls out

    Rs out

    L out

    R out

    C out

    Ls/Rs delay

    Lb/Rb delay

    C delay

    PLIIx SW

    LFE Gen. SW

    BM SW

    Bass M

    anagement

    ProLogic IIxTwo- To

    Four ChannelExpander

    PLIIx SW

    Control Voltage

    Fig. 2.6 NJU26226 Block Diagram (detail)

    Lb

    Sw

    Rb

    Ls

    Rs

    L

    R

    C

    + LPF +

    input mode = 5.1chDolby Headphone / Dolby Virtual Speaker disable

    Lb out

    Sw out

    Rb out

    Ls out

    Rs out

    L out

    R out

    C out

    Ls/Rs delay

    Lb/Rb delay

    C delay

    PLIIx SW

    LFE Gen. SW

    BM SW

    ProLogic IIx

    L/R/C

    delay

    Bass M

    anagement

    Input Trimm

    er

    Fig. 2.7 NJU26226 Block Diagram (detail) Input Trim

    mer

    Lb

    Sw

    Rb

    Ls

    Rs

    L

    R

    C

    + LPF +

    input mode = 7.1chDolby Headphone / Dolby Virtual Speaker disable

    Bass

    Managem

    ent

    Lb out

    Sw out

    Rb out

    Ls out

    Rs out

    L out

    R out

    C out

    Ls/Rs delay

    Lb/Rb delay

    C delay

    LFE Gen. SW

    BM SW

    Fig. 2.8 NJU26226 Block Diagram (detail)

  • NJU26226

    - 6 - Ver.2011-12-26

    Ls/Rs delay

    Sw out

    Ls out

    Rs out

    L out

    R out

    C out

    input mode = 2.1chDolby Virtual Speaker enable, 2speaker layout / 3speaker layout

    ProLogic II

    Input Trimm

    er

    Sw

    Ls

    Rs

    L

    R

    C

    Dolby

    Virtual Speaker

    + LPF +

    ++

    Ls/Rs delay

    Bass M

    anagement

    PLII SW

    LFE Gen. SW

    SW Downmix SW

    BM SW

    Fig. 2.9 NJU26226 Block Diagram (detail)

    Ls/Rs delay

    Sw out

    Ls out

    Rs out

    L out

    R out

    C out

    input mode = 2.1chDolby Virtual Speaker enable, 4speaker layout / 5speaker layout

    ProLogic II

    Input Trimm

    er

    Sw

    Ls

    Rs

    L

    R

    C

    Dolby

    Virtual Speaker

    + LPF +

    ++

    Bass M

    anagement

    Ls/Rs delay

    PLII SW

    LFE Gen. SW

    SW Downmix SW

    BM SW

    Fig. 2.10 NJU26226 Block Diagram (detail)

    Sw out

    Ls out

    Rs out

    L out

    R out

    C out

    input mode = 5.1chDolby Virtual Speaker enable

    Input Trimm

    er

    Sw

    Ls

    Rs

    L

    R

    C

    Dolby

    Virtual Speaker

    + LPF +

    ++

    Bass M

    anagement

    Ls/Rs delay

    LFE Gen. SW

    SW Downmix SW

    BM SW

    Fig. 2.11 NJU26226 Block Diagram (detail)

  • NJU26226

    - 7 -Ver.2011-12-26

    Bass M

    anagement

    HPF / Through

    (Depend on

    Ls/Rs speaker

    size setting)

    L

    R

    C

    SW

    Ls

    Rs

    Lb

    Rb

    Bass ManagementLFE Trim

    Bass M

    anagement M

    aster Volume

    L

    R

    C

    SW

    Ls

    Rs

    Lb

    Rb

    Bass ManagementL Trim

    Bass ManagementR Trim

    Bass ManagementC Trim

    Bass ManagementSW Trim

    Bass ManagementLs Trim

    Bass ManagementRs Trim

    Bass ManagementLs Trim

    Bass ManagementRs Trim

    BASS MANAGEMENT BLOCK

    Fig. 2.12 NJU26226 Block Diagram (Bass Management block)

    L

    R

    C

    SW

    Ls

    Rs

    Lb

    Rb

    PINK NOISE GENERATOR BLOCK

    L

    R

    C

    SW

    Ls

    Rs

    Lb

    Rb

    PNG enable SW

    Pink NoiseGenerator

    Fig. 2.13 NJU26226 Block Diagram (Pink Noise Generator block)

  • NJU26226

    - 8 - Ver.2011-12-26

    L

    R

    C

    SW

    Ls

    Rs

    Lb

    Rb

    DVS/DH L/R input Trimmer

    DVS/DH Center input Trimmer

    DVS/DH LS/RS input Trimmer

    DVS/DH LB/RB input Trimmer

    DVS/DH LFE input Trimmer

    DVS/DH stereo bypass downmix trimmer (front)

    DVS/DH stereo bypass downmix trimmer (center)

    DVS/DH stereo bypass downmix trimmer (surround)

    DVS/DH stereo bypass downmix trimmer(back surround)

    DVS/DH stereo bypass downmix trimmer (lfe)

    Dolby H

    eadphoneLt/R

    t Dow

    nmix

    Lo/Ro D

    ownm

    ixB

    ypass

    DOLBY HEADPHONE BLOCK DVS/DH output mode

    L

    R

    C

    SW

    Ls

    Rs

    Lb

    Rb

    -6dB

    Fig. 2.14 NJU26226 Block Diagram (Dolby Headphone block)

    L

    R

    C

    SW

    Ls

    Rs

    Lb

    Rb

    DVS/DH L/R input Trimmer

    DVS/DH Center input Trimmer

    DVS/DH LS/RS input Trimmer

    DVS/DH LFE input Trimmer

    DVS/DH stereo bypass downmix trimmer (front)

    DVS/DH stereo bypass downmix trimmer (center)

    DVS/DH stereo bypass downmix trimmer (surround)

    DVS/DH stereo bypass downmix trimmer(back surround)

    DVS/DH stereo bypass downmix trimmer (lfe)

    Lt/Rt D

    ownm

    ixLo/R

    o Dow

    nmix

    Bypass

    DVS/DH output mode

    L

    R

    C

    SW

    Ls

    Rs

    Lb

    Rb

    Dolby

    Virtual Speaker

    DOLBY VIRTUAL SPEAKER BLOCK

    -6dB

    Fig. 2.15 NJU26226 Block Diagram Block Diagram (Dolby Virtual Speaker block)

  • NJU26226

    - 9 -Ver.2011-12-26

    ! Pin Configuration

    Fig. 3 NJU26226 Pin Configuration

    NJU26226

    SSOP44

    44 43 42 41 40 39 38 37

    1 2 3 4 5 6 7 8 9

    10 11 12

    VDD VSS

    VSSIO VDDIO SDO0 SDO1 SDO2 SDO3

    SDI3 SDI2 SDI1 SDI0 LRI

    VDDIO BCKI VSS VDD

    TEST MUTEb WDC

    13 14 15 16

    PROC VSSIO VDDIO SEL

    36 35 34 33

    LRO BCKO MCK

    VDDIO

    17 18 19 20

    VDDPLL VSSPLL

    VSS VDD

    21 22

    CLKOUT CLK

    32 31 30 29

    SDA/SDOUT

    SCL/SCK AD2/SSb AD1/SDIN

    28 27 26 25

    TEST TEST TEST

    RESETb 24 23

    VDDIO VSSIO

  • NJU26226

    - 10 - Ver.2011-12-26

    ! Pin Description Table 1 Pin Description

    Pin No. Symbol I/O Function 1 SDI3 I Audio Data Input ch.3 2 SDI2 I Audio Data Input ch.2 3 SDI1 I Audio Data Input ch.1 4 SDI0 I Audio Data Input ch.0 5 LRI I LR Clock Input 6 VDDIO - I/O Power Supply +3.3V 7 BCKI I Bit Clock Input 8 VSS - DSP Core Power Supply GND 9 VDD - DSP Core Power Supply +1.8V

    10 TEST * I for test connect with VSSIO through 3.3kohm resistance. 11 MUTEb * I Master Volume Status after reset 1: 0dB, 0: Mute 12 WDC * OD Watchdog Clock output pin (Open drain output)

    13 PROC * I Signal Processing after reset 1: Normal Processing, 0: Waiting for a Command without Processing 14 VSSIO - I/O Power Supply GND 15 VDDIO - I/O Power Supply +3.3V 16 SEL I Host Interface Selection 1: Serial Interface, 0: I2C bus 17 VDDPLL - PLL Power Supply +1.8V 18 VSSPLL - PLL Power Supply GND 19 VSS - DSP Core Power Supply GND 20 VDD - DSP Core Power Supply +1.8V 21 CLKOUT O OSC Clock Output 22 CLK I OSC Clock Input (12.288MHz) 23 VSSIO - I/O Power Supply GND 24 VDDIO - I/O Power Supply +3.3V 25 RESETb I Reset (RESETb=0: DSP Reset) 26 TEST I for test (connect to VDDIO) 27 TEST I for test (connect to VSSIO) 28 TEST I for test (connect to VSSIO) 29 AD1/SDIN I I2C Address (I2C mode) / Serial In (4-wire serial mode) 30 AD2/SSb I I2C Address (I2C mode) / Serial enable (4-wire serial mode) 31 SCL/SCK I I2C SCL (I2C mode) / Serial clock (4-wire serial mode) 32 SDA/SDOUT I/O I2C SDA (I2C mode) / Serial Out (4-wire serial mode) 33 VDDIO - I/O Power Supply +3.3V 34 MCK O A/D, D/A clock output (buffer output of a CLK pin) 35 BCKO O Bit Clock Output 36 LRO O LR Clock Output 37 SDO3 O Audio Data Output ch.3 38 SDO2 O Audio Data Output ch.2 39 SDO1 O Audio Data Output ch.1 40 SDO0 O Audio Data Output ch.0 41 VDDIO - I/O Power Supply +3.3V 42 VSSIO - I/O Power Supply GND 43 VSS - DSP Core Power Supply GND 44 VDD - DSP Core Power Supply +1.8V

    I : Input O : Output OD : Open Drain Output I/O : Bi-directional

    Note: Pins symbol with * : Connect with VDDIO or VSSIO through 3.3k resistance

  • NJU26226

    - 11 -Ver.2011-12-26

    ! Audio Interface The NJU26226 audio interface provides industry serial data formats of I2S, MSB-first Left-justified or MSB-first Right-justified. The NJU26226 audio interface provides four data inputs, SDI0, SDI1, SDI2 and SDI3, and four data outputs, SDO0, SDO1, SDO2 and SDO3, as shown in table 2 and 3.

    Table 2 Serial Audio Input Pin Pin No. Symbol Description

    4 SDI0 3 SDI1 4 SDI2 1 SDI3

    The input signal to L/R, C/Sw, Ls/Rs and Lb/Rb can be selected from SDI0, SDI1, SDI2, and

    SDI3 (refer to Fig 2.2).

    Table 3 Serial Audio Output Pin Pin No. Symbol Description

    40 SDO0 L/R, C/Sw, Ls/Rs Lb/Rb, or Mute can be selected (refer to Fig 2.2). 39 SDO1 L/R, C/Sw, Ls/Rs Lb/Rb, or Mute can be selected (refer to Fig 2.2). 38 SDO2 L/R, C/Sw, Ls/Rs Lb/Rb, or Mute can be selected (refer to Fig 2.2). 37 SDO3 L/R, C/Sw, Ls/Rs Lb/Rb, or Mute can be selected (refer to Fig 2.2).

    Note: L/R : Front channel C/Sw : Center channel and Sub woofer Ls/Rs: Surround channel Lb/Rb: Surround back channel

    ! Host Interface The NJU26226 can be controlled via Serial Host Interface (SHI) using either of two serial bus formats : I2C bus or 4-Wire serial bus. Data transfers are in 8 bits packets (1 byte) when using either format. The SHI operates only in a SLAVE fashion. A host controller connected to the interface always drives the clock (SCL / SCK) line and initiates data transfers, regardless of the chosen communication protocol. The detail I2C bus and 4-Wire Serial bus information are described in the NJU26200 Series Hardware Data Sheet.

    Table 4 Serial Host Interface Pin Descriptions Pin No. Symbol Setting Host Interface

    Low I2C Bus Interface 16 SEL High 4-Wire Serial Interface

    Table 5 Serial Host Interface Pin Description Pin No. Symbol

    (I2C /Serial) I2C bus Interface 4-Wire Serial Interface

    29 AD1/SDIN I2C Address Select Bit1 Serial data input 30 AD2/SSb I2C Address Select Bit2 Slave select 31 SCL/SCK Serial Clock Serial Clock 32 SDA/SDOUT Serial Data Input/Output

    (Open Drain output) Serial data output

    (CMOS Output) Note: When 4-Wire Serial bus is selected, The SDA/SDOUT pin is CMOS output. The SDOUT pin does not require a

    pull-up resistance. When I2C Bus is selected, this pin is a bi-directional Open Drain output. This pin, which is assigned for I2C Bus, requires a pull-up resistance. The SDA/SDOUT pin isnt 5.0V Input tolerant. Please note the voltage level (Max voltage is VDDIO).

  • NJU26226

    - 12 - Ver.2011-12-26

    ! I2C Bus

    When the NJU26226 is configured for I2C bus communication in SEL=Low, the serial host interface transfers data on the SDA pin and clocks data on the SCL pin. SDA is an open drain pin requiring a pull-up resistance. Pins AD1 and AD2 are used to configure the seven-bit SLAVE address of the serial host interface. (Table 6)

    Table 6 I2C-Bus Interface Slave address

    * SLAVE address is 0 when AD1/2 is Low. SLAVE address is 1 when AD1/2 is High.

    Note: The serial host interface supports Standard-Mode (100kbps) and Fast-Mode (400kbps) I2C bus data transfer. Moreover, after sending S ("START" condition), Sr (repeated "START" condition) is not received but it becomes the waiting for the P ("STOP" condition). Therefore, please be sure to send P ("STOP" condition).

    ! 4-Wire Serial Interface

    The serial host interface can be configured for 4-Wire Serial bus communication by setting SEL1=High during the Reset Sequence initialization. SHI bus communication is full-duplex; a write byte is shifted into the SDIN pin at the same time that a read byte is shifted out of the SDOUT pin. Data transfers are MSB first and are enabled by setting SSb = Low. Data is clocked into SDIN on rising transitions of SCK. Data is latched at SDOUT on falling transitions of SCK except for the first byte(MSB) which is latched on the falling transitions of SSb. The SDOUT pin is always CMOS output. This pin does not require a pull-up resistance.

    Fig. 4 4-Wire Serial Interface Timing

    Note : When the data-clock is less than 8 clocks, the input data is shifted to LSB side and is sent to the DSP core at the transition of SSb=High.

    When the data-clock is more than 8 clocks, the last 8 bit data becomes valid. After sending LSB data, SDOUT transmits the MSB data which is received via SDIN until SSb becomes High.

    bit7 bit6 bit5 bit4 bit3

    AD2 bit2

    AD1 bit1

    R/W bit0

    0 0 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 1 1 0 0 0 1 1 1 1 1

    R/W

    Start bit R/W bit ACK

    Slave Address ( 7bit )

    SDIN

    SDOUT

    SCK

    SSb

    bit5 bit1bit7 bit0bit6

    bit1bit7 bit0bit6 bit5 unstable unstable MSB LSB

  • NJU26226

    - 13 -Ver.2011-12-26

    ! Pin setting The NJU26226 operates default command setting after resetting the NJU26226. In addition, the NJU26226 restricts operation at power on by setting PROC pin and MUTEb pin (Table 7). These pins are input pin. However, these pins operate as bi-directional pins. Connect with VDDIO or VSSIO through 3.3k resistance.

    Table 7 Pin setting Pin No. Symbol Setting Function

    High The NJU26226 operates default setting after reset. 13

    PROC Low The NJU26226 does not operate after reset. Sending start

    command is required for starting operation. High Master volume is set 0dB after reset. 11 MUTEb Low Master volume is set mute after reset.

    ! WatchDog Clock

    The NJU26226 outputs clock pulse through WDC (Pin No.8) during normal operation. The WDC clock is useful to check the status of the NJU26226 operation. For example, a microcomputer monitors the WDC clock and checks the status of the NJU26226. When the WDC clock pulse is lost or not normal clock cycle, the NJU26226 does not operate correctly. Then reset the NJU26226 and set up the NJU26226 again. The WDC clock is able to be variable for 10ms to 640ms by command. Default setting of WDC clock is 200ms. The WDC pin is open drain output. The WDC pin setting (Table 8)

    Table 8 WDC pin setting

    Note: The cycle of WDC output is rough. Because WDC output inserts in the process of sound processing. In slave mode, when there is no input of BCKI/LRI, the WDC pin cant output. It is required to set up a sampling rate correctly.

    Pin No. Symbol Setting WDC pin is used. Connect with VDDIO through 3.3k resistance

    12 WDC WDC pin is not used. Connect with VSSIO through 3.3k resistance.

    Do not open WDC pin.

  • NJU26226

    - 14 - Ver.2011-12-26

    ! Firmware Command Table

    Table 9 NJU26226 Command No. Command 1 SET_TASK_CMD 2 PRO2MODE_CMD 3 PRO2CDCFG_CMD 4 PRO2FLAGS_CMD 5 DVS_DH_CMD 6 BM_CONFIG_CMD 7 SAMPLERATE_CMD 8 PNG_MODE_CMD 9 DELAY_CMD 10 GAIN_CMD 11 SYSTEM_STATE_CMD 12 WATCHDOG_CMD 13 SMOOTH_CMD 14 INPUT_SEL_CMD 15 OUTPUT_SEL_CMD 16 REINIT_CMD 17 SOFTWARE_RESET_CMD 18 START_CMD 19 NOP_CMD

    Notes : In respect to detail command information, request New Japan Radio Co., Ltd. and permission of a licenser (Dolby) is required.

    License Information The Word DOLBY, Pro Logic and the double D mark are trademarks of Dolby Laboratories. The NJU26226 can only be delivered to licensees of Dolby Laboratories. Please refer to the licensing application manual issued by Dolby Laboratories.

    [CAUTION] The specifications on this databook are only

    given for information , without any guarantee as regards either mistakes or omissions. The application circuits in this databook are described only to show representative usages of the product and not intended for the guarantee or permission of any right including the industrial rights.