DLD Paper _2_ Solution

8/3/2019 DLD Paper _2_ Solution

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Digital Logic design

Solution of GTU Remedial Paper (DLD)Solution of GTU Remedial Paper (DLD)Solution of GTU Remedial Paper (DLD)Solution of GTU Remedial Paper (DLD)Q.1 (a) Define: Digital System.

Convert following Hexadecimal Number to Decimal :B28, FFF, F28Convert following Octal Number to Hexadecimal and Binary:

414, 574, 725.25

Digital System:- A Digital system in which the voltage level issue the finite level

of Digital system.

Conversion : - Hexa to Dec.

(B28)16 = 11*(16^2) + 2*(16^1) + 8*(16^0)

= 11*32+2*16+8*1

= 352+32+8

= (392)10

(FFF)16 = 15*32+15*16+15*1

= (735)10

(F28)16 = 15*32+2*16+8*1

= (520)10

Conversion : - octal to hexa & binary

(414)8= (100001100)2

= (0001 0000 1100)

=(10C)16

(574)8= (101111100)2

= (0001 0111 1100)

= (17C)16

(725.25)8= (111010101.010101)2

= (0001 1101 0101.0101 0100)

= (1D5.54)16


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(b) Define : Integrated Circuit and briefly explain SSI, MSI, LSI and VLSI :-


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Q.2 (a) Draw the logic symbol and construct the truth table for each of thefollowing gates.[1] Two input NAND gate [2] Two input OR gate[3] Two input EX-NOR gate [4] NOT gate

1] Two input NAND gate :

2] Two input OR gate :

3] Two input EX-NOR gate :

4] NOT gate :

(b) Give classification of Logic Families and compare CMOS and TTL


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families:

OR


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(b) Explain SOP and POS expression using suitable examples

SOP Form:

Algorithm: Minimum Sum of Products Expression from a K-Map

Step 1: Choose an element of ON-set not already covered by an implicantStep 2: Find "maximal" groupings of 1's and X's adjacent to that element.

Remember to consider top/bottom row, left/right column, and

corner adjacencies. This forms prime implicants (always a power

of 2 number of elements).

Repeat Steps 1 and 2 to find all prime implicants

Step 3: Revisit the 1's elements in the K-map. If covered by single prime

implicant, it is essential, and participates in final cover. The 1's it

covers do not need to be revisited

Step 4: If there remain 1's not covered by essential prime implicants, then

select the smallest number of prime implicants that cover the

remaining 1's

Converting General Expression to SOP Form

apply distributivity

A(B + CD) = AB + ACD

Converting Product Terms to Standard SOP

multiply each term by the sum of a missing variable and its

complement and apply distributivity

AB + ACD = AB(C + C)(D + D) + A(B + B)CD

= ABCD + ABCD + ABCD + ABCD +

ABCD + ABCD

POS Form:

Converting Sum Terms to Standard POS

add to each sum term the product of a missing variable and its

complement and apply distributivity

(A+B+C)(B+C+D)(A+B+C+D)

= (A+B+C+DD)(AA+B+C+D)(A+B+C+D)

= (A+B+C+D)(A+B+C+D)(A+B+C+D)(A+B+C+D)(A+B+C+D)

Q.3 (a) Design a 4 bit binary to BCD code converter.


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Decimal Digit Binary of Decimal Digit 8 4 2 1 2 4 2 1 5 2 1 1 6 4 -2 -3 8 4 -2 -1 5 4 2 1 XS-

0 0 0 0 0 0 0 0 11

1 1 1 1 1 101 111 1 100

2 10 10 10 11 10 110 10 101

3 11 11 11 101 1001 101 11 110

4 100 100 100 111 100 100 100 1115 101 101 1011 1000 1011 1011 1000 100

6 110 110 1100 1010 110 1010 1001 100

7 111 111 1101 1100 1101 1001 1010 101

8 1000 1000 1110 1110 1010 1000 1011 101

9 1001 1001 1111 1111 1111 1111 1100 110

(b) Design a full adder circuit using decoder and multiplexer.

Q.3 (a) Write short note on EEPROM, EPROM and PROMAns-

(b) Define: [1] Comparator [2] Encoder [3] Decoder[4] Multiplexer [5] De-multiplexer [6] Flip Flop [7] PLA

Ans:-[1]comparator:-[2]encoder:-an encoder is a digital device that receive digits,alphabets,specialsymbol

And converts them to their respective binary code.[3]decoder:- a decoder converts binary coded information to unique o\p such as

Decimal,octal etc.[4]multiplexer:- a multiplexer is a logic ckt. That accepts several data i\p and allowsonly

One of them to get through the o\p.[5]de-multiplexer:- a de-multiplexer is a digital ckt. That takes only one i\p and gives

several o\p.

[6]flip flop:-[7]pla:-

Q.4 (a) Draw and explain the working of following flip-flops[1] Clocked RS [2] JK


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Ans:-

[1]

Fig. of RS flip flop


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[2] jk flip flop


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Q.4 (b) Convert SR flip-flop into JK flip-flop

Ans:-

OR

Q.4 (a) Design sequential counter as shown in the state diagram using JK flip-flops

(b) State and explain the features of register transfer logic


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Ans:-


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Q.5 (a) Explain the working of 4 bit a synchronous counter

Ans:-


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(b) Explain memory unit

Ans:-


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OR

Q.5 (a) Explain the design of Arithmetic Logic Unit

Ans:-

(b) Explain Control Logic Design

Ans:-

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DLD Paper _2_ Solution