Embed Size (px)
DESCRIPTION
Distributed Computation: Circuit Simulation. CK Cheng UC San Diego [email protected]. Trends of Scaling (Moore’s Law). Expansion of applications: ai , bioinf , graphics, vision Explosion of communication: internet Distributed system: exascale computation - PowerPoint PPT Presentation
Citation preview
Trends of Scaling (Moore’s Law)• Expansion of applications: ai, bioinf, graphics,
vision• Explosion of communication: internet• Distributed system: exascale computation• Power constrained designs: low power• Interconnect dominance: VLSI• Nano-devices with variations: fault tolerant
design, design for manufacturability
2
Technology
System
Application
Research Outline
• Parallel SPICE– Cluster Machines– Netlist Partitioning– Whole Chip Analysis– SPICE Accuracy
• Power Ground Analysis– Worst Power Load Exploration– 3D Power Distribution– Voltage Drop and Electronic Migration Analysis– RLC Optimization
3
Circuit Simulation: Motivation Technology Scaling
Challenges for Circuit Simulation Complexity Signal Integrity: crosstalk, voltage drop, coupling noise etc. High clock frequency: Inductance Effect Smaller transistors: Higher nonlinearity
5
Simulation: Goal• Analyze whole chip with 100x memory
capacity, 100x speed up, 100x efficiency for designers
• Set standard of input/output for parallel processing
• Allow cluster machines or cloud computing for the acceleration
• Demonstrate the results via power ground analysis and tera Hertz circuitry
Parallel Device Loading (continued)
Original Circuit
Nonlinear Sub-circuit
Interface Linear-Nonlinear Iteration
linear Sub-circuit
…
…
Equivalent Ckt
Equivalent Ckt
PU: Processing Unit
linear Sub-circuit
Equivalent Ckt
linear Sub-circuit
Equivalent Ckt
PUK+j1
Parallel AMG
PUK
Parallel AMG
PUK+jm
Parallel AMG
PU1
Direct Solver (KLU)
Nonlinear Sub-circuit
Equivalent Ckt
PU2
Direct Solver (KLU)
Nonlinear Sub-circuit
Equivalent Ckt
PUk-1
Direct Solver (KLU)
Device Loading Device Loading Device Loading
7
Action Items• Input/Output Parsing and
Screening– Parallel Input
• Parallel input format• Parallel parsing
– Netlist Transformation– Parallel Output
• Output parsing• Graphic display
• Device Evaluation– Transistor Model
• Matrix Solver• Sensitivity Calculation• Adaptive Time Step Control
• Parallelization• Overall Framework
– Implement in C/C++ – Which math library?– Sparse matrix library? – Parallel Implementation
• Applications– Power Ground Network
Analysis– Tera Hertz Circuit
Simulation
Power Grid Analysis
• Package: – Voltage regulator– distributed RLC
model• Silicon Chips:
– Bumps– Metal wires
Power Network Analysis: Motivation
9
Year gte Lnm
freqGHz
VddVolt
PW
I=P/VAmp
Z=V/IOhm
2011 24 6.3 0.93 90 96 0.009642015 17 8.5 0.81 123 152 0.005332020 10.7 12.4 0.68 142 208 0.003262024 7.4 16.6 0.60 170 284 0.00211
ITRS Roadmap: MPU
Responses in Frequency DomainT1
T20
2040
6080
100120
140
0
10
20
30
40
50
600
0.5
1
1.5
2
2.5
3
M3 directionM1 direction
Vol
tage
(V
)
020
4060
80100
120140
0
10
20
30
40
50
600
0.2
0.4
0.6
0.8
1
1.2
1.4
M3 directionM1 direction
Vol
tage
(V
)
020
4060
80100
120140
0
10
20
30
40
50
600
0.05
0.1
0.15
0.2
0.25
M3 directionM1 direction
Vol
tage
(V
)
020
4060
80100
120140
0
10
20
30
40
50
600.0165
0.017
0.0175
0.018
0.0185
0.019
0.0195
0.02
0.0205
0.021
M3 directionM1 direction
Vol
tage
(V
)
020
4060
80100
120140
0
10
20
30
40
50
600.0165
0.017
0.0175
0.018
0.0185
0.019
0.0195
0.02
0.0205
0.021
M3 directionM1 direction
Vol
tage
(V
)
020
4060
80100
120140
0
10
20
30
40
50
600.0165
0.017
0.0175
0.018
0.0185
0.019
0.0195
0.02
0.0205
0.021
M3 directionM1 direction
Vol
tage
(V
)
γ=0 γ=0.05 γ=1
Time Domain Responses: Rogue Waves
Conclusion
• Spice Simulation for Whole System– Memory Capacity– CPU Time– User Interface
• Power Distribution Analysis– Huge Netlist– Complex Electrical Behavior– Stringent Constraints
12
