Digital Pll Cicc Tutorial Perrott

Tutorial on Digital Phase-Locked LoopsCICC 2009Michael H. Perrott September 2009

Copyright 2009 by Michael H. Perrott

Why Are Digital Phase-Locked Loops Interesting?Performance is important

- Phase noise can limit wireless transceiver performance - Jitter can be a problem for digital processors - Analog building blocks on a mostly digital chip pose design and verification challenges - The cost of implementation is becoming too high Can digital phase-locked loops offer excellent performance with a lower cost of implementation?

The standard analog PLL implementation is problematic in many applications

M.H. Perrott

2

Just Enough PLL Background

What is a Phase-Locked Loop (PLL)?ref(t) out(t) e(t) v(t) ref(t) e(t) ref(t) out(t) e(t) v(t) out(t)

Phase Detect

v(t) Analog Loop Filter VCO

de Bellescize Onde Electr, 1932

VCO efficiently provides oscillating waveform with variable frequency PLL synchronizes VCO frequency to input reference frequency through feedback

- Key block is phase detector

Realized as digital gates that create pulsed signalsM.H. Perrott 4

Integer-N Frequency Synthesizersref(t) div(t) e(t) v(t) Fout = N Fref ref(t) Phase Detect e(t) v(t) Analog Loop Filter VCO div(t) Divider N out(t)

Sepe and Johnston US Patent (1968)

Use digital counter structure to divide VCO frequency

- Constraint: must divide by integer values

Use PLL to synchronize reference and divider output

Output frequency is digitally controlledM.H. Perrott 5

Fractional-N Frequency Synthesizersref(t) div(t) e(t) v(t) e(t) v(t) Analog Loop Filter VCO div(t) Nsd[k] Modulator Divider N[k]

Kingsford-Smith US Patent (1974) Wells US Patent (1984)Fout = M.F Fref

ref(t)

Phase Detect

out(t)

Riley US Patent (1989) JSSC 93M.F

Dither divide value to achieve fractional divide values

- PLL loop filter smooths the resulting variations

Very high frequency resolution is achievedM.H. Perrott 6

The Issue of Quantization Noiseref(t) div(t) e(t) v(t) Fout = M.F Fref ref(t) Phase Detect e(t) v(t) Analog Loop Filter VCO div(t) Nsd[k] Modulator Divider N[k] M.F out(t)

Quantization Noise

Limits PLL bandwidth Increases linearity requirements of phase detectorM.H. Perrott

f7

Striving for a Better PLL Implementation

Analog Phase Detection1 D Q reset div(t) 1 D QReg

error(t) ref(t) div(t)

phase error

ref(t)

error(t)

ref(t)

Phase Detect div(t)

Analog Loop Filter VCO Divider

out(t)

M.H. Perrott

Pulse width is formed according to phase difference between two signals Average of pulsed waveform is applied to VCO input

9

Tradeoffs of Analog ApproachPhase Detector Signals ref(t) div(t) error(t) Phase Detector Characteristic

Average of error(t)Phase Detect div(t) Analog Loop Filter Divider

phase error

ref(t)

out(t)

VCO

M.H. Perrott

Benefit: average of pulsed output is a continuous, linear function of phase error Issue: analog loop filter implementation is undesirable

10

Issues with Analog Loop Filter

error(t)

Charge Pump

Vout Icp Cint

ref(t)

Phase Detect

Analog Loop Filter VCO Divider

out(t)

Charge pump: output resistance, mismatch Filter caps: leakage current, large areaM.H. Perrott 11

Going Digital ref(t) Phase Detect Analog Loop Filter VCO Divider out(t)

ref(t)

Time -toDigital

Digital Loop Filter DCO Divider

out(t)

Staszewski et. al., TCAS II, Nov 2003

Digital loop filter: compact area, insensitive to leakage Challenges:

M.H. Perrott

- Time-to-Digital Converter (TDC) - Digitally-Controlled Oscillator (DCO)

12

Outline of TalkOverview of Key Blocks (TDC and DCO) Modeling & CAD Tools High Performance TDC design Quantization Noise Cancellation DCO based on an efficient passive DAC structure Divider Design Loop Filter Design Prototype with measured Results

M.H. Perrott

13

Classical Time-to-Digital Converterdiv(t)Delay Delay Delay Delay

div(t)D Q Reg D Q Reg D Q Reg

e[k] ref(t)

1 1 1 0 0

e[k]

ref(t)

ref(t)

Time -toDigital div(t)


out(t)

Resolution set by a Single Delay Chain structure

- Phase error is measured with delays and registers

Corresponds to a flash architectureM.H. Perrott 14

Impact of Limited Resolution and Delay MismatchDelay varies due to mismatch

div(t)

1 1 1 0 0

Phase Detector Characteristic

e[k]

detector outputphase error out(t) DCO

ref(t)

ref(t)


Digital Loop Filter Divider

Integer-N PLL

- Limit cycles due to limited resolution (unless high ref noise) - Fractional spurs due to non-linearity from delay mismatch15

Fractional-N PLLM.H. Perrott

Modeling of TDCPhase Detector Characteristic quantization error tq[k] tdel time error phase error[k] T 2 TDC Gain 1 tdel e[k]

detector output

1

ref(t) T reference period



out(t)

M.H. Perrott

Phase error converted to time error by scale factor: T/2 TDC introduces quantization error: tq[k] TDC gain set by average delay per step: tdel

16

A Straightforward Approach for Achieving a DCO

Analog Control

Varactor

Varactor

DAC

ref(t)



out(t)

Ferriss ISSCC 2007 Hsu ISSCC 2008

Use a DAC to control a conventional LC oscillator

M.H. Perrott

- Allows the use of an existing VCO within a digital PLL - Can be applied across a broad range of IC processes

17

A Much More Digital Implementation

ref(t)

Adjust frequency in an LC oscillator by switching in a variable number of small capacitorsM.H. Perrott

- Most effective for CMOS processes of 0.13u and below

VaractorTime -toDigital div(t)

VaractorDigital Loop Filter DCO Divider

Digital Control

out(t)

Staszewski et. al., TCAS II, Nov 2003

18

Leveraging Segmentation in Switched Capacitor DCOBinary Array 1x 2x 4x 2 nx

Coarse Control

Varactor

Varactor

Unit Element Array 1x 1x 1x 1x

Fine Control

Similar in design as segmented capacitor DAC structures

- Binary array: efficient control, but may lack monotonicity - Unit element array: monotonic, but complex control

Coarse and fine control segmentation of DCO

- Coarse control: active only during initial frequency tuning (leverage binary array) - Fine control: controlled by PLL feedback (leverage unitelement array to guarantee monotonicity)19

M.H. Perrott

Leveraging Dithering for Fine Control of DCO

out(t)Coarse Initial Control Frequency

T ref(t)

Increase resolution by dithering of fine cap array Reduce noise from dithering by

- Using small unit caps in the fine cap array - Increasing the dithering frequency (defined as 1/T )c

M.H. Perrott

We will assume 1/Tc = M/T (i.e. M times reference frequency)

VaractorDivide-by-K

T c=T/M

Varactor

TuningFine Control

Digital Modulator

in[k] Digital Loop Filter

DCO

TDC out

20

Calculation of Noise Spectrum: Switched Cap DCO

Phase noise

- Same as for

Quantization noise from dithering

- See Section 3

Varactor

VaractorQuantization Noise qraw[k] Hntf(z) f M q[k] Tc in[k]

Digital Control

conventional VCO (tank Q, etc.)

Phase Noise z=ej2fTc f 2Kv s s=j2f21

out(t)

of Supplemental Slides

M.H. Perrott

Modeling

Overall Digital PLL ModelTDC TDC-referred Noise S tq(e j2fT) f tq[k] ref[k] T 2 DCO DCO-referred Noise S n(f) f TDC Gain 1 tdel Loop Filter e[k] H(z) z=ej2fT div[k] Divider CT-DT 1 N 1 T T DT-CT n(t) 2Kv s s=j2f out(t)

-20 dB/dec

M.H. Perrott

TDC and DCO-referred noise influence overall phase noise according to associated transfer functions to output Calculations involve both discrete and continuous time

23

Key Transfer Functionstq[k] ref[k] div[k] 1 N T 2 TDC Gain 1 tdel Loop Filter e[k] H(z) z=ej2fT CT-DT 1 T T DT-CT 2Kv s s=j2f n(t) out(t)

TDC-referred noise

DCO-referred noise

M.H. Perrott

24

Introduce a Parameterizing Functiontq[k] ref[k] div[k] 1 N T 2 TDC Gain 1 tdel Loop Filter e[k] H(z) z=ej2fT CT-DT 1 T T DT-CT 2Kv s s=j2f n(t) out(t)

Define open loop transfer function A(f) as:

Define closed loop parameterizing function G(f) as:

M.H. Perrott

- Note: G(f) is a lowpass filter with DC gain = 1

25

Transfer Function Parameterization CalculationsTDC-referred noise

DCO-referred noise

M.H. Perrott

26

Key Observationstq[k] ref[k] div[k] 1 N T 2 TDC Gain 1 tdel Loop Filter e[k] H(z) z=ej2fT CT-DT 1 T T DT-CT 2Kv s s=j2f n(t) out(t)

TDC-referred noiseLowpass with a DC gain of 2N

DCO-referred noiseHighpass with a high frequency gain of 1 How do we calculate the output phase noise?M.H. Perrott 27

Spectral Density Calculationsx(t) CT CT x[k] DT DT x[k] DT CT H(f) H(ej2fT) y(t) H(f) y[k] y(t)

CT DT DTM.H. Perrott

CT DT CT28

Phase Noise CalculationTDC-referred Noise S tq(e j2fT) f tq[k] fo 2N G(f) fo DCO-referred Noise S n(f) f n(t) 1-G(f)

TDC noise

-20 dB/dec

- DT to CT calculation - Dominates PLL phase

noise at low frequency offsets

DCO noise

out(t)2 1 2N G(f) S tq(e j2fT) T

- CT to CT calculation - Dominates PLL phase

noise at high frequency offsets

1- G(f) S n(f) dBc/Hz f29

2

foM.H. Perrott

Example Calculation for Delay Chain TDCRef freq = 1/T = 50 MHz, Out freq = 3.6 GHzS tq(e j2fT) tdel 12 f tq[k]2

Inverter delay = tdel = 20 psS out(f)tdc

fo

2N G(f)2 2 tdel

1 2N G(f) T f

12

fo

Note: G(f) = 1 at low offset frequencies

M.H. Perrott

30

CAD Tools

Closed Loop PLL Design ApproachOpen-Loop Design Approach G(f) = A(f) 1+A(f)

Closed-Loop Performance Specifications {f o, type, order}

Open-Loop Characteristics |A(f)| A(f) {K,f p,f z, ...}

A(f) =

G(f) 1-G(f)

Closed-Loop Transfer Function G(f)

Proposed Closed Loop Design Approach

Classical open loop approach

Lau and Perrott, DAC, June 2003

- Indirectly design G(f) using bode plots of A(f) - Directly design G(f) by examining impact of its specifications on phase noise (and settling time) - Solve for A(f) that will achieve desired G(f)Implemented in PLL Design Assistant Softwarehttp://www.cppsim.com32

Proposed closed loop approach

M.H. Perrott

Evaluate Phase Noise with 500 kHz PLL BandwidthKey PLL parameters:

- G(f): 500 kHz BW, Type II, 2 order rolloff - TDC noise: -94.7 dBc/Hz - DCO noise: -153 dBc/Hz at 20 MHz offset (3.6 GHz carrier)nd

M.H. Perrott

33

Calculated Phase Noise Spectrum with 500 kHz BW-60 -70 -80 -90

Output Phase Noise of SynthesizerDetector Noise VCO Noise Total Noise

Overall PLL Phase Noise TDC Noise

GSM Mask (Referenced to 3.6 GHz carrier)

L(f) (dBc/Hz)

-100 -110 -120 -130 -140 -150 -160 3 10 104

DCO Noise

10

5

10

6

10

7

Frequency Offset (Hz)

TDC noise too high for GSM mask with 500 kHz PLL bandwidthM.H. Perrott 34

Change PLL Bandwidth to 100 kHzKey PLL parameters:

- G(f): 100 kHz BW, Type = 2, 2 order rolloff - TDC noise: -94.7 dBc/Hz - DCO noise: -153 dBc/Hz at 20 MHz offset (3.6 GHz carrier)nd

M.H. Perrott

35

Calculated Phase Noise Spectrum with 100 kHz BW-60 -70 -80 -90

Output Phase Noise of SynthesizerDetector Noise VCO Noise Total Noise

Overall PLL Phase Noise TDC Noise

GSM Mask (Referenced to 3.6 GHz carrier)

L(f) (dBc/Hz)

-100 -110

DCO Noise-120 -130 -140 -150 -160 3 10 104

10

5

10

6

10

7

Frequency Offset (Hz)

GSM mask is met with 100 kHz PLL bandwidthM.H. Perrott 36

Loop Filter Design using PLL Design AssistantPLL Design Assistant allows fast loop filter design

- See Section 4 of Supplemental Slides

Assumption: Type = 2, 2nd order rolloff

- Where:

PLL Design Assistant provides the values of K, wp = 2fp, wz = 2fzM.H. Perrott 37

Example Digital Loop Filter CalculationAssumptionsdel

- Ref freq (1/T) = 50 MHz, Out freq = 3.6 GHz (so N = 72) - t = 20 ps, K = 12 kHz/unit cap - 100 kHz bandwidth, Type = 2 , 2 order rolloffv nd

M.H. Perrott

38

Verify Calculations Using C++ Behavioral Modeling1

D Q R

CppSim Module Description Name Inputs, Outputs Parameters Code

Schematic

- Hierarchical

1

R D Q

description of system topology

PFD

Charge Pump

Loop Filter

Code blocksof module behavior using templated C++ code

- Specification

Divider ModulatorCppSim Module Description Name Inputs, Outputs Parameters Code

Behavioral environment allows efficient architectural investigation and validation of calculationsM.H. Perrott

- Fast simulation speed is essential for design investigation

39

CppSim A Fast C++ Behavioral Simulator

http://www.cppsim.comM.H. Perrott 40

How Do We Improve TDC Performance?Two Key Issues: TDC resolution Mismatch

MotivationTDC-referred Noise S tq(e j2fT) f tq[k] fo 2N G(f) fo DCO-referred Noise S n(f) f n(t) 1-G(f)

-20 dB/dec

PLL bandwidth dramatically influences relative impact of TDC and VCO noiseWant high PLL bandwidth? Need low TDC Noise

out(t) Low PLL BandwidthDCO Noise

High PLL BandwidthTDC Noise

dBc/Hz

TDC Noise

dBc/Hz fDCO Noise

foM.H. Perrott

fo

f42

Improve Resolution with Vernier Delay Techniquediv(t)Delay Delay Delay Delay

div(t)D Q Reg D Q Reg D Q Reg

e[k] ref(t)Delay

1 1 1 0 0

e[k]

ref(t)

Vernierdiv(t)Delay Delay Delay

div(t)

D Q Reg

D Q Reg

D Q Reg

1 1 1 0 0

e[k]

ref(t)

ref(t)

Delay2

Delay2

Delay2

e[k]Delay2

Effective resolution: Delay-Delay243

M.H. Perrott

Issues with Vernier ApproachMismatch issues are more severe than the single delay chain TDC

- Reduced delay is formed as difference of two delaysDelay

Large measurement range requires large area

- Initial PLL frequency acquisition may require a large rangeVernierdiv(t)Delay Delay Delay

div(t)

D Q Reg

D Q Reg

D Q Reg

1 1 1 0 0

e[k]

ref(t)

ref(t)

Delay2

Delay2

Delay2

e[k]Delay2

Effective resolution: Delay-Delay244

M.H. Perrott

Two-Step TDC Architecture Allows Area ReductionSingle Delay Chain VernierDelay Delay Delay Delay Mux D Q Reg D Q Reg D Q Reg Delay2 Delay2 Delay2 D Q Reg D Q Reg D Q Reg Delay Delay

div(t)

ref(t) Logic Coarse e[k]

Ramakrishnan, Balsara VLSID 06

Fine e[k]Delay - Delay2

Single delay chain provides coarse resolution (Folded) Vernier provides fine resolutionM.H. Perrott

Delay

45

Two-Step TDC Using Time AmplificationSingle Delay Chain Single Delay Chain Time AmplifierDelay Mux D Q Reg D Q Reg D Q Reg D Q Reg D Q Reg D Q Reg Delay Delay

div(t)

Delay

Delay

Delay

ref(t) Logic Coarse e[k]Delay Amplification of Time

Simplified view of: Lee, Abidi VLSI 2007

Fine e[k]

Single delay chain provides coarse and fine resolution Time amplification is used to improve resolutionM.H. Perrott

Delay

46

Leveraging Metastability to Create a Time Amplifierin(t) ref(t) in(t) Time Amplifier out(t) ref(t) ref(t) in(t) out(t) tout tinD Q Latch

out(t) tin

ref(t) in(t) out(t) tout

Simplified view of: Abas, et al., Electronic Letters, Nov 2002 (note that actual implementation uses SR latch)

Metastability leads to progressively slower output transitions as setup time on latch is encroached uponM.H. Perrott

- Time difference at input is amplified at output

47

Interpolating time-to-digital converterTqDelay Delay Delay

Start

1 1 1 1 Out

Start

Stop

Registers

Tstop

1 1 0

Out

Stop Tin

Henzler et al., ISSCC 2008

Interpolate between edges to achieve fine resolution Cyclic approach can also be used for large rangeM.H. Perrott 48

An Oscillator-Based TDCPhase Error[1] Vdd Ring Oscillator div(t) ref(t) Osc(t) Reset ref(t) Logic div(t) Counter Count[k] Register e[k] e[k] Count[k] Phase Error[2]

3

3

Output e[k] corresponds to the number of oscillator edges that occur during the measurement time window Advantages

M.H. Perrott

- Extremely large range can be achieved with compact area - Quantization noise is scrambled across measurements

49

A Closer Look at Quantization Noise ScramblingPhase Error[1] Vdd Ring Oscillator div(t) ref(t) Osc(t) Reset ref(t) Logic div(t) Counter Count[k] Register e[k] Count[k] Quant. Error[k] -q[0] e[k] q[1] -q[2] q[3] Phase Error[2]

3

3

Quantization error occurs at beginning and end of each measurement interval As a rough approximation, assume error is uncorrelated between measurementsM.H. Perrott

- Averaging of measurements improves effective resolution

50

Deterministic quantizer error vs. scrambled error

Deterministic TDC do not provide inherent scrambling For oversampling benefit, TDC error must be scrambled! Some systems provide input scrambling ( fractional-N PLL), while some others do not (integer-N PLL)M.H. Perrott 51

Proposed GRO TDC Structure

A Gated Ring Oscillator (GRO) TDCPhase Error[1] Ring Oscillator Enable ref(t) Osc(t) Reset ref(t) Logic div(t) Counter Count[k] Register e[k] Count[k] Quant. Error[k] -q[0] e[k] q[1] -q[1] q[2] div(t) Phase Error[2]

3

4

Enable ring oscillator only during measurement intervals

- Hold the state of the oscillator between measurements - e[k] = Phase Error[k] + q[k] q[k-1] - Averaging dramatically improves resolution!

Quantization error becomes first order noise shaped!M.H. Perrott 53

Improve Resolution By Using All Oscillator PhasesPhase Error[1] Ring Oscillator Enable ref(t) div(t) Phase Error[2]

Reset ref(t) Logic div(t) Count[k] Register e[k] Counters

Osc. Phases(t)

Count[k] q[1] -q[0] -q[1] q[2]

Helal, Straayer, Wei, Perrott VLSI 2007

Quant. Error[k] e[k]

11

10

Raw resolution is set by inverter delay Effective resolution is dramatically improved by averaging M.H. Perrott

54

GRO TDC Also Shapes Delay MismatchEnable

Measurement 1

Enable

Measurement 2

Enable

Measurement 3

Enable

Measurement 4

Barrel shifting occurs through delay elements across different measurementsM.H. Perrott

- Mismatch between delay elements is first order shaped!

55

Simple gated ring oscillator inverter-based coreEnabled Ring Oscillator Disabled Ring Oscillator

(a)Enable

(b)

Delay ElementEnable

Gate the oscillator by switching the inverter cores to the power supply

Vo n-1 Vo 5 Vo 4 Vo 3 Vo 2 Vo n Vo 1Enable

M4 M3

Vo i-1M2 M1

Vo i

M.H. Perrott

56

GRO Prototypeenable 15 Stage Gated Ring Oscillator En DisS Q R

enable(t) enable

Straayer, Perrott

Logic

error[k]

GRO implemented as a custom 0.13 m CMOS IC

M.H. Perrott

57

Measured GRO Results Confirm Noise Shapingenable 15 Stage Gated Ring Oscillator Variable DelayS Q R

enable(t) enable

40

30

Input variable delay signal

20

Harmonics due to nonlinearity of variable delay

Logic

error[k]

Amplitude (dB)

10

0

-10

-20

Noise shaped quant. noise0.1

-30 0.01

M.H. Perrott

Frequency (MHz)

1

10

100

58

Measured deadzone behavior of inverter-based GRO

Deadzones were caused by errors in gating the oscillator GRO injection locked to an integer ratio of FS Behavior occurred for almost all integer boundaries, and some fractional values as well Noise shaping benefit was limited by this gating errorM.H. Perrott 59

Next Generation GRO: Multi-path oscillator conceptSingle Input Single Output

Multiple Inputs Single Output

Use multiple inputs for each delay element instead of one Allow each stage to optimally begin its transition based on information from the entire GRO phase state Key design issue is to ensure primary mode of oscillationM.H. Perrott 60

Multi-path inverter coreLee, Kim, Lee JSSC 1997

Mohan, et. al., CICC 2005

M.H. Perrott

61

Proposed multi-path gated ring oscillator

Hsu, Straayer, Perrott ISSCC 2008

Oscillation frequency near 2GHz with 47 stages Reduces effective delay per stage by a factor of 5-6! Represents a factor of 2-3 improvement compared to previous multi-path oscillatorsM.H. Perrott 62

A simple measurement approachN-Stage Gated Ring Oscillator Enable

Reset Start Logic Stop Count[k] Register e[k] Counters

Helal, Straayer, Perrott VLSI 2007

2 counters per stage * 47 stages = 94 counters each at 2GHz Power consumption for these counters is unreasonable Need a more efficient way to measure the multi-path GROM.H. Perrott 63

Count Edges by Sampling Phase

Calculate phase from:

- A single counter for coarse phase information (keeps track of phase wrapping) - GRO phase state for fine count informationmuch more efficient64

M.H. Perrott

1 counter and N registers

Proposed Multi-Path Measurement Structure

Multi-path structure leads to ambiguity in edge position Partition into 7 cells to avoid such ambiguity Requires 7 counters rather than 1, but power still OKM.H. Perrott 65

Prototype 0.13m CMOS multi-path GRO-TDCStart Stop Timing Generation Enable 47-stage Gated Ring Oscillator Z1-47 State Register Start Stop Enable CLK 1 2 3 4 5 6 7 Measurement Cells Out

CLK

Adder

Straayer et al., VLSI 2008

Two implemented versions:

- 8-bit, 500Msps - 11-bit, 100Msps version

2-21mW power consumption depending on input duty cycleM.H. Perrott 66

Measured noise-shaping of multi-path GRO65,536 pt. FFT-40 -50 -60 -70 -80 -90Noise of 80fsrms in 1MHz BW

(Hanning window + 20x averaging)Input of 1.2pspp279.2

TDC Output after 1MHz LPF

Power Spectral Density (dB ps2/Hz)

Filtered TDC Output

279.0

278.8

-100

Ideal variance of 50-Msps quantizer with 1ps steps

1.2ps278.6 0 40 80 120 160 200

104

105

106

107

Frequency (Hz)

Time (s)

(a)

(b)

Data collected at 50Msps More than 20dB of noise-shaping benefit 80fsrms integrated error from 2kHz-1MHz Floor primarily limited by 1/f noise (up to 0.5-1MHz)M.H. Perrott 67

Measured deadzone behavior for multi-path GRO

Only deadzones for outputs that are multiples of 2N

- 94, 188, 282, etc. - No deadzones for other even or odd integers, fractional output68

Size of deadzone is reduced by 10xM.H. Perrott

The Issue of Quantization Noise Due to Divider Dithering

The Nature of the Quantization Noise ProblemRef PFD DivN/N+1

Loop Filter

Out

1-bit Frequency M-bit Selection ModulatorQuantization Noise SpectrumFrequency Selection

Output Spectrum Noise

Fout PLL dynamics

Increasing PLL bandwidth increases impact of fractional-N noiseM.H. Perrott

- Cancellation offers a way out!

70

Previous Analog Quantization Noise Cancellation

Phase error due to is predicted by accumulating quantization error Gain matching between PFD and D/A must be precise

Matching in analog domain limits performanceM.H. Perrott 71

Proposed All-digital Quantization Noise Cancellation

Hsu, Straayer, Perrott ISSCC 2008

Scale factor determined by simple digital correlation Analog non-idealities such as DC offset are completely eliminatedM.H. Perrott

72

Details of Proposed Quantization Noise Cancellation

Correlator out is accumulated and filtered to achieve scale factor

- Settling time chosen to be around10 us

See analog version of this technique in Swaminathan et.al., ISSCC 2007 M.H. Perrott

73

Proposed Digital Wide BW Synthesizer

Gated-ring-oscillator (GRO) TDC achieves low in-band noise All-digital quantization noise cancellation achieves low out-of-band noise Design goals:M.H. Perrott

- 3.6-GHz carrier, 500-kHz bandwidth -

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Digital Pll Cicc Tutorial Perrott