Digital Integrated CircuitDesigneen.iust.ac.ir/profs/Abrishamifar/Digital Integrated Circuit Design... · VLSI Design and VLSI Circuit Design all ... However, I’d like to thank

Adib AbrishamifarEE Department

IUST

Lecture 13 – Building Blocks (Multipliers)

Digital Integrated Circuit Design

Adder

Register

Shift Register

IUST: Digital IC Design LECTURE 13 : Building BlocksLECTURE 13 : Building Blocks Adib Abrishamifar 20092/76

} This lecture note has been summarized and categorized from lecture note on Introduction to VLSI Design and VLSI Circuit Design all over the world. I can’t remember where those slide come from. However, I’d like to thank all professors who create such a good work on those lecture notes. Without those lectures, this slide can’t be finished.

Acknowledgement


Contents

} Outline} Introduction} Signed Integers} Review - Multiplication} Multipliers} Sequential (Serial) Multiplier} Array Multipliers

• Combinational Multiplier• Booth Multiplier• Pipelined Multiplier• Wallace Tree Multiplier• Carry Save Multiplier

} Serial-Parallel Multiplier} Summary


Outline

} Building Blocks for Digital Architectures} Arithmetic unit

• Bit-sliced datapath (Adders, Multipliers, Shifters, Comparators, etc.)

} Memory• RAM, ROM, Buffers, Shift registers

} Control• Finite state machine (PLA, random logic)• Counters

} Interconnect• Switches• Arbiters• Bus


Contents





Introduction

} Multipliers are used in a lot of DSP applications} Vector product, matrix multiplication} Convolution} Filtering (tap filters, FIR, …)} ...

} At least one good reason for studying multiplication and division is that there is an infinite number of ways of performing these operations


Contents





Signed Integers

} What Not to Do} Use fixed length binary representation} Use left-most bit (called most significant bit or MSB)

for sign:0 for positive1 for negative

} Example: +18ten = 00010010two

–18ten = 10010010two


Signed Integers

} Why Not to Use Sign Bit} Sign and magnitude bits should be differently treated

in arithmetic operations} Addition and subtraction require different logic

circuits} Overflow is difficult to detect} “Zero” has two representations:

+ 0ten = 00000000two– 0ten = 10000000two

} Signed-integers are not used in modern computers


Signed Integers

} Integers With Sign – Other Ways} Use fixed-length representation, but no sign bit

• 1’s complement: To form a negative number, complement each bit in the given number

• 2’s complement: To form a negative number, start with the given number, subtract one, and then complement each bit, or first complement each bit, and then add 1

} 2’s complement is the preferred representation


Signed Integers

} 2’s-Complement} Why not 1’s-complement? Don’t like two zeros} Add 1 to 1’s-complement representation} Some properties:

• Only one representation for 0• Exactly as many positive numbers as negative numbers• Slight asymmetry – there is one negative number with no

positive counterpart


0000

10000111

1111

1010 = – 2

Signed integers

0000

1000

1111

1010 = – 5

1’s complement integers

0010

1010 1010

0101

2

– 25

– 5

0000

1000

1111

10000

1010 = – 6

2’s complement integers

1010 01106– 6

0– 0

0

– 7 – 87 7

0

– 07

– 7

Signed Integers

}} Three SystemsThree Systems


Sign-magnitude

000 = +0001 = +1010 = +2011 = +3100 = - 0101 = - 1110 = - 2111 = - 3

2’s complement

000 = +0001 = +1010 = +2011 = +3100 = - 4101 = - 3110 = - 2111 = - 1

(Preferred)

1’s complement

000 = +0001 = +1010 = +2011 = +3100 = - 3101 = - 2110 = - 1111 = - 0

Signed Integers

}} Three RepresentationsThree Representations


Signed Integers

} 2’s Complement n-bit Numbers} Range: –2n –1 through 2n –1 – 1 } Unique zero: 00000000 . . . . . 0} Expansion of bit length: stretch the left-most bit all the

way, e.g., 11111101 is still – 3.} Overflow rule: If two numbers with the same sign bit

(both positive or both negative) are added, the overflow occurs if and only if the result has the opposite sign


an-1an-2 . . . a1a0 = -2n-1an-1 + Σ 2i aii=0

n-2

-128 64 32 16 8 4 2 18-bit conversion box

-128 64 32 16 8 4 2 11 1 1 1 1 1 0 1

Example

-128+64+32+16+8+4+1 = -128 + 125 = -3

Signed Integers

} 2’s-Compliment to Decimal Conversion


Contents





} Basic algorithm analogous to decimal multiplication} Break multiplier into digits} Multiply one digit at a time;

shift multiplicand to form partial products} Create product as sum of partial products

} n bit multiplicand X m bit multiplier = (n+m) bit product

Multiplicand 0110 (6)Multiplier X 0011 (3)

0110011000000000

Product 00010010 (18)

Partial Products

Review - Multiplication


0 1 0 1 +5x0 0 1 1 +30 1 0 1

0 1 0 10 0 0 0

0 0 0 00 0 0 1 1 1 1 +15

1 0 1 1 -5x0 0 1 1 +3

1 1 1 1 0 1 11 1 1 0 1 10 0 0 0 00 0 0 01 1 1 0 0 0 1 -15


} 2’s complement} Multiplier positive, Multiplicand +/- :

• Sign extend the partial products when adding up• Example:


} 2’s complement (cont.)} Mplier negative, Mcand +/- :

• convert negative Mplier to positive, do the multiplication, negate the result

• Example:

1 0 1 1 -5x1 1 0 1 -3

1 0 1 1 -5x0 0 1 1 +3

1 1 1 1 0 1 11 1 1 0 1 10 0 0 0 00 0 0 01 1 1 0 0 0 1 -150 0 0 1 1 1 1 +15



Iteration Step Multiplicand Product

0 Initial values 0010 0000 0011

1 LSB=1 => Prod=Prod+Mcand 0010 0010 0011

Right shift product 0010 0001 0001



3 LSB=0 => no operation 0010 0001 1000


4 LSB=0 => no operation 0010 0000 1100


0010two× 0011two = 0110two, i.e., 2ten×3ten = 6ten


} Example


Iteration Step Multiplicand Product

0 Initial values 11010 00000 0011





3 LSB=0 => no operation 11010 11011 1000


4 LSB=0 => no operation 11010 11101 1100


1010two× 0011two = 101110two, i.e., -6ten×3ten = -18ten


} Example


Iteration Step Multiplicand Product0 Initial values 11010 00000 10111 LSB=1 => Prod=Prod+Mcand 11010 11010 1011

Right shift product 11010 11101 01012 LSB=1 => Prod=Prod+Mcand 11010 10111 0101

Right shift product 11010 11011 10103 LSB=0 => no operation 11010 11011 1010

Right shift product 11010 11101 11014 LSB=1 => Prod=Prod – Mcand* 00110 00011 1101


1010two× 1011two = 011110two, i.e., -6ten×(-5ten) = 30ten

*Last iteration with a negative multiplier in 2*Last iteration with a negative multiplier in 2’’s complements complement


} Example


Contents





Multipliers

} There are many different circuits for multiplication

} Each one has a different balance between speed(performance) and amount of logic (cost)


Contents





} Compute the sums as a sequence of separate steps} Main benefit: only requires one 2:1 adder

• Much lower hardware cost for large n} Use a register to store the partial products} Use two registers to store the multiplier and

multiplicand} Requires a state machine (with the corresponding

control logic) to control the sequence of additions used

Sequential Multiplier


} Shift register} Originally holds multiplicand} Shifts it left for each partial product

} One bit of multiplier at a time presented to the AND gates

Adder

Shift Register

Register

0

Initializedw/mcand, shifts it left

One bit of mplier applied each cycle

2N bits



Adder

Register

Shift Register


} Resource Requirements} Adder: 2N-bit} Registers: 2N-bit wide} A state machine



} Better design:} Shift result register to right} Uses N AND gates} Uses N-bit adder

Adder

Register

Shift Register


Contents





y3 y2 y1 y0 multiplicandx3 x2 x1 x0 multiplier

________________________x0y3 x0y2 x0y1 x0y0 four

carry←x1y3 x1y2 x1y1 x1y0 partialcarry←x2y3 x2y2 x2y1 x2y0 products

carry← x3y3 x3y2 x3y1 x3y0 to be__________________________________________________ summedp7 p6 p5 p4 p3 p2 p1 p0

Requires three 4-bit additions. Slow.

Array Multipliers

} Adding Partial Products


y3 y2 y1 y0 multiplicandx3 x2 x1 x0 multiplier

________________________x0y3 x0y2 x0y1 x0y0 four

x1y3 x1y2 x1y1 x1y0 partialx2y3 x2y2 x2y1 x2y0 products

x3y3 x3y2 x3y1 x3y0 to be__________________________________________________ summedp7 p6 p5 p4 p3 p2 p1 p0

Note: Carry is added to the next partial product (carry-save addition).Adding the carry from the final stage needs an extra (ripple-carrystage. These additions are faster but we need four stages.

Array Multipliers

} Carry Forward


FA

xiyjppk

ppk+1co

ci

y3 y2 y1 y0x0

x1

x2

x30

0

0

0

0 0 0 0

p7 p6 p5 p4 p3 p2 p1 p0FA FA FA FA

Critical path0

Array Multipliers

} Structure


Contents





} Also referred to as a parallel multiplier} Implement multiplication using a 2-dimensional

array of 1-bit full adders} Basic structure is the same as the addition array } Can also be implemented using a linear array of CSA

• Each partial product Pi = 2i ai B• At first CSA level, add three partial products• At all subsequent CSA levels, add one more partial product• A CLA (or other type of 2:1, 2-input/1-output, adder) is

required after the final CSA level

Combinational Multiplier


} Idea} Use an array of AND gates to generate the partial

products in parallel

LSB LSB1 1 01

1

0

1 1 0

01001

multiplier

multiplicand

1 1 0

0 0 0



HA FA FA HA

X3 X2 X1 X0Y1

X3 X2 X1 X0Y0

Z0

FA FA FA HA

X3 X2 X1 X0Y2

Z1

FA FA FA HA

X3 X2 X1 X0Y3

Z2

Z3Z4Z5Z6Z7


} Adding PProds


} Critical Path} A lot of critical paths, same delay (AND gates not

shown)

Delay=(M+N-2)tcarry+(N-1)tsum+tAND

HA FA FA HA

FA FA FA HA

FA FA FA HA

Critical Path 1Critical Path 2

MxNMultiplier

NM



HA FA FA HA

HAFAFAFA

FAFA FA HA

Critical Path 1

Critical Path 2

Critical Path 1 & 2


} MxN Critical Paths

( ) ( ) ( ) ( )1 2 1 1mult carry sum andt M N t N t N t= − + − + − + −


HA FA FA HA

FA FA FA HA

FA FA FA HA


} Better floorplan for compact layout} Send partial product diagonally} Results in better area} AND gates and hence the first row not shown


Contents





} Originally proposed to reduce addition steps} Bonus: works for two’s complement numbers} Encoding scheme to reduce number of stages in

multiplication} Performs two bits of multiplication at once

requires half the stages} Each stage is slightly more complex than simple

multiplier, but adder/subtracter is almost as small/fast as adder

Booth Multiplier


} There are multiple ways to create a product} Example: multiply 2ten by 6ten (0010two X 0110two)} Product = (2 X 2) + (2 X 4) OR} Product = (2 X -2) + (2 X 8)

} Idea} Recode each 1 in multiplier as “+2-1”

• Converts sequences of 1 to 10…0(-1)• Might reduce the number of 1’s

Booth Multiplier


0 0 1 1 1 1 1 1 0 0

+1 -1+1 -1

+1 -1+1 -1

+1 -1+1 -1

0 1 0 0 0 0 0 -1 0 0

Booth Multiplier

} Example


0 0 1 1 0 6x0 1 1 1 0 14+1 0 0 -1 00 0 0 0 0

1 1 0 1 0 (-6)0 0 0 0 0

0 0 0 0 00 0 1 1 00 0 1 0 1 0 1 0 0 84

1 1 1

Sign extension

} Example

Booth Multiplier


} Booth encoding} Two’s-complement form of multiplier

• y = -2nyn + 2n-1yn-1 + 2n-2yn-2 + ...} Rewrite using 2a = 2a+1 - 2a

• y = -2n(yn-yn-1) + 2n-1(yn-2 -yn-1) + 2n-2(yn-3 -yn-2) + ...} Consider first two terms: by looking at three bits of y, we

can determine whether to add x, 2x to partial product

Booth Multiplier


yi yi-1 yi-2 increment0 0 0 00 0 1 x0 1 0 x0 1 1 2x1 0 0 -2x1 0 1 -x1 1 0 -x1 1 1 0

Booth Multiplier

} Booth actions


Booth Multiplier

} Booth example} x = 011001 (2510), y = 101110 (-1810)} y1y0y-1 = 100, P1 = P0 - (10 ⋅ 011001) = 11111001110} Y3y2y1 = 111, P2 = P1+ 0 = 11111001110} Y5y4y3 = 101, P3 = P2 - 0110010000 = 11000111110


} Question: } How do we know when to subtract?} When do we know when to add?

} Answer: look for “runs of 1s” in multiplier} Example: 001110011} Working from Right to Left, any “run of 1’s” is equal to:

- value of first digit that’s one+value of first digit that’s zero

} Example : 001110011• First run: -1 + 4 = 3• Second run: -16 + 128 = 112• Total: 112 + 3 = 115

Booth Multiplier


} Scan multiplier bits from right to left} Recognize the beginning and in of a run looking at only 2 bits

at a time} “Current” bit ai

} Bit to right of “current” bit ai-1

0 1 1 0 0 1 1 1 0 0

BeginningOf Run

MiddleOf Run

EndOf Run

Bit ai Bit ai-1 Explanation1 0 Begin Run of 1’s1 1 Middle of Run of 1’s0 1 End of Run0 0 Middle of Run of 0’s

Booth Multiplier


} Key idea: test 2 bits of multiplier at once} 10 - subtract (beginning of run of 1’s)} 01 - add (end of run of 1’s) } 00, 11 - do nothing (middle of run of 0’s or 1’s)

Multiplicand (32 bits)

Product(64 bits) Write

Control

32-bit ALU

Shift Left

ADD/SUB

2Bits 1:0

LHPROD(32 bits)

MP/RHPROD(32 bits)

Booth Multiplier


Booth Multiplier

} Booth Structure


} Advantages and Disadvantages} Depends on the architecture

• Potential advantage: might reduce the # of 1’s in multiplier} In the multipliers that we have seen so far

• Doesn’t save in speed (still have to wait for the critical path, e.g., the shift-add delay in sequential multiplier)

• Increases area: recoding circuitry AND subtraction

Booth Multiplier


Contents





} Insert registers (latches) between rows} Insert registers for bits of multiplier} Schedule MSB bits to arrive later

HA FA FA HA

FA FA FA HA

FA FA FA HA

Pipelined Multipliers

IUST: Digital IC Design LECTURE 13 : Building BlocksLECTURE 13 : Building Blocks Adib Abrishamifar 200956/76p0p1p3p6p7p8p9 p5 p4

x0 x1 x2 x3 x44a 0a1a2a3a

p2

FA withFA withAND gate AND gate and latchesand latches

(for (for aaii,,intermediateintermediate

sum andsum andcarry)carry)

FAFA

LatchLatch

Sum/Sum/carrycarrypathpath

Pipelined Multipliers

} Example


Contents





} Idea: divide & conquer} Why add the k numbers one by one?} Tree structure è logarithmic

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Wallace Tree Multiplier


Delay = 4 CSA + 1 CLA


} Example


[0,k-1] [0,k-1][0,k-1] [0,k-1]

[1,k] [0,k-1] [1,k] [0,k-1]K-bit CSA K-bit CSA

[1,k] [0,k-1]

K-bit CSA

[2,k+1] [1,k]K-bit CSA

[2,k+1] [1,k+1]K-bit CSA

[0,k-1] [0,k-1][0,k-1]

[1,k-1], ‘0’

K-bit CPA[0][1]

[2,k+1]

[2,k+1][k+2]

‘0’,[2,k][k+1]


} For 7 k-bit


CSA CSA CSA CSA CSA CSA

CSA CSA CSA CSA

CSA CSA CSA

CSA CSA

n k-bit numbersn k-bit numbers

(2/3) nnums(2/3) nnums

CSA CSA CSA CSA(2/3)2 n(2/3)2 n

CSA. . .

(2/3)h n = 2(2/3)h n = 2

h levels


} At each step, # of operands reduces to 2/3


h N h N h N0 2 7 28 14 4741 3 8 42 15 7112 4 9 63 16 10663 6 10 94 17 15994 9 11 141 18 23985 13 12 211 19 35976 19 13 316 20 5395


} Delay depends on height h} h = O ( log n ) è Logarithmic delay} Max # N of k-bit numbers that can be added using a

Wallace tree of height h


} Reduces depth of adder chain} Built from carry-save adders:} Three inputs a, b, c } Produces two outputs y, z such that y + z = a + b + c

} Carry-save equations:} yi = parity(ai,bi,ci)} zi = majority(ai,bi,ci)



6 5 4 3 2 1 0 6 5 4 3 2 1 0

Partial products First stage

Bit position

6 5 4 3 2 1 0 6 5 4 3 2 1 0Second stage Final adder

FA HA

(a) (b)

(c) (d)


} Wallace Tree Multiplier


Partial products

First stage

Second stage

Final adder

FA FA FA

HA HA

FA

x3y3

z7 z6 z5 z4 z3 z2 z1 z0

x3y2x2y3

x1y1x3y0 x2y0 x0y1x0y2

x2y2x1y3

x1y2x3y1x0y3 x1y0 x0y0x2y1


} Wallace Tree Multiplier


} At each stage, i numbers are combined to form ceil(2i/3) sums

} Final adder completes the summation} Wiring is more complex} Can build a Booth-encoded Wallace tree

multiplier



Contents





Carry Save Multiplier

} Speeding up multiplication is a matter of speeding up the summing of the partial products

} “Carry-save” addition can help} Carry-save addition passes (saves) the carries to

the output, rather than propagating them} In general, carry-save addition takes in 3 numbers

and produces 2} Whereas, carry-propagate takes 2 and produces 1} With this technique, we can avoid carry

propagation until final addition


310 0011+ 210 0010

c 0100 = 410

s 0001 = 110

310 0011c 0010 = 210

s 0110 = 610

1000 = 810

carry-save add

carry-save add

carry-propagate add


} Sum three numbers, 310 = 0011, 210 = 0010, 310 = 0011



HA HA HA HA

FAFAFAHA

FAHA FA FA

FAHA FA HA

Vector Merging Adder

( ) ( )1 1mult carry and merget N t N t t= − + − +

} Carry Save Adder



SCSCSCSC

SCSCSCSC

SCSCSCSC

SC

SC

SC

SC

Z0

Z1

Z2

Z3Z4Z5Z6Z7

X0X1X2X3

Y1

Y2

Y3

Y0

Vector Merging Cell

HA Multiplier Cell

FA Multiplier Cell

X and Y signals are broadcastedthrough the complete array.

} Carry Save Multiplier Floorplan


Contents





} Used in serial-arithmetic operations} Multiplicand can be held in place by register} Multiplier is shfited into array

Serial-Parallel Multiplier


} Structure

Serial-Parallel Multiplier


Contents





Summary

} Goals different than addition} In some structures, sum and carry delay equal} Analysis more difficult : Multiple critical paths

} Different levels of optimization} Data encoding (Booth)} Architecture-level: Wallace Tree} Gate-level: pipelining} Transistor-level: equal sum, carry delays

} More to cover} Constant multiplication} Floating point, precision

Documents

Digital Integrated CircuitDesigneen.iust.ac.ir/profs/Abrishamifar/Digital Integrated Circuit Design... · VLSI Design and VLSI Circuit Design all ... However, I’d like to thank