Digital Electronic Circuits -Lesson plan and QB.pdf

P.E.S.I.T DEPT. OF TE III SEM (AUTONOMOUS) 1

DIGITAL ELECTRONICS CIRCUITS (Theory)

LESSON PLAN

Subject Code: 11 TE 204 Faculty: Ms.MP No. of Hours: 52

Class #

Chapter Title / Reference Literature

Topics to be covered % of Portions covered

Reference Chapter

Cumulative

1-8

UNIT 1

Boolean Algebra &Combinational Networks T1: 3.1.1, 3.2, 3.4, 3.5, 3.6, 3.8, 3.9.1- 3.9.5 T2: 3.1.1,3.1.2

Boolean algebra theorems, Boolean formulae and functions, Canonical Formulas, Manipulations of Boolean formulas, incomplete Boolean functions and Don’t care conditions in Logic Design. Definition of combinational logic: problem statements to truth tables, deriving switching equations. NAND and NOR function, universal gates and NAND & NOR realization.

15%

15%

9-21

UNIT 2 Simplification of Boolean Expressions T1: 4.1, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7.1, 4.8, 4.9, 4.10, 4.11, 4.14

Formulation of the simplification Problem,criteria for minimality, Prime Implicants and Irredundant Disjunctive Expressions, Prime Implicates and Irredundant Conjunctive Expressions,

23% 38%

Karnaugh Maps, using K-maps to obtain minimal expressions for complete Boolean functions, minimal expression of incomplete Boolean functions, five-variable maps,

The Quine-McLuskey method of generating prime implicants and prime implicates, prime implicant/prime implicate tables and irredundant expressions, prime implicant/prime implicate table reductions, Decimal method for obtaining prime implicants/implicates, Variable entered K-maps.


Class #

Chapter Title / Reference Literature

Topics to be covered % of Portions covered

Reference Chapter

Cumulative

22-31

UNIT 3 Combinational Logic Modules and their applications T1: 5.1.1, 5.1.2, 5.2, 5.3, 5.4, 5.5, 5.6, 5.7, 5.8, 5.9, 5.10

Binary adders and subtractor, carry look ahead adder, Decimal adder. Comparators, Decoders, Encoders, multiplexers,Realization using Mux and Mux trees, Programmable logic devices, PROMS, PAL, PLA Devices.

19% 57%

32-41

UNIT 4 Sequential Logic systems T1: 6.1, 6.2, 6.3, 6.4, 6.5, 6.6, 6.7, 6.8, 6.9, 6.9.1, 6.9.2,7.1,7.2

The basic Bistable element, Flip

Flops-Truth table, circuit,

characteristic equations, state

equations, state transition diagrams Latches, Timing considerations, Master-slave Flip-flops (pulse triggered), Edge triggered Flip-flops, characteristic equations , Registers, Counters, Design of Synchronous counters. & Asynchronous counters,

Structure and operation of clocked

synchronous sequential, network,

Analysis of clocked synchronous

sequential networks.

20% 77%

42-52

UNIT 5 Logic Families

T1 : A.7, A.8, A.9, A.10, A.11

Introduction to different logic

families; Operational characteristics

of BJT in saturation and cut-off

regions; Operational characteristics

of MOSFET as switch; TTL inverter

- circuit description and operation;

CMOS inverter - circuit description

and operation, Structure and

operations of TTL and CMOS gates;

Electrical characteristics of logic

gates – logic levels and noise

margins, fan-out, propagation delay,

transition time, power consumption

and power-delay product.

23% 100%


Literature:

Book Type Code Title & Author Publication Info

Edition Publisher Year

Text

T1 Digital Principles and Design by Donald D. Givone

-- TATA McGraw Hill 2007

T2

Logic and Computer design

fundamentals by Mano and

Kim,

2nd Pearson

publication 2001

Reference R1 Digital logic applications and design by John M. Yarbrough

-- Thomson

Brookes/Cole 2001


11TE207: DIGITAL ELECTRONICS CIRCUITS LAB (0-0-1-1.5)

Subject Code: 11 TE 207 Faculty: Ms. MP

CYCLE OF EXPERIMENTS

CYCLE - I

1. *Simplification and realization of Boolean expressions using basic and universal logic gates.

2. Realization of parallel adder/subtractor using 7483 chip.

3. BCD to Excess-3 code conversion and vice versa 4. Realization of Binary to Gray code conversion and vice versa

CYCLE - II

5. *MUX/DEMUX, use of 74153, 74139 for arithmetic circuits and code converter.

6. Realization of one/two bit comparator and study of 7485 magnitude comparator.

7. Use of (a) decoder chip to drive LED display and (b) Priority encoder.

8. *Truth table verification of flip flops: (i) JK master slave (ii) T Type and (iii) D type.

CYCLE - III

9. *Realization of 3 bit counters as a sequential circuit and mod-N counter design (7476, 7490, 74192, 74193).

10. *Shift left; Shift right, SIPO, SISO, PISO, PIPO operations using 7495S.

11 Design and testing of Ring counter/Johnson counter

12. Design and testing of Sequence generator

* Experiments to be done using PSPICE also

******


QUESTION BANK

Unit 1: Boolean Algebra & Combinational Networks 1. What are basic and universal gates? Give example? 2. Realize AND, OR, NOT, NOR and X-OR gate using NAND gates only. 3. Realize AND, OR, NOT, NAND and X-OR gate using NOR gates only. 4. Explain the following:

(i) The Sum-of product expressions (ii) Product of sum expression (iii) De-Morgan’s Theorem. 5. Simplify using Boolean Theorems: (i) (A+B)(C+D) (ii)

(A+B+C+D) (ABCD) (iii) BCED + B’C+BCD’ (iv) (A+AB’+CD)’ (v) B’ (B+C) +D’+CD (vi) {A [B+C(A’+B)]}

6. Using the Theorems of Boolean Algebra, simplify the following: B)CDAA()DCD(BA ''''

)DCA()DB()CB(CAB '''''

7. Prove that if 0yzxw '' , Then zywzxxzwx)zw(ywx '''''''

8. Convert he following expression to sum of product form: (i) )UY()ZX( (ii) )UYZXY()UZZXY(

9. Prove the following Boolean identity by exhaustion: AB+BC+A’C=AB+A’C 10. Given the function : T(w,x,y,z) )15,11,9,8,7,6()13,5,3,2,1( d

(i) Find a minimal sum of product expression (ii) Find a minimal product of sum expression

11. Implement the above expressions using NAND and NOR gates respectively 12. Simplify the following expressions:

(i) )BA()BAA()BCABA()CA()BA( '''''''

(ii) ABDABDBAACDCDDACBA '''''''''

(iii) DBCDBCBCDACDBDACDCBA ''''''''''' 13. State Shannon’s expansion theorem and using this theorem expand the following expression

Cabf

14. Solve the following expression using Boolean algebra technique

BACAABAF )(

15. (a) Explain SOP and POS forms of representing switching function. Assume 3-var case and give examples. (b) Prove the following using Boolean theorems of by using K-map: (i) a + a’b = a + b (ii) ab + a’c’ + ab’c (ab + c) = 1

(c) A staircase light is controlled by two switches, one at the top of the stairs and another at bottom of stairs. (i) Develop a truth table for realizing the above logic. (ii) Find the SOP form of switching function for control of staircase light. (iii) Realize the function using basic gates.

Assignment Questions: 1. Simplify the following using Boolean expression

2. F(x,y,z)=(2,3,6,7)

3. F(A,B,C,D)=(7,13,14,15) 4. xy + x ‘y ‘z’+x ‘ y z ‘ 5. Implement the following function with NAND or NOR gates. Use only four gates. F=w1xz +w1yz + x1yz1 + wxy1z


Unit 2: Simplification of Boolean expression

1. Simplify using k-map: F=(0,1,2,8,10,11,14,15) 2. Simplify using k-map: (i) 7,5,3,1,0 (ii) )14,13,11,9,8,7,6,5,1(

(iii) )15,11,9,8,7,6,4,3,2,0( (IV) )13,11,9,8,7,5,2,1,0(

(v) )14,13,11,7()10,9,8,6,4,3,2,1,0(

(vi) )27,15,14,10,9,7,5,0( and realize using logic gates.

3. Simplify the following functions using K-Map:

'''''' BAACCDBDADC'BA)D,C,B,A(f

)14,13,11,10,8,7,5,4,2,1()D,C,B,A(f

4. Find a minimum two-level logic circuit for the function: )4,2()14,13,12,6,5,1(),,,( dzyxwf using Quine-Mc-Cluskey method:

5. Simplify using Quine Mc-Cluskey method: )15,13,,8,7,6,3,2(

)12,10,9,8()14,13,7,6,3,2,1,0(

)27,26,25,23,22,21,20,19,18,15,14,13,12,11,10,7,6,5,4,3,1(

using both decimal and binary numbers. Also solve using VEM technique. 6. Using Quine Mc Clusky tabulation method, obtain the set of prime implicants for the function.

)13,8,2()15,14,12,10,9,5,4,1,0(),,,( dcbaf

and hence obtain the minimal form of the given function employing decimal representation. 7. Simplify the following using VEM technique. Reduce 4 variables to 3 variables

DABCABCDDBCACDBADCBADCBADCBADCBAY 8. i) draw the logic diagram using AOI logic for minimal sum. Obtain minimal sum using K-map ii) Find all the prime implicants and essential prime implicants.

ASSIGNMENT:

1. The following Boolean expression: BE + B1DE1 is a simplified version of the expression: A1BE + BCDE + BC1D1E + A1B1DE1+ B1C1DE1 Are there any don’t care conditions? If so, what are they?

2. Obtain the simplified expressions in product of sums:

F(x,y,z)=(0,1,4,5)

F(A,B,C,D)=(0,1,2,3,4,10,11)

F(w,x,y,z)=(1,3,5,7,13,15) 3 Simplify the following function using Quine Mc-Cluskey and Vem technique:

F(w,x,y,z)=(2,3,12,13,14,15)

F(A,B,C,D,E,F)=(6,9,13,18,19,25,27,29,41,45,57,61)

F(W,X,Y,Z)=(1,4,6,7,8,9,10,11,15)


Unit 3: Combinational Logic Modules and their applications Design a full adder using (i) Basic gates (ii) Using NAND gates (iii) Using 2 half adders 1. Realize a full adder using minimum number of 2-input NAND gates. Write the relevant expressions, truth-table

and logic diagram. 2. Design a full subtractor using (i) Using NAND gates (ii) Using 2 half adders. 3. What is Carry Look Ahead adder? Explain 4. Design a 4-bit Carry Look Ahead Adder? Briefly explain the

working of a (i) Serial adder and (ii) Parallel adder to add two decimal numbers expressed in BCD. List their relative merits.

5. Show how 7483 can be used for 4-bit addition and 4-bit subtraction using suitable examples

6. Construct the adder with two-4 bit binary adders and an inverter. 7. Implement the 4-bit parallel adder 74LS83 to perform both addition and subtraction. Give out the logic behind

the implementation with example 8. Realize a single bit digital comparator using gates and explain its working? 9. Design and realize a 2-bit magnitude comparator circuit? 10. Design a circuit that compares two-4 bit numbers, A and B, to check if they are equal. The circuit has one

output X, so that X=1 if A=B, X=0 if A B. 11. Design a combinational circuit that accepts 2 unsigned 4-bit binary numbers and provides 3 outputs; one of

them is A3A1A2A0: word A and the other is B3B2B1B0: Word B. Outputs are active depending on whether A=B or A>B or A<B. Draw the logic diagram.

12. Show how to realize an 8-bit magnitude comparator using 7485. 13. Implement the full adder with multiplexers? 14. Realize a 4:1 multiplexer using NAND gates only and briefly explain its working? 15. Show how IC 74151 multiplexer can be used to implement the Boolean Function:

F(A,B,C,D)=(0,1,3,4,8,9,15). 16. Design a full adder using a 4 x 1 Mux? 17. Design a 32 x 1 Mux using a 8 x 1 Mux? 18. Realize using 16:1 multiplexer the function?

19. f(D,C,B,A)=m0, m3, m6, m9, m12, m15. 20. Write short notes on Demultiplexer. 21. Realize a single bit full adder using demultiplexer and briefly explain. 22. Design a Binary to Gray decoder using demultiplexer. 23. Design a Gray to binary decoder using demultiplexer. 24. Design a full adder using a 3 x 8 decoder. 25. Design a combinational circuit for 3 bit even-parity generator and implement it using NAND gates only. 26. a) Design BCD to Excess 3 code converter using NOR gates only.

b) What is race around condition? Explain how it is eliminated using J-K master-slave flip-flop. 27. Implement the following multi Boolean function using 3 x 4 x 2 PLA PLD

)7,5,3(),,(

)5,3,1,0(),,(

0122

0121

maaaf

andmaaaf

28. Implement the following multi-Boolean function using PROM PLD

1012

1011

),(

0),(

xxxf

xxxxf

29. (a) Realize the following functions using NOR gates : (i) f(a ,b) = a’b’ i. f(a, b, c, d) = ad’(b + c’) + a’d.


b. From basic principles, develop expressions for the Difference and Borrow of a Full Subtractor. Simplify the expressions and realize using binary gates.

31 Differentiate between complement subtarctors. (i) Half and Full adder. (ii) 1’s and 2’s complement subtractors.

32 Describe a 4-bit binary parallel adder. Work out the maximum speed of operation pf the circuit. Show how a parallel adder can be modified to work as adder/subtractor.

Assignment 1. Show how to realize a 8-bit parallel adder using 7483. 2. Design a combinational circuit that accepts inputs as 3-bit numbers and generates an output binary number

equal to square of the input number. Realize the logic circuit using only NAND gates.

3. Design a decimal adder for two digits represented in the Excess-3 code. Show that the correction after adding the two digits with a four bit binary adder is as follows:

4. The output carry is equal to the carry out of the binary adder. 5. If output carry=1, add 0011. 6. If output carry=0, add 1101. 7. Design a Full subtractor using a 3 x 8 decoder. 8. Write about PLA, PLD, PAL, PROMs. 9. Implement the four Boolean function listed using three half-adder circuits

a. D=A B C b. E= A’ BC +AB’C c. F=ABC’ + (A’ +B’)C d. G = ABC

Unit 4: Sequential Logic systems 1. What are sequential circuits? Give examples. 2. What is a NAND latch? Show how a NAND latch can be used in eliminating contact debouncing. 3. What is a clock SR Flip flop? Assuming a suitable input wave form explain its behavior. 4. Explain the operating of JK Flip-flop. Assume a suitable I/P wave and draw timing diagrams to explain the

behavior of a circuit. 5. What are preset & clear inputs? What they are required in sequential circuits? 6. What is race around in flip-flops? How do you eliminate it? 7. Explain the operation of MSJK flip-flop with suitable I/P waveforms. 8. Explain the working of 5-bit shift register with timing diagram. Also explain SISO, PISO, PIPO, SIPO

operations. 9. Explain the working of a Bi-directional shift registers 10. What is a ring counter? Explain its working with the help of timing diagrams. 11. Explain the state diagram technique for realization of 4 bit shift right register 12. What is mode K counter or divide by K counter? Design a mod 7, mod 6 counters? 13. Explain how a BCD counter works with a help of suitable and logic diagram? 14. State and explain two applications of shift register. 15. Design mod-4 ripple up counter with initial state is (011)2. Draw timing diagram for the same. 16. Compare Moore and mealy models. 17. Design a MOD – 4 synchronous down counter using JK flip flops and implement it. 18. Derive transition table. State table and state diagram for Moore sequential circuit shown in below figure.

KA

JA

QA

QA

KB

JB

QB

QB

CLK

X

Q.18 Logic Design


(19) (a) Show how J-K flip-flop can be realized using NAND gates. Represent the J-K flip-flop in a truth table and show that Qn+1 = JnQ’n and K’nQn. (b) What is race around? Discuss how it is avoided in J-K master-slave flip-flop. (20) Design a 3-bit up counter using J-K flip-flop as basic building blocks. Show how it can be modified to work as UP/DOWN counter.

Assignment 1. What is a twisted ring counter? Explain its working with the help of a neat circuit and timing diagram. 2. Explain the state diagram technique for realization of 3 bit ripple counter 3. Design a ripple counter circuit using 7493 that will flash an LED for 40 msec and off for 20 msec. (Assume that

a 100Hz clock is available). Design the appropriate value of current limiting resistor also. 4. How does D and T flip flop work? 5. Explain the working of skipping counter and design a counter, which counts through the following sequence 2-3-4-5-6-7-2---? 6. Construct the transition table for the binary state assignment (000,001,010,011,100,----) 7. Design a synchronous mod 8 counter .use a binary state assignment. Realize the counter using D, JK, T & RS

flip-flops.

Unit 5: Logic Families 1. Define (i) Fan-in (ii) Fan-out (iii) Noise Margin (iv) Propagation Delay Power dissipation (vi) Speed power product. What are their significance? 2. Explain the operation of Basic TTL NAND gate circuit with relevant diagrams. Also briefly describe the WIRED-

AND configuration? 3. Explain the totem-pole output configuration and wired-AND operation of logic gates.

4. With circuit diagram briefly explain the working and the use of (i) open collector IC’s (ii) Tristate Buffer (iii)

schottky TTL 5. What are the different types of output states available in TTL?


6. Write short notes on: (i) Comparison of CMOS & NMOS logic

(ii) Tri-state logic (iii) Bus drivers 7. How CMOS is preferred to TTL, give reasons. 8. Briefly explain with suitable circuit diagram, the working of 2 input medium speed TTL NAND gate with totem

pole output and 2 input Schottky TTL NAND gate with totem pole output. 9. Briefly explain, with suitable circuit diagram, the working of (i) NMOS NAND gate, NOR gate & Inverter and (ii)

CMOS NAND gate. List their performance, merits and demerits. 10. Explain the current sourcing and current sinking action in transistor logic circuit. 11. Briefly explain with suitable circuit, CMOS NAND, NOR & NOT gate. 12. Explain a two input NAND gate TTL with totem pole output with a neat circuit diagram. 13. Explain the working of a CMOS, NOT, NAND and NOR gates.

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Digital Electronic Circuits -Lesson plan and QB.pdf