Development of an embedded system for networking applications · An embedded system is a system where diﬀerent areas work together; it integrates hardware circuitry with software

POLITECNICO DI TORINO

Faculty of EngineeringMaster of Science in Electronic Engineering

Master Thesis

Development of an embedded system fornetworking applications

Advisor:prof. Danilo Demarchi

Candidate:Francesco Gramazio

Company tutorTelsy SPA

Ing. Fabrizio Vacca

December 2018

Summary

Nowadays, people in the world get in touch with about 100 embedded systems per day,that not only have the aim to realize specific functions but also are a way to introduceinnovations. According to the World Trade Statistics, in 2009 the 98% of all programmabledevices were embedded, and if in 2010 there were about 16 billion of embedded systems,in 2020 it is estimated that this number will increase, astonishingly reaching 40 billionunits. With this capillary spreading of devices, privacy and information are in constantdanger: according to Cybercrime Report 2016, cyber-attacks grow of the 350% every year.It is of the foremost importance, therefore, to secure communications through embeddedsystems, especially for companies (and in particular military companies). National defenceagencies must deal with confidential information, thus they have to develop solid devicesfor security: clear data has to be encrypted prior to the transmission and decrypted afterthe reception, to ensure that every information that comes out into the external world issafe, with no possibilities to externally monitor the traffic network and to go back to theoriginal clear information.

In this work, we propose the design of a cipher IP board called ENA (Embedded Net-worked Appliance), aimed to ensure a complete security of IP traffic exchanged on strategicnetworks for military applications, in order to guarantee a safe exchange of informationfrom one host to another. The device is intended to be installed both at the transmitterand the receiver side, to hide information during the transmission. The Encrypting IP boxis available for both optical and copper-based wired Ethernet Interfaces. It is designed forreal time applications; the device can be used for VoIP transmissions and for time-sensitiveapplications, for this reason the UDP protocol is used for transmission. The device is com-posed by two different parts: a carrier board, that contains components to provide powerto the whole system, and the main module, which is a proprietary company board. Themain focus of the study is the design of the specific carrier board, with proper interfaces,for the realization of the IP cipher, and the development of the microprocessor and mi-crocontroller software, to execute the different tasks (e.g. download of the FPGA bitfileinto the Flash Memory, configuration of the FPGA and the microprocessor application forEthernet frame manipulation and encryption).

At the end of the design the system is tested with an external traffic analyser to analysethe throughput, and the working conditions are specified. The minimum frame size thatallows a correct encrypting of the information through Ethernet has been discovered to

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be 1280byte. Thanks to this work, it has been possible to highlight the limits of themicroprocessor and, although with the current restrictions the ENA could not be suitablefor being an enterprise product, it represents a good proof of concept of how deeply militarycompanies have to deal with the topic of security and confidentiality.

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Contents

Summary i

1 Introduction 1

2 System overview 32.1 Embedded Systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2.1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32.1.2 Embedded Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . 42.1.3 Embedded Software . . . . . . . . . . . . . . . . . . . . . . . . . . . 62.1.4 Types of Embedded Systems . . . . . . . . . . . . . . . . . . . . . . 7

2.2 System Architecture of the designed embedded system . . . . . . . . . . . . 92.2.1 Microcontroller STM32F756 IGK6 . . . . . . . . . . . . . . . . . . . 92.2.2 QSPI - NOR Flash Memory . . . . . . . . . . . . . . . . . . . . . . . 182.2.3 IMX6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.2.4 Cyclone IV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3 System Architecture 223.1 Carrier Board Design and Custom Module Structure . . . . . . . . . . . . . 24

3.1.1 Carrier Board Design . . . . . . . . . . . . . . . . . . . . . . . . . . 243.1.2 The ENA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2 STM Microcontroller Software . . . . . . . . . . . . . . . . . . . . . . . . . 353.2.1 Initialization TOKEN . . . . . . . . . . . . . . . . . . . . . . . . . . 353.2.2 LEDs 1 & 2 ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363.2.3 Communication TOKEN . . . . . . . . . . . . . . . . . . . . . . . . 36

3.3 IMX6 Microprocessor Software . . . . . . . . . . . . . . . . . . . . . . . . . 413.3.1 Kernel IP Forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . 413.3.2 User Space application for IP Forward . . . . . . . . . . . . . . . . . 423.3.3 Encryption and Decryption of Ethernet Packets . . . . . . . . . . . . 42

4 Throughput Tests 514.1 Description of the test devices . . . . . . . . . . . . . . . . . . . . . . . . . . 51

4.1.1 Ethernet interface hardware architecture of ENA . . . . . . . . . . . 514.1.2 Ethernet interface hardware architecture of Smarc ROJ . . . . . . . 514.1.3 Software comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

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4.2 Throughput performance of Kernel IP Forwarding . . . . . . . . . . . . . . 534.2.1 General Purpose Throughput test . . . . . . . . . . . . . . . . . . . 544.2.2 ROJ eNUC Throughput test . . . . . . . . . . . . . . . . . . . . . . 554.2.3 ENA Throughput test . . . . . . . . . . . . . . . . . . . . . . . . . . 574.2.4 Performance Conclusions . . . . . . . . . . . . . . . . . . . . . . . . 58

4.3 Throughput performance with application IP Forwarding . . . . . . . . . . 604.4 Throughput performance with Encrypting and Decrypting application . . . 614.5 Comparison between ENA with IP Forwarding application and Encrypt-

ing/Decrypting Application . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

5 Conclusion 68

A Open System Interconnection/International Standard Organization 70

B IP-Internet Protocol 72B.1 Overview and main characteristics . . . . . . . . . . . . . . . . . . . . . . . 72B.2 IPv4 packet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

C Secure Hash Algorithm 75

D Networking 76

References 78

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List of Figures

2.1 Global Embedded System Market Revenue in USD Billion [5] . . . . . . . . 42.2 General scheme of an Embedded System . . . . . . . . . . . . . . . . . . . . 72.3 System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102.4 Flash memory interface connection inside microcontroller [21] . . . . . . . . 122.5 The scheme of the QuadSPI interface in STM microcontroller [21] . . . . . 132.6 Complete command that is send to the Flash Memory . . . . . . . . . . . . 132.7 FMC blocks diagram [21] . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152.8 SRAM asynchronous read access timing in extended mode [21] . . . . . . . 162.9 SRAM asynchronous write access timing in extended mode [21] . . . . . . . 172.10 Synchronous Muxed A/D write access [20] . . . . . . . . . . . . . . . . . . . 192.11 Asynchronous Muxed A/D read access [20] . . . . . . . . . . . . . . . . . . 192.12 Configuration Cycle Waveform [1] . . . . . . . . . . . . . . . . . . . . . . . 21

3.1 General Design Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.2 Carrier Board Schematic: Express Connector Page . . . . . . . . . . . . . . 263.3 Carrier Board Schematic: SFP Black Optical Module Page . . . . . . . . . . 273.4 Carrier Board Schematic: SFP Red Optical Module Page . . . . . . . . . . 283.5 Carrier Board Schematic: Main Power Page . . . . . . . . . . . . . . . . . . 293.6 Block Diagram of the main board . . . . . . . . . . . . . . . . . . . . . . . . 333.7 Flow Chart of STM software . . . . . . . . . . . . . . . . . . . . . . . . . . 373.8 Flow Chart for QSPI writing process Part I . . . . . . . . . . . . . . . . . . 433.9 Flow Chart for QSPI writing process Part II . . . . . . . . . . . . . . . . . 443.10 Flow Chart for FPGA Configuration Part I . . . . . . . . . . . . . . . . . . 453.11 Flow Chart for FPGA Configuration Part II . . . . . . . . . . . . . . . . . . 463.12 Flow Chart for FPGA Configuration Part III . . . . . . . . . . . . . . . . . 473.13 Flow Chart for FPGA Configuration Part IV . . . . . . . . . . . . . . . . . 483.14 Flow Chart for FPGA Configuration Part V . . . . . . . . . . . . . . . . . . 493.15 Network configuration of the Devices . . . . . . . . . . . . . . . . . . . . . . 50

4.1 Ethernet interface architecture of ENA . . . . . . . . . . . . . . . . . . . . . 524.2 Ethernet interface architecture of Smarc ROJ . . . . . . . . . . . . . . . . . 534.3 Test System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544.4 General Purpose System Throughput Test . . . . . . . . . . . . . . . . . . . 554.5 Packets vs Size Graph of General Purpose System . . . . . . . . . . . . . . 55

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4.6 ROJ Smarc Throughput Test . . . . . . . . . . . . . . . . . . . . . . . . . . 574.7 Packets vs Size Graph of ROJ Smarc . . . . . . . . . . . . . . . . . . . . . . 574.8 ENA Throughput Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584.9 Packets vs Size Graph of ENA . . . . . . . . . . . . . . . . . . . . . . . . . 594.10 Comparison Throughput test . . . . . . . . . . . . . . . . . . . . . . . . . . 604.11 Comparison Packets vs Size Graph . . . . . . . . . . . . . . . . . . . . . . . 614.12 Throughput Test of ENA with IP forwarding application . . . . . . . . . . . 624.13 Packets vs Size Graph of ENA with IP forwarding application . . . . . . . . 624.14 Throughput Test of ENA with Encrypting and Decrypting application . . . 644.15 Packets vs Size Graph of ENA with Encrypting and Decrypting application 644.16 Sweep Throughput Test of ENA with Encrypting and Decrypting application 664.17 Comparison between Throughput test of IP Forwarding Application and

Encrypting Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674.18 Zoom of comparison between Throughput test of IP Forwarding Application

and Encrypting Application . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

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List of Tables

2.1 Embedded Flash memory organization . . . . . . . . . . . . . . . . . . . . . 12

3.1 COM Express A-pins I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303.2 COM Express A-pins II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.3 COM Express B-Pins I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.4 COM Express B-Pins II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323.5 PinOut of the Interface between STM and FPGA . . . . . . . . . . . . . . . 343.6 PinOut of the Interface between STM and IMX6 . . . . . . . . . . . . . . . 343.7 PinOut of STM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.8 Pinout of FPGA Cyclone IV . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.1 Data of Throughput of General Porpose System in Mbps . . . . . . . . . . . 564.2 Number of frames per second of General Porpose System . . . . . . . . . . 564.3 Data of Throughput of ROJ Smarc in Mbps . . . . . . . . . . . . . . . . . . 564.4 Number of frames per second of ROJ Smarc . . . . . . . . . . . . . . . . . . 584.5 Data of Throughput of ENA in Mbps . . . . . . . . . . . . . . . . . . . . . 594.6 Number of frames per second of ENA . . . . . . . . . . . . . . . . . . . . . 594.7 Data of Throughput of ENA with IP forwarding application in Mbps . . . . 634.8 Number of frames per second of ENA with IP forwarding application . . . . 634.9 Data of Throughput of ENA with Encrypting and Decrypting application

in Mbps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654.10 Number of frames per second of ENA with encrypting and decrypting ap-

plication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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Chapter 1

Introduction

The purpose of this thesis is the design of an Ecrypting IP Box. The scope of an Ecrypt-ing box is to ensure a complete security of IP traffic exchanged on strategic networks formilitary applications.Nowadays the privacy and the informations are in constant danger; according to Cyber-crime Report 2016 [4], the cyber attacks annually grow of 350%. So it is evident how thecompanies and in particular military companies have to develop solid devices for security.

The scope of this device is to guarantee secure exchanging of information from one hostto another host. The clear data before being transmitted has to be encrypted to ensurethat each information that comes out to the external world, is safe with no possibility tomonitor externally the traffic network and to go back to the original clear information. Atthe other side another Encrypting IP Box has to be install to decrypt the informationsthat arrive. The Encrypting IP box is available both for optical and copper based wireEthernet Interfaces. It is designed for real time applications; so the device could be usefor Voip transmissions and for time-sensitive applications; for this reason UDP protocol isused for the transmissions (appendix D).

The thesis is divided into five chapters: in the first chapter a description is given re-lated to the problem of security, the use of cipher equipment and the summery of eachchapter. In the second chapter a detail description of the embedded system world is madeand the reason why, nowadays, the embedded systems are dominating the entire consumerelectronics and non-consumer landscape. Moreover, a detailed description of the differentembedded systems that are present today and the main components that form a completeembedded system is given. A brief overview of the design embedded system (ENA - Em-bedded Networked appliance) is also present and where it is positioned into the differentfunctional categories of embedded systems. The third chapter deals with the main projectsteps for the design of the Encrypting IP Box and a detailed description of each step ispresent. In the fourth chapter, the Ethernet interfaces of the design device and of a simi-lar commercial device are analysed initially, then theoretical performance and graphs aredescribed to perform critical analysis on the device. Then performance tests are carried

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1 – Introduction

out to measure the throughput of the device; comparisons are performed to comment thedifferent results. In the fifth chapter a summary of the entire work is performed and con-clusions are made.Thanks to this work it has been possible to analyze the performance of the device and ithas been possible to decree the final specifications and if it would be possible a future useof the device for enterprise realizations.

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Chapter 2

System overview

2.1 Embedded Systems

2.1.1 Introduction

Nowadays, most processing systems are not personal computers, but they are devices thatcommunicate with the external environment; they have a specific function and, in spite ofwhat we think, in most cases, they don’t require to open programs or to have interfaceswith mouse and keyboard. These systems are called embedded and they dominate the mar-ket all over the world even if they are not so known as the general purpose systems. Atthe moment, it is considered that a person in the world gets in touch daily with about 100embedded systems. It isn’t a surprise if it is thought that a lot of devices have almost onemicroprocessor like smartphone, cash machine, washing machine, dishwasher, credit card,ink-jet printer, scanner, up to the automotive domain where cars today contain dozensof embedded systems, such as transmission control, cruise control, etc; any kind of devicethat runs on electric power already has a computing system or will soon have a computingsystem embedded on it.The embedded systems not only have the aim to realize specific functions but they arealso a way to introduce new innovations. In history we have witnessed the advent of dif-ferent industrial revolutions. Starting from the 60s, a second industrial revolution brokeout which led to the development and diffusion of digital technologies. We have movedfrom big computers, that occupied entire rooms, to personal computers, to today’s hugespread of laptops and smartphones, helped by the possibility to connect all over the worldthrough the network and the internet. Of course this diffusion has a heavy impact onthe embedded system market which has a market share of more than 90% of the totalelectronic sector. According to the World Trade Statistics, in 2009 98% of programmabledevices were embedded and if in 2010 there were about 16 billion embedded systems, in2020 it is estimated that 40 billion units will be reached. [2]According to an article of Zion Research titled "Embedded Systems Market", the globaldemand of embedded systems market was valued USD 159.00 billion in 2015 and is ex-pected to become 225.34 billion by the end of 2021 (figure 2.1).This market growth is driven also by the huge demand, in the last years, of medical

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2 – System overview

Figure 2.1: Global Embedded System Market Revenue in USD Billion [5]

devices such as ECG embedded systems, heart rate monitors and glucose level monitors.The exponential growth of embedded systems, the advent of the internet and its enormousdevelopment, has allowed the growth of what is known as the Internet of Things. It is anew era where not only people are connected to the network through PCs, smartphonesand tablets but also through any kind of object.A question that could arise spontaneously is why this huge diffusion of embedded systemscompared to that general purpose systems. The answer is easy: the main benefits of em-bedded systems is the low power consumption, the very small size and low cost per-unit,due to the possibility to reduce the complexity of the circuits that have to perform fewdedicated functions and the possibility to integrated it in every object that surround usdaily.

An embedded system is a system where different areas work together; it integrateshardware circuitry with software programming techniques. The software used in embed-ded system is a set of instructions that perform specific tasks. A general scheme of anembedded system is represented in figure 2.2.The core of an embedded system is the electronic hardware that is on the Printed CircuitBoard. Broadly, the typical structure of an embedded system consists of a device thatinteracts with the external world through Input/Output interfaces that can be A/D Con-verters(which convert an analog physical signal sent, for instance, by a sensor to a digitalsignal) or UARTs interface or infrared ports. All the information is processed in a CentralProcessing Unit and is stored in a memory.

2.1.2 Embedded Hardware

Hardware is fundamental, it is the physical core that contains different particular compo-nents, depending on the requirement and specification. Some of them are:

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• General Purpose Microprocessors: They are single chip devices that contain an Arith-metic & Logic Unit, a Program Counter, a Stack Pointer(SP), registers, interruptscircuits, different clocks all integrated on a single chip. It is necessary to add amemory(ROM and RAM), memory decoder, oscillators, serial and parallel ports ex-ternally. It is used to perform a huge amount of computations and to provide manyapplications and tasks that required a great complexity compared to a microcon-troller. Summing up it has a high cost, a high power consumption, a large memorysize, flash and cache, external bus interface with a memory management unit tohandle a huge amount of read/write operations and a greater memory usage.

• Microcontrollers: It is a computer system-on-chip; so it contains an integrated pro-cessor, a memory, a small amount of RAM, peripheral devices(timers, DAC, DACand serial communication devices), all on one chip. Preferably used in small appli-cations with precise calculation. So it is a very compact and low power chip. Ofcourse, it has physical limits like a limited amount of ram , less flexibility due to itsnot expandability, less reliable and low performance. Nevertheless it is low cost, lowpower and very small size. A microcontroller also provides a set of pins that allowthe use of sensors, actuators and transfer of data to other devices.

• DSPs/ASIP: An Application Specific Instruction set Processor (ASIP) is used forspecific applications like digital-signal processing, telecommunications and embeddedcontrol. The advantage of the ASIP in an embedded system is the flexibility notwith-standing good performance, power and size. A Digital-Signal Processor(DSP) is aclass of ASIP; it is a single chip designed to have very high performance, numericallyintensive tasks (like multiply, add, shift).

• ASICs: Application Specific Integrated Circuits are designed for a specific applicationfor example Digital to Audio Converter or Mpeg2 Decoder. They have a very highperformance but a very high cost and they are not flexible.

• FPGA/CPLDs: Field Programmable Gate Array is a fully programmable customizedchip. The big advantage is the cost and reliability. It is a bidimensional array oflogic blocks and flip-flops that allow the user to configure different interconnectionsbetween blocks. It has the possibility to design a processor, a ROM, a RAM, a DSPand any kind of block onto a single chip.There are different types of FPGA according to its physical structure:

– Reprogrammable FPGA(SRAM Based) that can be reprogrammed endlesslywhen need. It is very flexible but has a higher cost.

– One time programmable FPGA based on antifuse: it can be reprogrammed onlyonce. Usually used for particular applications like aerospace, satellite and veryhigh security app.

The Complex Programmable Logic Devices differs from FPGA mainly due to itsarchitecture. It consists of more programmable sum of product logic arrays withsmall numbers of clocked registers. So they are less flexible but have the advantage

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of predictable timing delays and have higher logic interconnection ratio. DifferentlyThe FPGA architecture is dominated by different interconnections. A CPLD containsan embedded flash which stores the configuration, whereas an FPGA has to beconfigured each time it is switched on.

• System on Chip (SoC): It contains a CPU, Peripheral devices, Power ManagementCircuits, Communicaion interfaces(UART, SPI, I2C) on a single Integrated Circuit.It can include different programmable processors. For exampe a SoC can contain anARM Cortex+ Custom GPU + DSP + FPGA.

• Input Devices: They take input from the outside world and route the signal into thedifferent blocks. Inputs can be different types of sensors, switches, etc.

• Output Devices: They are the result of the different operations that occur in themicrocontroller. Different examples of outputs can be LED, LCD, Actuators, Mo-tors,Relays, etc.

• Bus Controllers: They handle all the communications, and the transfers among thedifferent components inside the embedded system. Some examples of bus controllersare Serial Buses (SPI, I2C,etc) RS232, RS485 and Universal Serial Buses.

• Memories: They are used to store data. In an embedded system a Non-Volatile RAM,Volatile RAM, DRAM,etc are usually present.

It is possible to compare the structure in figure 2.2 with the well-known DesktopComputer. In an embedded system the primary memory, central processing unit, and allthe peripheral components are built on a single chip that is called Microcontrollers. Onthe other hand a desktop computer has to handle larger data dimension compared to anembedded system. Personal computer has to elaborate huge amounts of data and transferit faster between CPU and memory, CPU and Input/Output devices. To store such a sohuge amount of information, secondary memories like Hard Disks or CD-Rom are neededmoreover it implements different methods like direct memory access or multi-level cachethat are not necessary in embedded system.

2.1.3 Embedded Software

Software is essential for any type of embedded systems. It provides all the functionality tothe system. Due to the different nature of the tasks that an embedded system has to per-form, different languages are used; for example one language can be used to obtain a goodand precise control-dominated application but isn’t the best choice for signal processingapplications or for network interfaces applications. Four types of different languages areemployed:

• Software languages: use instructions to describe the sequences to be executed. Thereare different types of software languages that depend on the abstract level: assemblyand high level. An assembly language uses a set of instruction written in symbolicform and perform very simple operations on registers and memories. High level

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Figure 2.2: General scheme of an Embedded System

languages like C, C++, ADA, etc are used to construct more complex functions,loops, arrays etc.

• Hardware languages: Verilog and VHDL(Very high speed integrated circuits Hard-ware Description Language) are the most popular hardware languages. They areused to describe the system with discrete event semantics and structural hierarchy.They are also used to simulate digital integrated circuits.

• Dataflow languages: They are used to describe systems with processes that runconcurrently and communicate through queues. They are composed by nodes, arcsand data. Typically they are used for signal processing applications.

• Hybrid languages: this language combines different type of other languages like Es-terel that combines hardware semantics with software language.

2.1.4 Types of Embedded Systems

Embedded systems can also be classified into different types based on performance ofthe microcontroller, functional requirements and performance. They are divided into fourdifferent functional categories:

• Stand alone embedded systems: This type of systems does not require an host likea PC but they work by themselves. They take the input from analog or digitalsources, they process the information, compute calculation and convert the data; in

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the end they give the results (outputs) that are used to control motors, switches orshow information onto the display. Examples of stand alone embedded systems are:digital cameras, microwave ovens, dish washes, videogame consoles, etc.

• Real time embedded systems: Real-time systems are systems that monitor and con-trol an external environment. Sensors, input interfaces and actuators are used toconnect the environment to the systems. So they have the ability to react when anevent happens; for example vehicle systems for cars, aircrafts, radio communications,are examples of real time embedded systems.

• Networked embedded systems: These systems handle different networks to access theresources. They can use LAN or internet to connect. The connection of course canbe wired or wireless. An example of networked embedded systems can be a homesecurity systems that is connected with protocol TCP/IP or any kind of system thatis connected to a web server and can be controlled by a web browser. The designedEncrypting IP Box system is a networked embedded system.

• Mobile embedded systems: they are used in smartphones, digital cameras, etc.

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2.2 System Architecture of the designed embedded system

In figure 2.3 a general block diagram of the designed system is represented. The hardwareembedded is composed by:

• Amicrocontroller(STM Family): It has the main role to download the bitfile of FPGAfrom the USB Cik-Token to the Flash Memory and every time the system is switchedon, it sends the bitfile to the FPGA. The microcontroller has also some Status LED.The user has the possibility to erase the entire internal microcontroller flash memoryand the external memory with a button. It has internal buses to communicate withthe microprocessor and the FPGA. It has also the task to switch on and off themicroprocessor and the FPGA.

• A microprocessor(IMX Family): It handles all the network communications with theoutside world. The packets that arrive through the Ethernet are processed insidethe microprocessor and are sent to the FPGA. It has two Ethernet interfaces thatmanage the network traffic; a USB OTG to connect the IMX to an external Computerand some Status LEDs. The microprocessor is programmed through an internalconnector.

• An FPGA: It has the task to process the internet packets, if they are not encodedthey are encrypted by the FPGA and viceversa. The FPGA has to be programmedeach time the system is switched on because the chosen FPGA is SRAM based.

• A flash Memory (QSPI): The Bitfile and other informations (like logs) are savedinside the flash memory.

• Inputs/Outputs devices: The main Inputs are the Cik-Token USB and the two SFPEthernet modules that have the role of both Input and Output. The different outputLEDs are used as status indicators that are used to inform the user about the statusof the machine. The system has a reset bottom to reset all the machine.

All the most important components used are analysed and a brief explanation of thefeatures are given focusing mainly on the most important characteristics that are used toachieve the technical project specifications.

2.2.1 Microcontroller STM32F756 IGK6

A microcontroller is a self-contained system. The big advantage of which is the flexibilityof use. In fact it is possible to change its work very easily only by programming it again.It contains peripherals, integrated memories, registers and a processor. In the designeddevice the microcontroller is the main component that powers on all the other devices andmanages all the other components. When the device is powered, only the mictrocontrolleris activated and it handles all the principal tasks that involve the other parts.The used microcontroller STM32F756 is based on ARM 32-bit Cortex -M7 RISC corewith a maximum frequency of 216 MHz. An ARM CPU is a RISC (Reduced Instruction

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Figure 2.3: System Block Diagram

Set Computing) machine and this is the first big difference from the Intel CPU (CISC);so the instructions in RISC CPU are smaller and allow to achieve a linear and simplerarchitecture compared to the CISC machine. RISC architectures are defined "load-store"because they allow to access the memory with simple specific instructions that are usedto read and write the data in the registers of the microprocessor.For its intrinsic simpler architecture, an ARM CPU has a low power consumption and abetter heat dissipation that are the main features required in portable devices like smart-phones, tablets and embedded systems.The Cortex-M family are ARM microprocessor cores that are designed for use as dedi-cated microcontroller chip. The Cortex-M7 core has a single floating point unit (SFPU)which supports all the data-processing instructions; it also implements a full set of DSPinstructions. It features a six-stage pipeline with branch speculation that tries to guesswhich way a branch will go before this is known; it improves the flow in the instructionpipeline to achieve high effective performance in the microprocessor.The STM32F756 embeds up to 1MB of Flash memory, 320kB of SRAM and has a

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FMC(Flexible External Memory Controller) with up to 32-bit data bus. The FMC in-cludes three memory controllers: NOR/PSRAM, NAND and Synchronous DRAM. In theproject the SRAM memory controller is used to program the integrated FPGA in theboard. It embeds, also, a Quad SPI memory interface that is used to interface the micro-controller with a QSPI flash memory that stores the bitfile of FPGA. In low-power, threedifferent modes can be used: sleep, stop and Standby modes. It offers also a true randomnumber hardware generator(RNG) and a cryptographic acceleration cell for AES 128, 192,256, HASH( SHA-1, SHA-2) and HMAC.In the following subsections the main features that are used in the design of the deviceare analized.

Embedded Flash memory(FLASH)

The Flash Memory interface manages Cortex-M7 and TCM accesses to the Flash mem-ory. The TCM(Tightly-coupled memory) has the purpose to provide low-latency memoryrespect the unpredictability of the cache. In fact the Tightly coupled memory has deter-ministic access time. The accesses through the cache are not deterministic since the datacan be in the cache(hit) or the data must be fetched from the main memory(miss). So theTCM provides a more efficient memory accesses. The Flash memory interface implementsthe erase and program Flash memory operations and it has the capacity up to 1Mbyte.Infigure 2.4 the flash memory interface connection inside the microcontroller is shown. Theembedded flash has three interfaces:

• 64-bits ITCM interface that is connected to the ITCM bus of Cortex and it is usedfor instruction and data read access; the write accesses is not supported on ITCM;

• 64-bits AHB interface that is connected th the AXI bus of Cortex through the AHBmatric and is used for code execution, read and write accesses. The AHB interfacesupports the DMA data transfer;

• 32-bits of AHB register that is used for control and status register accesses.

It is possible to see that after the flash interface, the flash bus is 256 bits.The flash memory has a main block that is divided into 4 sectors of 32 Kbytes, 1 sectorof 128 Kbytes and 3 sectors of 256 Kbytes. In table(2.1) all the information about thememory that is required to write correctly the program code and to place the code in theright part of the memory is summarized.

11


Figure 2.4: Flash memory interface connection inside microcontroller [21]

Table 2.1: Embedded Flash memory organization

Name Block base address Sector sizeSector 0 0x0800 0000 - 0x0800 7FFF 32 KBSector 1 0x0800 8000 - 0x0800 FFFF 32 KBSector 2 0x0801 0000 - 0x0801 7FFF 32 KBSector 3 0x0801 8000 - 0x0801 FFFF 32 KBSector 4 0x0802 0000 - 0x0803 FFFF 128 KBSector 5 0x0804 0000 - 0x0807 FFFF 256 KBSector 6 0x0808 0000 - 0x080B FFFF 256 KBSector 7 0x080C 0000 - 0x080F FFFF 256 KB

Quad SPI Interface

The STMmicrocontroller has a dedicated Quad SPI interface that is specialized to commu-nicate with Quad SPI Flash memories. The Quad SPI Flash Memories are Serial Memoriesthat use the SPI(Serial Peripheral Interface) with four wire for data. The main benefit ofusing QSPI is higher speed. Compared to the traditional SPI Flash interface that has four

12


lines (CLK, CS, MISO, MOSI), the QSPI uses 6 lines. From figure 2.5 the QSPI has:

• CLK - the clock output;

• DQ[3:0] - the serial I/O bidirectional signals that are used to transfer address, dataand command information;

• nCS - the chip select output;

Figure 2.5: The scheme of the QuadSPI interface in STM microcontroller [21]

The QSPI communicates with the Flash memory sending commands. In figure 2.6 theformat of a complete command is represented. Each command is formed at least by oneinstruction phase, the address phase, the alternate phase and the data phase.

• Instruction phase: an 8-bits of instruction is sent once every clock cycle on DQ0 linethat specifying the type of operation;

• Address phase : 4 bytes are sent to the Flash memory to select the address. The bitsare sent 4 bits every clock cycle using the 4 serial line DQ[0:3];

• Alternate phase: 1 to 4 bytes are sent to control the mode of operation.

• Data phase: during this phase any number of bytes can be sent or received from theFlash memory. The data is sent 4 bit every clock cycle using the four I/O pins.

Figure 2.6: Complete command that is send to the Flash Memory

13


Clock-out Capability

The microcontroller has the possibility to use one Pin(PC9) as special clock output. It ispossible to configure it with the prescaler the frequency clock of the pin. This pin is usedas clock for the FPGA.

14


Flexible memory controller (FMC)

The STM microcontroller has to write the bitfile, stored in the QSPI, in the FPGA. Beforethe read/write operations it is necessary to configure the memory controllers. The FMCconsists of four main blocks as shown in figure 2.7:

• AHB interface

• NOR Flash/PSRAM/SRAM controller

• SDRAM controller

• NAND controller

Figure 2.7: FMC blocks diagram [21]

The FPGA contains an SRAM cell where the bitfile have to be stored so it is necessaryto configure one of the four banks of the FMC. It is chosen to use bank 3 to perform theoperations of configuration and bank 0 to perform check write/read operations between

15


FPGA and microcontroller; this division is chosen to have relaxed timing for configura-tion(done only once) and better performance in read/write register operations. The FMCgenerates the appropriate signal timings to drive the different types of memories and inthe case of SRAM a non-multiplexed mode and normal asynchronous mode is selected.In this mode, the following parameters that depend on the memory datasheet have to becomputed and set:

• ADDSET: address setup time

• DATAST: data setup time

• ACCMOD: access mode

These parameters give the FMC the flexibility to access static memories. There are fourextended access modes(A,B,C and D) that allow the possibility to change the timing.With the ADDSET and DATAST it is possible to modify the timing to read and writeoperations. The two variables are multiple of the clock core of the micro. In figures 2.8and 2.9 it is possible to see the timing for read and write operation and how the twoparameters modify the timing.

Figure 2.8: SRAM asynchronous read access timing in extended mode [21]

16


Figure 2.9: SRAM asynchronous write access timing in extended mode [21]

Universal asynchronous receiver transmitter (UART)

An embedded system often communicates with the external world. It could be to send andreceive commands, or for debugging purposes or to transfer data to another device. Oneof the most used interfaces is the UART. It is used for different purposes, one of them isto get the debug console functional and to receive information after a command is sent. Itsupports synchronous and asynchronous half-duplex and full-duplex communications; it’salso possible to use DMA(direct memory access) for multibuffer cofiguration. A bidirec-tional communication requires two pins minimum: Receive data (RX) and Transmit data(TX).The serial data that are transmitted and received through the pins are composed by:

• An Idle Line prior for the priority;

• A start bit;

• A data word(7 or 8 or 9 bits) with the least significant bit first;

• 1 or 2 stop bits;

• A status register;

• Data registers(receive and transmit)

• A baud rate register

17


2.2.2 QSPI - NOR Flash Memory

The MT25Q is a multiple input/output serial Nor Flash memory device manifacturedin 45nm. It has a security protection where each sector can be locked independently.To access the full memory storage, the device includes an extended address register; thebase address is 3-Byte address and can only access 128MB of memory; with the extendedaddress register (3 bits [2:0]) it is possible to select one of the eight 128MB segments ofthe memory. In the device, this mode is enabled to store all the bitfile of FPGA and tohave enough space for the audit file.

2.2.3 IMX6

The iMX 6Quad is a 32-bit processor that feature implementation of the quad ARM Cor-tex -A9 core, which operates at speed up to 800MHz. The Cortex-A family comparedto the Cortex-M family (used in STM microcontroller) is the only that includes a mem-ory management unit(MMU); the MMU is harware component that handles all memoryoperations associated with the processor. So in other words it is responsable for all thememory management and its main feature is to perform the translation of virtual memoryaddresses to physical adresses. It includes a General Interrupt Controller(GIC), 32kB ofL1 Instruction cache, 32kB of L1 Data cache and 1MB L2 cache, shared by four cores.The IMX6 is the core of the device; it handles the communications through the Ethernet.The received data are sent to the FPGA with a 16 bit protocol communication.

External Interface Module(EIM)

The External Interface Module manages the interface to the external devices. It includesthe generation of the chip select, clock, and the control of all the external signals. It ispossible to use asynchronnous communication to access device in SRAM-like mode andsynchronous access. The interface with the FPGA is a multiplexed Address/Data mode ,so address and data bits are sent on the same pin. This reduces the number of wires butthe speed is lower. The pins used are EIM_DA[15:0]. The writing operation is performedin syhchronous access; when the address is on the line, the Chip Select enable, write enableand LBA are pulled down, so at the next rising edge of the clock the address is sampled,then the LBA is pulled up and the Data are written. For the reading operation, instead,an asynchronous access is performed. The Chip select is pulled down, then the LBA ispulled down when the Address is ready on the line and when the Output enable has atransition from high to low, the data can be read. After one data is read, the chip selectis released. In figures 2.10 and 2.11the timing of the operations in details are present.

MAC-NET

The MAC-NET core handles the process of the different networking protocols, such asIP protocol(Appendix B) and TCP. It also implements a hardware acceleration blockto optimize the performace of network controllers. The IMX6 supports different speedconfigurations (10/100-Mbit/s) and gigabit full-duplex operations. The Ethernet interface

18


Figure 2.10: Synchronous Muxed A/D write access [20]

Figure 2.11: Asynchronous Muxed A/D read access [20]

used is a SFP transceiver. The small form-factor pluggable is a compact transceiver thatis used both for telecommunication and data communications applications. It interfacesa network device to a fiber optic. It is also compatible with different communicationstarndards and has a transmission rate ranging from 100Mbps up to 10 Gbit/s. All thecommunications needed a standard model to transmit informations, so different standardswere born.

One of the most famous technologies to connect computers, routers, printers all overthe world is Ethernet. In Ethernet, devices wait for a free time slot to communicate in thenetwork and the waiting device transmits when there is no transmitting data. The mediumthough the data travel, can be a coaxial cable, a twisted pair cable, or a fiber optics(like in

19


this device). Ethernet technology defines technical specifications at the physical lever andat the MAC level of the ISO/OSI model network (Appendix A). The system divides thedata into shorter pieces called frames. The basic structure of an Ethernet packet(frame)is recived by the datalink layer. The main elements of a frame are:

• Preamble: The starter is a sequence of 7 bytes of alternating 1 and 0. This sequenceof bits is used to "wake up" the receiver, to synchronize the clocks of the transmitterand receiver.

• Start Frame Delimiter(SFD): The eight byte indicates the beginning of the ethernetframe.It is immediately followed by the MAC address.

• Destination MAC address: It is an uniquely number that contains the LAN addressof the destination and it is composed by 6 bytes.

• Source MAC address: It is the address of the source.

• EtherType: It is composed by 2 bytes and indicates the type of protocols or thelength of the data.

• Payload: It contains the real data that are transmitted. It has a minimum lentgh of48 bytes and if the minimum length is not achieved a padding is added. If the lengthis above the maximum value, the data are split into different packets.

• Frame Check Sequence(FCS): It is a CRC(Cyclic redundancy check) that allows tocheck the presence of transmission errors. The receiver computes the CRC with analgorithm and compares it with the CRC that is received.

2.2.4 Cyclone IV

A Field Programmable Gate Array (FPGA) is an integrated circuit that has the possi-bility to be configured by a designer after manufacturing. In fact, it contains an array ofprogrammable logic blocks. It is possible to realize complex logic functions with a veryhigh scalability.It also includes memory elements, that can be simple flip-flop or morecomplex block memory like SRAM. Altera Cyclone IV is a low power FPGA. It features6K to 150K logic elements, up to 6.3Mb of embedded memory, up to 360 18x18 multi-pliers for DSP processing applicatons and data rates up to 3.125 Gbps. It includes up to30 global clock (GCLK) networks and up to eight PLLs with five outputs. It is possibleto dinamically reconfigure the PLLs. It also supports SDR, DDR, DDR2, SDRAM andQDRII SRAM interfaces and supports the use of error correction coding bits on DDR andDDR2 SDRAM interfaces.The Cyclone IV uses SRAM cells to store the configuration data. Due to the volatile typeof memory, the configuration data must be download in the FPGA each time the devicepowers up. There are different way to configure the device: AS, Ap, FPP and JTAG con-figuration schemes. In this device a fast passive parallel(FPP) configuration is performedusing the STM32F756 microcontroller. The configuration data that is stored in the QSPIis transferred to the FPGA on the DATA[7..0] pins. The configuration data is transferred

20


one byte per clock cycle. After the configuration , the registers and I/O pins must beinitialized, then the device enters in user mode. To perform the configuration a CycleState Machine is to be designed following the cycle waveform shown in the data sheet. Afast passive parallel(FPP) configuration is performed; in this way 8 bits are latched intothe FPGA on every rising edge clock. In figure 2.12 it is shown the configuration cyclewaveform. After the device is configured, its registers, I/O pins have to be initialized.The configuration phase consists of 3 stages: reset, configuration and initialization. WhennCONFIG is low, the device is in reset mode, with the transition low-to-high of nCONFIG,the FPGA starts the configuration. When the nCONFIG goes from 0 to 1, it releases theopen-drain nSTATUS pin, so it is pulled high by the pull-up resistor and now it is possibleto configure the FPGA. After the FPGA has recived all the configuration data, it releasethe CONF DONE pin and a transition low-to-high is performed. When the initializationis done and the FPGA is in user mode, the INIT DONE pin is pulled up. Now the FPGAis ready to perform its operations.

Figure 2.12: Configuration Cycle Waveform [1]

21

Chapter 3

System Architecture

In this chapter a detailed description of the system architecture and all the design stepsis done. In the figure 2.3 a general block diagram of the designed system is represented.The system is composed mainly by two big subsystems:

• the carrier board that contains the components that provide power to the wholesystem and the interfaces to the external world like USB TOKEN, LEDs,reset but-ton,Zeroize button, USB OTG and SFP connectors.

• the main module that contains all the active components that manage the informa-tions that arrive from the external world like the microcontroller, the microprocessor,memories, buses,ecc.The main module is called ENA (Embedded Networked Appli-ance)

The ENA is put in contact with the carrier board through an Express Connector.The used carrier board is a developer carrier board that was designed by Telsy with

different modules that can be used for development of different applications. The mainscope of this thesis is the design of the system and the evaluation and measurement ofthe performance of the ENA. At the end, if the performance are satisfactory a customdesigned carrier board will be produced and in the section 3.1.1, the custom carrier boarddetails are analysed. A flow chart of the general designed steps is made in figure 3.1 andin the following sections all the steps are described in details. It is possible to notice fromthe general block scheme (2.3) that the microcontroller has the rule to manage all theother components so when the ENA is switched on, the STM is turned on; all the othercomponents are still off. For this reason, first, the STM software is developed to performall the tasks needed for the correct download of the bitfile into the FPGA and to handlethe correct reading of the USB Token. After that,if the FPGA works correctly, it is turnedon the microprocessor IMX6 and the network transmission can be handled; a detaileddescription is in section 3.1.2. The last step is related to the tests and measurements toprovide a good precise features and to establish performance; the details are discussed inthe chapter 4.

22

3 – System Architecture

Carrier Board Design

STM Microcontroller Software

IMX Microprocessor Software

Tests and measurements

Good performance?

No enterpriseproduct

PossibleProduction

YESNO

Figure 3.1: General Design Flow Chart

23


3.1 Carrier Board Design and Custom Module StructureIn this section it is analysed the custom designed carrier board with its schematic pagesand the pins of the express connector. The ENA, instead, has already been realized forother applications and it is covered by copyright, so only a brief description of the hardwareand pins is made.

3.1.1 Carrier Board Design

The main play role of the carrier board is to provide power supply to the different parts ofthe system. The main power source is the 230V electric power that is reduced to the range(12-36)V with an external power supply. The system includes also a Li-Ion Battery witha charger, so that, when there is a blackout, the device continues to work. The externalinputs/outputs integrated into the carrier board are the following:

• Plug for 12-36V Vdc;

• 2 LEDs Battery;

• 2 SFP Optical Connector

• 2 LEDs for Lossy in SFP Connection

• Zeroize Button

• Red LED for Antitampering

• Reset Button

• USB Token

• OTG Micro-USB

• 3 LEDs for IMX6 information

• 2 LEDs for STM information

A list with the used components with the relative explanation is done in the following:

• Dual Input Li-Ion Battery Charger LTC4078. It is a linear charger that is ableto charging a single-cell Li-Ion battery from wall adapter. It has a maximum 22Vrating for wall adapter and the charging stops if the power source exceeds the over-voltage limit. To avoid high increasing of temperature the LTC4078 has an internalfeedback regulator that maintains a constant die temperature also during high poweroperations. Two pins of the charger battery provide charge informations. They areconnected to two leds. The pin CHRG is activated(pulled down) when the deviceis charging, and when the cycle is completed, the LED turns off. The PWR pin ispulled down, so the LED turns on when there is a valid input charging(i.e. when theinput supply is greater than the undervoltage and less then the overvoltage) and itturns off when the wall adapter is removed.

24


• Stand-Alone Fuel Gauge IC. The DS2782G+ is an integrated circuit that can mea-sure voltage, temperature, current and can estimate the capacity of the rechargablelithium battery. It gives also information of capacity estimation remaining and thepercentage. The calculations are stored into an EEPROM chip. It is used to under-stand if there is a voltage onto the battery, the temperature, if the current passesand charges the battery correctly. It is possible to program it with an I2C. Due tothe fact that the voltage of I2C from the STM is too low (1.8V) a voltage leveltranslator is used;

• Voltage-Level Translator TCA9406 is a 2-bits bidirectional I2C voltage-level trans-lator. This allows the device to interface between higher logic signal levels(TheDS2782G+ needs 3.3V) and lower logic levels(1.8V of STM);

• LT8614 is a Synchronous Step-Down Switcher regulator. The LT8614 is used tomantain a very stable voltage also at high frequency. It minimizes the EMI emissionsand mantains a very stable voltage up to 2MHZ. It has also a very low quiescentcurrent to have high efficiency with smal load current. The device is used to deliver3.3V to the other components and to provide independent voltage 3.3V to the twoSFP connector.

• LD1117. It is a Low drop-out voltage regulator needed to provide a fixed and stablevoltage output 1.8V.

• A single inverter buffer/Driver with open-Drain output is used to connect the switchbutton to the microcontroller. A "standard" switch is normally open and when it ispushed, it closes, but the Zeroize button is normally closed and when it is pushedhas to be opened. To do this, an inverter is used.

• Two SRV05 integreted circuits are used. They are a 10A diode array to protect theUSBs connector against ESD and high surge events;

• Noise suppression filters that are applied to all the USB connectors to suppress noisefor differential signal line without distortion in high speed transmission due to thehigh coupling.

• LEDs. The anode of the LEDs is connected to the main board through the COM-Express and the cathode is connected to the ground. So when a high logic level isasserted, the Led switches on.

In the following, it is included the schematic of the custom carrier board with some notes forthe PCB Designer. Some components are not used in this project but a space for a possiblewelding of the chip is considered for future company applications. This components aremarked into the schematics with NF.

25


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DIF

F90

44

22

33

11

FL20

0

DLW

21SN

900S

Q2

(Mur

ata)

DIF

F90

DIF

F90

DIF

F90

DIF

F90

GN

DA

1

ncA

2

ncA

3

ETH

_LIN

K10

0#A

4

ncA

5

ncA

6

ncA

7

ETH

_LIN

K#

A8

ETH

_TX

-A

9

ETH

_TX

+A

10

GN

DA

11

ETH

_RX

-A

12

ETH

_RX

+A

13

ncA

14

ncA

15

ncA

16

ncA

17

ZER

OIZ

EA

18

ATD

_LED

_A (*

)A

19AT

D_B

EEP_

A (*

)A

20G

ND

A21

RS4

85-

A22

RS4

85+

A23

WA

KE-

UP

DS-

101

A24

AN

L0_R

X_L

A25

AN

L0_R

X_R

A26

SPK

OU

T_R

_N (*

)A

27SP

KO

UT_

R_P

(*)

A28

AN

L0_T

X_L

A29

AN

L0_T

X_R

A30

GN

D_A

NL

A31

ncA

32nc

A33

ncA

34nc

A35

AN

L1_R

X_L

A36

AN

L1_R

X_R

A37

#PTT

_IN

(*)

A38

AN

L1_T

X_L

A39

AN

L1_T

X_R

A40

GN

D_A

NL

A41

#PTT

_OU

T_O

D (*

)A

42nc

A43

ncA

44nc

A45

ncA

46V

_BAT

T (3

V6)

A47

ncA

48nc

A49

ncA

50G

ND

A51

ncA

52nc

A53

GPI

O0

(1V

8)A

54nc

A55

ncA

56G

ND

A57

ncA

58nc

A59

GN

DA

60SG

MII

_TX

2+(=

=TX

1+)

A61

SGM

II _T

X2-

(==T

X1-

)A

62G

PIO

1 (1

V8)

A63

SGM

II _T

X1+

A64

SGM

II _T

X1-

A65

GN

DA

66G

PIO

2 (1

V8)

A67

SGM

II _T

X0+

A68

SGM

II _T

X0-

A69

GN

DA

70LV

DS_

A0+

A71

LVD

S_A

0-A

72LV

DS_

A1+

A73

LVD

S_A

1-A

74LV

DS_

A2+

A75

LVD

S_A

2-A

76

LVD

S_V

DD

_EN

(1V

8)A

77

LVD

S_A

3+A

78

LVD

S_A

3-A

79

GN

DA

80

LVD

S_A

_CK

+A

81

LVD

S_A

_CK

-A

82

LVD

S_I2

C_C

K (1

V8)

A83

LVD

S_I2

C_D

AT

(1V

8)A

84

POW

ER_O

N (1

V8)

A85

ncA

86

ncA

87

ncA

88

ncA

89

GN

DA

90

ncA

91

SPI0

_MIS

O (1

V8)

A92

GPI

O4

(1V

8)A

93

SPI0

_CLK

(1V

8)A

94

SPI0

_MO

SI (1

V8)

A95

uCRY

PTO

_TX

(1V

8/3V

3)A

96

uCRY

PTO

_RX

(1V

8/3V

3)A

97

SER

0_TX

(1V

8)A

98

SER

0_R

X (1

V8)

A99

GN

DA

100

SER

1_TX

(1V

8)A

101

SER

1_R

X (1

V8)

A10

2

GN

DA

103

VC

C_P

SAA

104

VC

C_P

SAA

105

VC

C_P

SAA

106

VC

C_P

SAA

107

VC

C_P

SAA

108

VC

C_P

SAA

109

GN

DA

110

GN

DB

1

ncB

2

ncB

3

ncB

4

ncB

5

ncB

6

ncB

7

ncB

8

ncB

9

ncB

10

GN

DB

11

ncB

12

ncB

13

ncB

14

ncB

15

ncB

16

ncB

17

USB

_CR

_VC

C (5

V)

B18

USB

_CR

+B

19U

SB_C

R-

B20

GN

DB

21nc

B22

ncB

23nc

B24

ncB

25nc

B26

WD

T (1

V8)

B27

ncB

28nc

B29

ncB

30G

ND

B31

ncB

32I2

C_C

K (1

V8)

B33

I2C

_DA

T (1

V8)

B34

ncB

35nc

B36

ncB

37nc

B38

USB

3_V

CC

(5V

)B

39U

SB3_

IDB

40G

ND

B41

USB

3-B

42U

SB3+

B43

USB

1_V

CC

(5V

)B

44U

SB1-

B45

USB

1+B

46nc

B47

ncB

48SY

S_R

ESET

(1V

8)B

49nc

B50

GN

DB

51R

SVD

B52

RSV

DB

53G

PO1

(1V

8)B

54R

SVD

B55

RSV

DB

56G

PO2

(1V

8)B

57SF

P_I2

C_C

LK (*

)B

58SF

P_I2

C_D

AT

(*)

B59

GN

DB

60SG

MII_

RX

2+ (=

=RX

1+)

B61

SGM

II_R

X2-

(==R

X1-

)B

62G

PO3

(1V

8)B

63SG

MII_

RX

1+B

64SG

MII_

RX

1-B

65SR

DS_

SIG

_DET

(*)

B66

SGM

II_A

LOS

(*)

B67

SGM

II_R

X0+

B68

SGM

II_R

X0-

B69

GN

DB

70D

DIX

_PA

IR0+

B71

DD

IX_P

AIR

0-B

72D

DIX

_PA

IR1+

B73

DD

IX_P

AIR

1-B

74D

DIX

_PA

IR2+

B75

DD

IX_P

AIR

2-B

76

ncB

77

ncB

78

ncB

79

GN

DB

80

DD

IX_P

AIR

3+B

81

DD

IX_P

AIR

3-B

82

ncB

83

ncB

84

ncB

85

ncB

86

CSI

_CLK

+B

87

CSI

_CLK

-B

88

DD

IX_H

PDB

89

GN

DB

90

ncB

91

ncB

92

ncB

93

ncB

94

DD

IX_D

DC

_AU

X_S

ELB

95

ncB

96

SPI_

CS

(1V

8)B

97

DD

IX_C

TRLC

LKB

98

DD

IX_C

TRLD

ATA

B99

GN

DB

100

PWM

(1V

8)B

101

ncB

102

GN

DB

103

VC

C_P

SAB

104

VC

C_P

SAB

105

VC

C_P

SAB

106

VC

C_P

SAB

107

VC

C_P

SAB

108

VC

C_P

SAB

109

GN

DB

110

K20

0

Com

Expr

ess f

emal

e (T

YC

O_3

-631

8491

-6)

DIF

F100

DIF

F100

DIF

F100

DIF

F100

DIF

F100

DIF

F100

DIF

F100

DIF

F100

44

22

33

11

FL20

1

DLW

21SN

900S

Q2

(Mur

ata)

44

22

33

11

FL20

2D

LW21

SN90

0SQ

2 (M

urat

a)

GN

D

12V

C20

110

0nF

LVD

S_B

LK_E

NLV

DS_

BLK

_PW

M

NF

VC

CB

6

DIR

5

B4

VC

CA

1

GN

D2

A3

IC20

0

SN74

AV

C1T

45D

BV

VC

CB

6D

IR5

B4

VC

CA

1G

ND

2A

3

IC20

1

SN74

AV

C1T

45D

BV

GN

D3V3

1V8 GN

D

GPO

3_1V

8

PWM

_OU

T_1V

8

PWM

_OU

T_1V

8

NF NF

C20

310

0nF

C20

410

0nF

NF

NF

R20

9

180R

D20

3

LED

_GR

EEN

-630

0T5

VC

CD

204

LED

_GR

EEN

-630

0T5

VC

CD

205

LED

_GR

EEN

-630

0T5

VC

C

GN

D

NF

1 2 3 4 5 6

P202

Hea

der 6

NC

Wak

eup

GN

D

Dat

a-N

C

Dat

a+

1 2 3 4 5 6

P204

Hea

der 6

1 2 3 4 5 6

P206

Hea

der 6 1 2 3 4 5 6

P207

Hea

der 6 1 2 3 4 5 6

P208

Hea

der 6

1 2 3 4 5 6

P203

Hea

der 6

STM

32F7

_LED

1

STM

32F7

_LED

2

Vcc5

GN

D 3

IN2

Y4

NC

1

IC20

3

SN74

LVC

1G06

-EP

R21

11M

GN

D

GN

D

VB

AT_3

V6

C20

910

0nF

VC

CA

3SD

A_A

4SC

L_A

5O

E6

VC

CB

7SD

A_B

1SC

L_B

8G

ND

2

IC20

4

TCA

9406

I2C

_DA

T(1V

8)I2

C_C

K(1

V8)

GN

D

1V8

3V3

C21

1

100n

F

C21

0

100n

F

ATD

_SD

A

GN

D

ATD

_SC

L

I2C

_CK

(1V

8)I2

C_D

AT(

1V8)

GN

D12 FL204

BLM21PG121SN1 (120 ohm 3A)

IO1

1G

ND

2IO

23

IO3

4V

BU

S5

IO4

6

IC20

5

SRV

05-4

HTG

GN

D12 FL205

BLM21PG121SN1 (120 ohm 3A)

IO1

1G

ND

2IO

23

IO3

4V

BU

S5

IO4

6

IC20

6

SRV

05-4

HTG

ATD

_SC

L

ATD

_SD

A

C21

2

100n

F

GN

D

VB

AT_3

V6

GN

D

GN

D

no

rma

lly

op

en

It m

us

t b

e c

lose

d b

ut

it is

u

se

d a

no

rma

lly

op

en s

wit

ch

NO

T U

SED

NO

T U

SED

To b

e pl

ace

as c

lose

as

poss

ible

to it

s USB

co

nnec

tor

To b

e pl

ace

as c

lose

as

poss

ible

to th

e U

SB

conn

ecto

r

PIC2

0001

PI

C200

02

COC200

PIC20101 PIC20102 CO

C201

PIC20201 PIC20202 COC202

PIC20301 PIC20302 COC203


C204

PIC20501 PIC20502

COC205

PIC20601 PIC20602 COC206

PIC20701 PIC20702

COC207

PIC20801 PIC20802

COC208

PIC20901 PIC20902 COC209

PIC21001 PIC21002

COC210

PIC21101 PIC21102

COC211

PIC21201

PIC21202 COC2

12

PID2000A

PID2000K

COD200

PID2010A PID2010K

COD201

PID2020A PID2020K

COD202

PID2030A

PID2030K

COD203 PID2040A

PID2040K

COD204 PID2050A

PID2050K

COD205

PIFL

20001

PIFL2000

2

PIFL2000

3 PIFL

20004 CO

FL200

PIFL20

101

PIFL

20102

PIFL

20103

PIFL20

104

COFL201 PIFL

20201

PIFL2020

2

PIFL2020

3 PIFL

20204

COFL

202

PIFL20301

PIFL2030

2 COFL

203

PIFL20401 PIFL20402

COFL204

PIFL20501 PIFL20502 COFL205

PIIC20001

PIIC20002

PIIC20003

PIIC20004

PIIC20005

PIIC20006

COIC200

PIIC20101

PIIC20102

PIIC20103

PIIC20104

PIIC20105

PIIC20106

COIC201

PIIC20201

PIIC

2020

2

PIIC20203

PIIC20204

PIIC20205

PIIC

2020

6

PIIC20207

PIIC20208 COIC202

PIIC20301

PIIC20302

PIIC20303

PIIC20304

PIIC20305

COIC203

PIIC20401

PIIC20402

PIIC20403

PIIC20404

PIIC20405

PIIC20406

PIIC20407

PIIC20408 CO

IC20

4

PIIC20501

PIIC20502

PIIC20503

PIIC20504

PIIC20505

PIIC20506

COIC205

PIIC20601

PIIC20602

PIIC

2060

3 PIIC20604

PIIC20605

PIIC20606

COIC206

PIK2000A1

PIK2000A2

PIK2000A3

PIK2000A4

PIK2000A5

PIK2000A6

PIK2000A7

PIK2000A8

PIK2000A9

PIK2000A10

PIK2

000A11

PIK2000A12

PIK2000A13

PIK2000A14

PIK2

000A15

PIK2000A16

PIK2000A17

PIK2

000A18

PIK2000A19

PIK2000A20

PIK2000A21

PIK2

000A22

PIK2000A23

PIK2000A24

PIK2000A25

PIK2

000A26

PIK2000A27

PIK2000A28

PIK2

000A29

PIK2000A30

PIK2000A31

PIK2000A32

PIK2

000A33

PIK2000A34

PIK2000A35

PIK2

000A36

PIK2000A37

PIK2000A38

PIK2000A39

PIK2

000A40

PIK2000A41

PIK2000A42

PIK2

000A43

PIK2000A44

PIK2000A45

PIK2000A46

PIK2

000A47

PIK2000A48

PIK2000A49

PIK2

000A50

PIK2000A51

PIK2000A52

PIK2000A53

PIK2

000A54

PIK2000A55

PIK2000A56

PIK2

000A57

PIK2000A58

PIK2000A59

PIK2000A60

PIK2

000A61

PIK2000A62

PIK2000A63

PIK2000A64

PIK2000A65

PIK2000A66

PIK2000A67

PIK2

000A68

PIK2000A69

PIK2000A70

PIK2000A71

PIK2000A72

PIK2000A73

PIK2000A74

PIK2

000A75

PIK2000A76

PIK2000A77

PIK2000A78

PIK2000A79

PIK2000A80

PIK2000A81

PIK2

000A82

PIK2000A83

PIK2000A84

PIK2000A85

PIK2000A86

PIK2000A87

PIK2000A88

PIK2

000A89

PIK2000A90

PIK2000A91

PIK2000A92

PIK2

000A93

PIK2000A94

PIK2000A95

PIK2

000A96

PIK2000A97

PIK2000A98

PIK2000A99

PIK2

000A

100

PIK2000A101

PIK2000A102

PIK2

000A

103

PIK2000A104

PIK2000A105

PIK2000A106

PIK2

000A

107

PIK2000A108

PIK2000A109

PIK2

000A

110

PIK2000B1

PIK2000B2

PIK2000B3

PIK2000B4

PIK2000B5

PIK2000B6

PIK2000B7

PIK2000B8

PIK2000B9

PIK2000B10

PIK2

000B

11

PIK2000B12

PIK2000B13

PIK2000B14

PIK2

000B

15

PIK2000B16

PIK2000B17

PIK2

000B

18

PIK2000B19

PIK2000B20

PIK2000B21

PIK2

000B

22

PIK2000B23

PIK2000B24

PIK2000B25

PIK2

000B

26

PIK2000B27

PIK2000B28

PIK2

000B

29

PIK2000B30

PIK2000B31

PIK2000B32

PIK2

000B

33

PIK2000B34

PIK2000B35

PIK2

000B

36

PIK2000B37

PIK2000B38

PIK2000B39

PIK2

000B

40

PIK2000B41

PIK2000B42

PIK2

000B

43

PIK2000B44

PIK2000B45

PIK2000B46

PIK2

000B

47

PIK2000B48

PIK2000B49

PIK2

000B

50

PIK2000B51

PIK2000B52

PIK2000B53

PIK2

000B

54

PIK2000B55

PIK2000B56

PIK2

000B

57

PIK2000B58

PIK2000B59

PIK2000B60

PIK2

000B

61

PIK2000B62

PIK2000B63

PIK2000B64

PIK2000B65

PIK2000B66

PIK2000B67

PIK2

000B

68

PIK2000B69

PIK2000B70

PIK2000B71

PIK2000B72

PIK2000B73

PIK2000B74

PIK2

000B

75

PIK2000B76

PIK2000B77

PIK2000B78

PIK2000B79

PIK2000B80

PIK2000B81

PIK2

000B

82

PIK2000B83

PIK2000B84

PIK2000B85

PIK2000B86

PIK2000B87

PIK2000B88

PIK2

000B

89

PIK2000B90

PIK2000B91

PIK2000B92

PIK2

000B

93

PIK2000B94

PIK2000B95

PIK2

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PIK2000B97

PIK2000B98

PIK2000B99

PIK2

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PIK2000B101

PIK2000B102

PIK2

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PIK2000B104

PIK2000B105

PIK2000B106

PIK2

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107

PIK2000B108

PIK2000B109

PIK2

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110

COK2

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PILS

20001

PILS

20002

COLS

200

PIP20001

PIP20002

PIP20003

PIP20004

PIP20005

PIP20006 COP200

PIP20101

PIP20102

PIP20103

PIP20104

PIP20105

PIP20106 COP201

PIP20201

PIP20202

PIP20203

PIP20204

PIP20205

PIP20206

COP202

PIP20301

PIP20302

PIP20303

PIP20304

PIP20305

PIP20306 COP203

PIP20401

PIP20402

PIP20403

PIP20404

PIP20405

PIP20406

COP204

PIP20501

PIP20502

PIP20503

PIP20504

PIP20505

PIP20506

PIP20507

PIP20508

PIP20509

PIP2

05010

PIP2

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PIP2

05012

PIP2

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PIP205

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PIP2

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PIP2

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PIP2

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PIP2

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PIP2

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PIP2

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PIP2

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PIP2

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PIP2

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PIP2

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PIP2

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PIP2

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PIP2

0802

PIP2

0803

PIP2

0804

PIP2

0805

PIP2

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COP208

PIQ20001 PIQ20002

PIQ20003 COQ2

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PIQ20101

PIQ20102 PIQ20103 COQ201

PIR2

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PI

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00

PIR20101 PIR20102 COR201

PIR2

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PI

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COR202

PIR2

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PI

R203

02

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PIR20401 PIR20402 COR204

PIR2

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PI

R205

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PIR2

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PI

R206

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PIR20701 PIR20702 COR207

PIR2

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PI

R208

02 COR208 PIR

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PIR209

02 COR209

PIR2

1001

PI

R210

02 COR210

PIR21101 PIR21102 COR211

PIS20001

PIS20002

COS200

PIS20101

PIS20102 COS201

PITP2000

1 CO

TP20

0 PITP2010

1 CO

TP20

1 PITP2020

1 CO

TP20

2 PITP2030

1 CO

TP20

3 PITP2040

1 CO

TP20

4 PITP2050

1 CO

TP20

5 PITP2060

1 CO

TP20

6

PITP2090

1 CO

TP20

9 PITP2100

1 CO

TP21

0 PITP2110

1 CO

TP21

1 PITP2120

1 CO

TP21

2 PITP2130

1 CO

TP21

3

PITP2140

1 CO

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4

PITP2150

1 CO

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5

PITP2160

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6 PITP2170

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7

PIK2000A38

PITP2110

1 NL

#PTT

0IN

PIK2000A42

PITP2140

1 NL

#PTT

0OUT

0OD

PIK2000B49

PIR20101 PIS20102

NL#SYS0RESET01V8

PIC20401

PIC20801

PIC21101

PIIC20006

PIIC20106

PIIC20203

PIIC

2020

6

PIIC20403

PIIC20406

PIP2

0701

PIP2

0801

PIR20102

PIR2

1002

PIC20301

PIC20701

PIC21001

PIFL20301

PIIC20001

PIIC20101

PIIC20207

PIIC20407

PIP2

0601

PIC20101

PIK2000A104

PIK2000A105

PIK2000A106

PIK2

000A

107

PIK2000A108

PIK2000A109

PIK2000B104

PIK2000B105

PIK2000B106

PIK2

000B

107

PIK2000B108

PIK2000B109

PIP20401

PIC2

0002

PIK2000A20

NLATD0BEEP0A

PIK2000A19

PIR2

0001

NLATD0LED0A

PIIC20408

NLATD0SCL POATD0SCL

PIIC20401

NLATD0SDA POATD0SDA

PIP20005

PIP20006

PIP20106

PIC20102

PIC20202 PIC20302

PIC20402

PIC20502 PIC20601

PIC20702

PIC20802

PIC20901

PIC21002

PIC21102

PIC21202

PID2000K

PID2010K

PID2020K

PID2030K

PID2040K

PID2050K

PIFL20401

PIFL20501

PIIC20002

PIIC20005

PIIC20102

PIIC20105

PIIC

2020

2

PIIC20303

PIIC20402

PIK2000A1

PIK2

000A11

PIK2000A21

PIK2000A31

PIK2000A41

PIK2000A51

PIK2

000A57

PIK2000A60

PIK2000A66

PIK2000A70

PIK2000A80

PIK2000A90

PIK2

000A

100

PIK2

000A

103

PIK2

000A

110

PIK2000B1

PIK2

000B

11

PIK2000B21

PIK2000B31

PIK2000B41

PIK2000B51

PIK2000B60

PIK2000B70

PIK2000B80

PIK2000B90

PIK2

000B

100

PIK2

000B

103

PIK2

000B

110

PILS

20001

PIP20206

PIP20305

PIP20306

PIP20404

PIP20405

PIP20406

PIP20507

PIP20509

PIP2

05011

PIP2

05013

PIP2

05019

PIP2

05020

PIP206

04

PIP206

05

PIP2

0606

PIP2

0704

PIP2

0705

PIP2

0706

PIP2

0804

PIP2

0805

PIP2

0806

PIQ20102 PIR20701

PIS20001

PIS20101

PITP20

601

PIIC20004

PIK2000B63

NLGPO301V8

PIIC20405

PIK2

000B

33

NLI2

C0CK(1

V8)

PIIC20404

PIK2000B34

NLI2

C0DAT(

1V8)

PIK2000A71

PIP205

018

NLLV

DS0A

00

PIK2000A72

PIP2

0501

6

NLLV

DS0A00

PIK2000A73

PIP205

014

NLLV

DS0A

10

PIK2000A74

PIP2

0501

2

NLLV

DS0A10

PIK2

000A75

PIP2

05010

NLLV

DS0A

20

PIK2000A76

PIP20508

NLLV

DS0A20

PIK2000A78

PIP20505

NLLV

DS0A

30

PIK2000A79

PIP20503

NLLVDS

0A30

PIIC20003

PIP20402

NLLV

DS0B

LK0EN

PIIC20103

PIP20403

NLLVDS0BLK0PWM

PIK2000A81

PIP20506

NLLV

DS0C

K0

PIK2

000A82

PIP20504

NLLV

DS0C

K0

PIIC20205

PIK2000A83

NLLVDS0I2C0CK

PIIC20208

PIP205

017

NLLVDS0I2C0CK03V3

PIIC20204

PIK2000A84

NLLVDS0I2C0DAT

PIIC20201

PIP205

015

NLLVDS0I2C0DAT03V3

PIK2000A77

PIQ20101 PIR20702

NLLV

DS0VDD

0EN

PIC2

0001

PILS

20002

PIC20201 PI

FL2030

2

PIQ20002

PIR20402 PIC20501

PIC20602 PIP20501

PIP20502

PIQ20003

PIC20902

PIIC20302

PIR21101 PIS20002

PID2000A

PIR2

0002

PID2010A

PIR2

0202

PID2020A

PIR2

0302

PID2030A

PIR2

0602

PID2040A

PIR2

0802

PID2050A

PIR209

02

PIFL2000

2

PIIC20506

PIP20003

PIFL2000

3

PIIC20504

PIP20002

PIFL

20102

PIIC20604

PIP20102

PIFL

20103

PIIC20606

PIP20103

PIFL

20202

PIP20302

PIFL

20203

PIP20303

PIFL20402 PIIC20502

PIP20004

PIFL20502 PIIC20602

PIP20105

PIIC20301

PIIC20501

PIIC20503

PIIC20601

PIIC

2060

3

PIK2000A2

PIK2000A3

PIK2000A4

PIK2000A5

PIK2000A6

PIK2000A7

PIK2000A8

PIK2000A9

PIK2000A10

PIK2000A12

PIK2000A13

PIK2000A14

PIK2

000A15

PIK2000A16

PIK2000A17

PIK2000A25

PITP2000

1

PIK2

000A26

PITP2010

1 PIK2000A27

PITP2020

1

PIK2000A28

PITP2030

1

PIK2

000A29

PITP2040

1 PIK2000A30

PITP2050

1

PIK2000A32

PIK2

000A33

PIK2000A34

PIK2000A35

PIK2

000A36

PITP2090

1 PIK2000A37

PITP2100

1

PIK2000A39

PITP2120

1

PIK2

000A40

PITP2130

1

PIK2000A

43

PIK2000A44

PIK2000A45

PIK2000A46

PIK2000A48

PIK2000A49

PIK2

000A50

PIK2000A52

PIK2000A53

PIK2

000A54

PIK2000A55

PIK2000A56

PIK2000A58

PIK2000A59

PIK2000A63

PIR2

0601

PIK2000A67

PIR2

0801

PIK2000A86

PIK2000A87

PIK2000A88

PIK2

000A89

PIK2000A91

PIK2000A92

PITP2150

1

PIK2

000A93

PIR209

01

PIK2000A94

PITP2160

1

PIK2000A95

PITP2170

1

PIK2000B2

PIK2000B3

PIK2000B4

PIK2000B5

PIK2000B6

PIK2000B7

PIK2000B8

PIK2000B9

PIK2000B10

PIK2000B12

PIK2000B13

PIK2000B14

PIK2

000B

15

PIK2000B16

PIK2000B17

PIK2

000B

22

PIK2000B23

PIK2000B24

PIK2000B25

PIK2

000B

26

PIK2000B27

PIK2000B28

PIK2

000B

29

PIK2000B30

PIK2000B32

PIK2000B35

PIK2

000B

36

PIK2000B37

PIK2000B38

PIK2

000B

47

PIK2000B48

PIK2

000B

50

PIK2000B52

PIK2000B53

PIK2000B55

PIK2000B56

PIK2000B58

PIK2000B59

PIK2000B66

PIK2000B67

PIK2000B71

PIK2000B72

PIK2000B73

PIK2000B74

PIK2

000B

75

PIK2000B76

PIK2000B77

PIK2000B78

PIK2000B79

PIK2000B81

PIK2

000B

82

PIK2000B83

PIK2000B84

PIK2000B85

PIK2000B86

PIK2000B87

PIK2000B88

PIK2

000B

89

PIK2000B91

PIK2000B92

PIK2

000B

93

PIK2000B94

PIK2000B95

PIK2

000B

96

PIK2000B97

PIK2000B98

PIK2000B99

PIK2000B102

PIP20201

PIP20203

PIP20304

PIQ20001 PIR2

0502

PIQ20103 PIR20401 PI

R205

01

PIK2000A85

PIR2

1001

NLPOWER0ON

PIIC20104

PIK2000B101

NLPWM0OUT0

1V8

PIK2

000A22

PIP20202

NLRS4850N

PIK2000A23

PIP20205

NLRS

4850

P

PIK2000A24

PIP20204

NLRS

4850

WU

PIK2000B69

NLSGMI

I0RX

00N

POSGMII0RX00N

PIK2

000B

68

NLSGMII0RX00P

POSGMII0RX00P

PIK2000B62

PIK2000B65

NLSGMII0RX10N

POSGMII0RX10N

PIK2

000B

61

PIK2000B64

NLSGMII0RX10P

POSGMII0RX10P

PIK2000A69

NLSG

MII0

TX00

N POSGMII0TX00N

PIK2

000A68

NLSGMII0TX00P

POSGMII0TX00P

PIK2000A62

PIK2000A65

NLSGMII0TX10N

POSGMII0TX10N

PIK2000A

61

PIK2000A64

NLSGMI

I0TX

10P

POSGMII0TX10P

PIK2

000B

54

PIR2

0201

NLSTM32F70LED1

PIK200

0B57

PIR2

0301

NLSTM32F70LED2

PIK2000A99

PIP2

0703

NLUART000IMX60RX01V8

PIK2000A98

PIP20702

NLUA

RT000I

MX60

TX01V8

PIK2000A102

PIP2

0803

NLUART010IMX60RX01V8

PIK2000A101

PIP2

0802

NLUA

RT010I

MX60

TX01V8

PIK2000A97

PIP20603

NLUART0CR0RX03V3

PIK2000A

96

PIP20602

NLUA

RT0CR0

TX03

V3

PIFL

20201

PIK2000B45

NLUS

B10N

PIFL

20204

PIK2000B46

NLUS

B10P

PIK2000B44

PIP20301

NLUSB10VCC

PIK2

000B

40

PIP20104

NLUSB30ID

PIFL20

101

PIK2000B42

NLUS

B30N

PIFL20

104

PIK2

000B

43

NLUS

B30P

PIIC20605

PIK2000B39

PIP20101

NLUS

B30V

CC

PIFL

20004

PIK2000B20

NLUS

B0CR

0N

PIFL

20001

PIK2000B19

NLUSB0CR0P

PIIC20505

PIK2

000B

18

PIP20001

NLUSB0

CR0V

CC

PIC21201

PIIC20305

PIK2

000A47

PIR21102

NLVBAT03V6

PIIC20304

PIK2

000A18

NL

ZERO

IZE0

PB

POATD0SCL

POATD0SDA

POSGMII0RX00N

POSGMII0RX00P

POSGMII0RX10N

POSGMII0RX10P

POSGMII0TX00N

POSGMII0TX00P

POSGMII0TX10N

POSGMII0TX10P

Figure 3.2: Carrier Board Schematic: Express Connector Page

26


11

22

33

44

55

66

77

88

DD

CC

BB

AA

Title

Num

ber

Rev

isio

nSi

ze A3

Dat

e:17

/09/

2018

Shee

t o

fFi

le:

G:\N

EW_B

OX

INO

_IP\

..\ET

H_B

LAC

K_S

IDE.

SchD

ocD

raw

n B

y:

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P B

LA

CK

Sid

e

VeeT

1

VeeT

20

TXD

isab

le3

TXFa

ult

2

TD-

19TD

+18

VeeT

17

Vcc

T16

Vcc

R15

VeeR

14

RD

+13

RD

-12

VeeR

11

MO

DD

EF2

4M

OD

DEF

15

MO

DD

EF0

6RA

TE-S

ELEC

T7

LOS

8

VeeR

9Ve

eR10

SHIELD 21

K30

0

SDF-

PLU

G

L301

1uH

L300

1uH

3V3_

N

R30

24K

7

(gnd

)

R30

3**

* (4

K7)

3V3_

N

C30

210

0nF

C30

510

0nF

C30

110

0nF

C30

310

uF/X

7R 2

5V

C30

010

uF/X

7R 2

5V

C30

410

uF/X

7R 2

5V

GN

D

GN

DG

ND

GN

D

SGM

II_R

X0_

PSG

MII

_RX

0_N

1_N

_RX

LOS

NF

IP_B

OX

001

EART

H

SGM

II_R

X0_

PSG

MII

_RX

0_N

SGM

II_TX

0_P

SGM

II_TX

0_N

SGM

II_TX

0_P

SGM

II_TX

0_N

R30

04K

7

3V3_

N

C30

6

100n

F

C30

7

100n

F

ET

HS

FP

Co

nn

ecto

rB

LA

CK

Sid

e

3

1

2

Q30

0FD

V30

3N

GN

D

D30

0LE

D_G

REE

N-6

300T

5 V

CC

R30

133

0R

R30

4

22R

Hig

h w

hen

ther

e is

loss

of

mod

ulat

ed si

gnal

PIC30001 PIC30002 COC300

PIC30101 PIC30102 COC301

PIC30201 PIC30202 COC302

PIC30301 PIC30302 COC303

PIC30401 PIC30402 COC304

PIC30501 PIC30502 COC305

PIC3

0601

PI

C30602

COC3

06

PIC3

0701

PIC3

0702

COC307

PID3000A PID3000K COD300

PIK30001

PIK30002

PIK30003

PIK30004

PIK30005

PIK30006

PIK30007

PIK30008

PIK30009

PIK300010

PIK300011

PIK300012

PIK300013

PIK300014

PIK300015

PIK300016

PIK300017

PIK300018

PIK300019

PIK300020

PIK300021

COK300

PIL3

0001

PIL3

0002

COL300

PIL3

0101

PIL3

0102

COL301

PIQ3

0001

PIQ30002 PIQ30003 COQ300

PIR30001 PIR30002 COR300

PIR30101 PIR30102 COR301

PIR30201 PIR30202 COR302

PIR30301 PIR30302 COR303

PIR304

01 PIR

30402

COR304

PIK30008

PIR304

02 NL10N0RXLOS

PIC30101 PIC30302

PID3000A

PIL3

0001

PIL3

0101

PIR30001

PIR30201 PIR30301

PIK300021

PIC30001 PIC30102

PIC30201 PIC30301

PIC30401 PIC30502

PIK30001

PIK30003

PIK30009

PIK300010

PIK300011

PIK300014

PIK300017

PIK300020

PIQ30002

PIC30002 PIC30202

PIK300016

PIL3

0002

PIC30402 PIC30501

PIK300015

PIL3

0102

PIC306

02

PIK300018

PIC3

0702

PIK300019

PID3000K PIR30101

PIK30002

PIR30002

PIK30004

PIK30005

PIK30006

PIR30202

PIK30007

PIR30302

PIQ3

0001

PIR

30401

PIQ30003 PIR30102

PIK300012

NLSGMI

I0RX00

N POSGMII0RX00N

PIK300013

NLSGMII0RX00P

POSGMII0RX00P

PIC3

0701

NLSGMI

I0TX00

N POSGMII0TX00N

PIC3

0601

NLSG

MII0TX00

P POSGMII0TX00P

POSGMII0RX00N

POSGMII0RX00P

POSGMII0TX00N

POSGMII0TX00P

Figure 3.3: Carrier Board Schematic: SFP Black Optical Module Page

27


11

22

33

44

55

66

77

88

DD

CC

BB

AA

Title

Num

ber

Rev

isio

nSi

ze A3

Dat

e:17

/09/

2018

Shee

t o

fFi

le:

G:\N

EW_B

OX

INO

_IP\

..\ET

H_R

ED_S

IDE.

SchD

ocD

raw

n B

y:

SF

P R

ED

Sid

e

VeeT

1

VeeT

20

TXD

isab

le3

TXFa

ult

2

TD-

19TD

+18

VeeT

17

Vcc

T16

Vcc

R15

VeeR

14

RD

+13

RD

-12

VeeR

11

MO

DD

EF2

4M

OD

DEF

15

MO

DD

EF0

6RA

TE-S

ELEC

T7

LOS

8

VeeR

9Ve

eR10

SHIELD 21

K40

0

SDF-

PLU

G

L401

1uH

L400

1uH

3V3_

R

R40

24K

7

(gnd

)

ET

HS

FP

Co

nn

ecto

rR

ED

Sid

e

R40

3**

* (4

K7)

3V3_

R

C40

210

0nF

C40

510

0nF

C40

110

0nF

C40

310

uF/X

7R 2

5V

C40

010

uF/X

7R 2

5V

C40

410

uF/X

7R 2

5V

GN

D

GN

DG

ND

GN

D

1_R

_RX

LOS

NF

IP_B

OX

001

SGM

II_TX

1_P

SGM

II_TX

1_N

SGM

II_R

X1_

PSG

MII

_RX

1_N

EART

H

SGM

II_R

X1_

PSG

MII

_RX

1_N

SGM

II_TX

1_P

SGM

II_TX

1_N

R40

04K

7

3V3_

R

C40

6

100n

F

C40

7

100n

F3

1

2

Q40

0FD

V30

3N

GN

D

D40

0LE

D_G

REE

N-6

300T

5 V

CC

R40

133

0R

R40

4

22R

Hig

h w

hen

ther

e is

loss

of

mod

ulat

ed si

gnal

PIC40001 PIC40002 COC400

PIC40101 PIC40102 COC401

PIC40201 PIC40202 COC402

PIC40301 PIC40302 COC403

PIC40401 PIC40402 COC404

PIC40501 PIC40502 COC405

PIC4

0601

PI

C40602

COC4

06

PIC4

0701

PIC4

0702

COC407

PID4000A PID4000K COD400

PIK40001

PIK40002

PIK40003

PIK40004

PIK40005

PIK40006

PIK40007

PIK40008

PIK40009

PIK400010

PIK400011

PIK400012

PIK400013

PIK400014

PIK400015

PIK400016

PIK400017

PIK400018

PIK400019

PIK400020

PIK400021

COK400

PIL4

0001

PIL4

0002

COL400

PIL4

0101

PIL4

0102

COL401

PIQ4

0001

PIQ40002 PIQ40003 COQ400

PIR40001 PIR40002 COR400

PIR40101 PIR40102 COR401

PIR40201 PIR40202 COR402

PIR40301 PIR40302 COR403

PIR404

01 PIR

40402

COR404

PIK40008

PIR404

02 NL10R0RXLOS

PIC40101 PIC40302

PID4000A

PIL4

0001

PIL4

0101

PIR40001

PIR40201 PIR40301

PIK400021

PIC40001 PIC40102

PIC40201 PIC40301

PIC40401 PIC40502

PIK40001

PIK40003

PIK40009

PIK400010

PIK400011

PIK400014

PIK400017

PIK400020

PIQ40002

PIC40002 PIC40202

PIK400016

PIL4

0002

PIC40402 PIC40501

PIK400015

PIL4

0102

PIC406

02

PIK400018

PIC4

0702

PIK400019

PID4000K PIR40101

PIK40002

PIR40002

PIK40004

PIK40005

PIK40006

PIR40202

PIK40007

PIR40302

PIQ4

0001

PIR

40401

PIQ40003 PIR40102

PIK400012

NLSGMI

I0RX10

N POSGMII0RX10N

PIK400013

NLSGMII0RX10P

POSGMII0RX10P

PIC4

0701

NLSGMI

I0TX10

N POSGMII0TX10N

PIC4

0601

NLSG

MII0TX10

P POSGMII0TX10P

POSGMII0RX10N

POSGMII0RX10P

POSGMII0TX10N

POSGMII0TX10P

Figure 3.4: Carrier Board Schematic: SFP Red Optical Module Page

28


11

22

33

44

55

66

77

88

DD

CC

BB

AA

Title

Num

ber

Rev

isio

nSi

ze A3

Dat

e:17

/09/

2018

Shee

t o

fFi

le:

G:\N

EW_B

OX

INO

_IP\

..\M

AIN

_PO

WER

.Sch

Doc

Dra

wn

By:

Mai

n P

ow

er

1

3

2

4

L102

AC

M12

11-7

01-2

PL-T

L01

C10

9

100n

F

C10

8

10nF

F100

Fuse

1A

max

C10

7

1nF

C10

6

220p

F

C110

47uF

/X7R

25V

IHLP

2525

CZE

R6R

8M01

L100

6,8u

H

C10

0

1nF

C10

1

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Figure 3.5: Carrier Board Schematic: Main Power Page

29


Express Connector

The motherboard integrated a COM-Express female type TYCO_3-63184916 with 220pinsbut not all the pins are used. A list with the used pins is done in the tables 3.1, 3.2, 3.3 and3.4. The COM Express provides to the main board the 12V, the Voltage battery (3.6V)and the physical ground.

Table 3.1: COM Express A-pins I

PIN Signal NoteA1 GND GroundA11 GND GroundA18 ZEROIZE It connects the Zeroize botton to the STMA19 ATD_LED_A Antitampering LedA20 ATD_BEEP_A Antitampering BeeperA21 GND GroundA22 RS485- DS-101 Data -A23 RS485+ DS-101 Data+A24 WAKE-UP DS-101 Wake upA47 V_BATT(3V6) Voltage from the Li-BatteryA51 GND GroundA57 GND GroundA60 GND GroundA61 SGMII_TX2+ SGMII Tx Line connects to the Red Switch SFPA62 SGMII_TX2- SGMII Tx Line connects to the Red Switch SFP

30


Table 3.2: COM Express A-pins II

PIN Signal NoteA63 GPIO(1V8) It connects a LED to the IMXA64 SGMII_TX1+ Connected to the A61A65 SGMII_TX1- Connected to the A62A66 GND GroundA67 GPIO2(1V8) It connects a LED to the IMXA68 SGMII_TX0+ SGMII Tx Line connects to the Black Switch SFPA69 SGMII_TX0- SGMII Tx Line connects to the Black Switch SFPA70 GND GroundA85 POWER_ON(1V8) Connected to 1.8VA93 GPIO4(1V8) It connects a LED to the IMXA98 SER0_TX(1V8) UART Transmitter IMXA99 SER0_RX(1V8) UART Reciver IMXA100 GND GroundA101 SER1_TX(1V8) UART 1 Transmitter IMXA102 SER1_RX(1V8) UART 1 Reciver IMXA103 GND Ground

A104-A109 VCC Power Input (+5V or +12V) default value=12VA110 GND Ground

3.1.2 The ENA

The Main custom module is the core of the device; it contains the principal components:the FPGA, the microcontroller, the microprocessor, the QSPI and all the used buses. In thefigure 3.6 a Block Diagram of the main board is shown. For each main component a briefdescription of the pins and their functions is made for the explanation of the schematic.

STM32F756

In this subsection the pinout of the STM is done, focusing the attention on the main usedpins. The pins are divided into different ports. In the tables 3.5,3.6 and 3.7,the pinoutsand the pin descriptions are present. The STM is connected to the FPGA with a Bus of16 bits; the FPGA stores the configuration data in SRAM cells, so the Bus is composedby a Data Bus of 16 bits where the data travel, a 10 bit Address bus where the addressof the registers is passed to the FPGA during the read and write operations and thesignal control pins (write enable, output enable, chip select). The STM has also the taskto power on/off the FPGA and to manage the interrupt from FPGA with the Power Oncontrol Signal and Interrupt signal. It powers on/off the microprocessor IMX6 and sendsthe BOOT parameters. The STM uses an UART to communicate with the IMX6 receivinginformations and sending command. Lastly, it shares a bus with the QSPI memory to readand write data. The JTAG Interface is used to program the STM.

31


Table 3.3: COM Express B-Pins I

PIN Signal NoteB1 GND GroundB11 GND GroundB18 USB_CR_VCC(5V) USB Power +5VB19 USB_CR+ USB Differential Line+B20 USB_CR- USB Differential Line-B21 GND GroundB31 GND GroundB33 I2C_CK(1V8) I2C IMX CLK for Battery Managment ChipB34 I2C_DAT(1V8) I2C IMX DAT for Battery Managment ChipB39 USB3_VCC Micro USB OTG IMX6 Power 5VB40 USB3_ID Micro USB OTG IMX6 IDB41 GND GroundB42 USB3- Micro USB OTG IMX6 -B43 USB3+ Micro USB OTG IMX6+B44 USB1_VCC USB Host IMX6 Power (internal to the device)B45 USB1- USB Host IMX6 - (internal to the device)B46 USB1+ USB Host IMX6 + (internal to the device)B49 SYS_RESET(1V8) Reset Button

Table 3.4: COM Express B-Pins II

PIN Signal NoteB51 GND GroundB54 GPIO1(1V8) LED1 STMB57 GPIO2(1V8) LED2 STMB60 GND GroundB61 SGMII_RX2+ SGMII Rx Line connects to the Red Switch SFPB62 SGMII_RX2- SGMII Rx Line connects to the Red Switch SFPB64 SGMII_RX1+ Connected to B61B65 SGMII_RX1- Connected to B62B68 SGMII_RX0+ SGMII Rx Line connects to the Black Switch SFPB69 SGMII_RX0- SGMII Rx Line connects to the Black Switch SFPB70 GND GroundB80 GND GroundB100 GND GroundB103 GND Ground

B104-B109 VCC Power Input (+5V or +12V) default value=12VB110 GND Ground

32


Figure 3.6: Block Diagram of the main board

FPGA-Cyclone IV

The FPGA is interfaced with the STM microcontroller and with the IMX6 microprocessorwith two different buses. The STM is interfaced with the FPGA with a Bus of 16 bits ofdata and 10-bits address. Instead, the IMX6 is connected with a multiplexed Data/Addressof 16-bit.The Pinout of FPGA is in table 3.8.

33


Table 3.5: PinOut of the Interface between STM and FPGA

SIGNAL Function/Description Connection DirectionnEMC_BL0 Memory (Data Low) FPGA OutnEMC_BL1 Memory(Data High) FPGA OutEMC_OE Memory(Output Enable) FPGA OutEMC_WE Memory(Write Enable) FPGA OutEMC_CS1 Chip Select for FPGA FPGA Out

nINT_FPGA Interrupt from FPGA FPGA, Int=0; InnRST_FPGA Reset FPGA FPGA, Rst=0; Out

EMC_A0-EMC_A5 Memory(Add 0-5) FPGA OutEMC_A12-EMC_A15 Memory(Add 6-9) FPGA OutEMC_D0-EMC_D1 Memory(Data 0-1) FPGA I/OEMC_D2-EMC_D3 Memory(Data 2-3) FPGA I/OEMC_D4-EMC_D12 Memory(Data 4-12) FPGA I/OEMC_D13-EMC_D15 Memory(Data 13-15) FPGA I/O

FPGA_CLK FPGA Clock FPGA OutFPGA_CRC_ERROR Crc Error from FPGA FPGA InFPGA_INIT_DONE Init. Signal from FPGA FPGA In

FPGA_CONFIG_DONE Conf. Signal from FPGA FPGA InFPGA_nSTATUS FPGA Signal Status FPGA InFPGA_nCONFIG FPGA Config Signal FPGA OutFPGA_PWRON Power On Control Signal FPGA, Off=0 Out

nFMC_NE4 CS for FPGA registers FPGA Out

Table 3.6: PinOut of the Interface between STM and IMX6

SIGNAL Function/Description Connection DirectionIMX_BOOT_CTRL0-1 Control Signal IMX6 OutIMX_BOOT_CTRL2 Control Signal IMX6 OutIMX_BOOT_CTRL3 Control Signal IMX6 OutIMX_BOOT_CTRL4 Control Signal IMX6 OutIMX_BOOT_CTRL5-7 Control Signal IMX6 OutIMX_BOOT_CTRL8-9 Control Signal IMX6 OutIMX_BOOT_CTRL10 Control Signal IMX6 OutIMX_BOOT_SEL0-1 Sel. 0 and 1 IMX6 Out

nUCC_IMX6_RST_3V3 Reset for IMX6 IMX6; OutUCC_IMX6_PWRON_3V3 Power On IMX6 IMX6; Out

UCC_IMX6_PW_EN Pw Enable for IMX6 IMX6; OutUCC_IMX6_RXD_3V3 Rx UART from IMX6 IMX6 OutUCC_IMX6_TXD_3V3 Tx UART to IMX6 IMX6 In

34


Table 3.7: PinOut of STM

SIGNAL Function/Description Connection DirectionPWR_GOOD Power Supply GOOD ERR=0; InATD_ALARM Alarm of Antitampering ALARM=0; InQSPI_CLK Interface QSPI(Clock) QSPI OutQSPI_NCS1 Interface QSPI(Chip Select) QSPI OutQSPI_D0-1 Interface QSPI(D0-1) QSPI I/OQSPI_D3 Interface QSPI(D3) QSPI I/OQSPI_D2 Interface QSPI(D2) QSPI I/O

TMS/SWDIO JTAG Interface PC InTCK/SWCLK JTAG Interface PC In

TDI JTAG Interface PC InTDO/SWO JTAG Interface PC In

TRST JTAG Interface PC InSTM32_LED1_A_3V3 LED1 STM32F756 ON=1; OutSTM32_LED1_A_3V3 LED1 STM32F756 ON=1; Out

UART7_RX_3V3 Rx UART from PC PC InUART7_TX_3V3 Tx UART to PC PC Out

USB_FS_N USB- Interface USB TOKEN I/OUSB_FS_P USB+ Interface USB TOKEN I/O

3.2 STM Microcontroller Software

In this section the role of the STM, its behaviour and the different functions of the codeare analized. In figure 3.7, the flow chart of the STM set up is represented. After the poweron of the ENA (so the power on of STM), the STM has to be configured to open in a rightway the USB Token. Then, two STM Leds are switched on to communicate that the USBconfiguration is done and it is possible to plug in the USB Token. The USB Token has tobe identify; after that the bitfile is write into the flash memory. If the process ends withouterrors, it is possible to configure the FPGA. At the end of the FPGA configuration, themicroprocessor IMX6 is switched on.

3.2.1 Initialization TOKEN

After the power on of the STM, it is necessary to configure the USB host. A USB Token isused to download the FPGA bitfile into the board. The Token is a USB pen-drive with adedicated chip and the possibility to plug in a micro SD and a SDCard. It contains two filesystems: one is the Virtual System USB and the second is a FatFs folder called DISC_1.The DISC_1 is the folder of the microSD. In DISC_1 a folder is present named with theserial number of the device. Each device has an unique serial number, so in this way, everysingle USB token is associated to its device.

35


Table 3.8: Pinout of FPGA Cyclone IV

SIGNAL Function/Description Connection DirectionEMC_BL0(IO/-BLE) Memory(Data Low) STM InEMC_BL1(IO/-BLE) Memory(Data High) STM In

EMC_OE Memory(Output Enable) STM InEMC_WE Memory(Write Enable) STM InFPGA_CS1 Memory(Chip Select) STM InFPGA_INT Interrupt to STM STM OutRTS_FPGA Reset of FPGA STM InEMC_A0-A9 Memory(Address 0-9) STM I/OEMC_D0-D15 Memory(Data 0-15) STM I/OFPGA_CLK FPGA Clock STM In

FPGA_CONFIG Configuration Signal STM I/OFPGA_CONFIG_DONE Configuration Done STM OutFPGA_CRC_ERROR CRC Error Signal STM OutFPGA_INIT_DONE Init. Done Signal STM OutFPGA_PWRON Power On Controll STM InFPGA_STATUS Status Signal STM OutEIM_BCLK Clock from IMX6 IMX InEIM_CSN Chip Select IMX In

EIM_DA0-15 Data/Address 0-15 IMX I/OEIM_EB0-1 Enable Signal IMX InEIM_LBA Load Signal IMX InEIM_OE Output Enable IMX InEIM_RW Read Signal IMX In

EIM_WAIT Wait Signal IMX Out

If a different token is plugged in, it is no possibility to open the folder and to performall the next operations. In the folder is present the bitfile of the FPGA named "fpga.rbf".From now on, if a Token USB is plugged in, an interrupt is sent to the STM.

3.2.2 LEDs 1 & 2 ON

After the Token Initialization, two LEDs are switched on. Before do this, the PIN I/Ohave to be configured. LEDs are output pin and they not require a high output maximumfrequency. If one of the two leds remains off, some problems occur.

3.2.3 Communication TOKEN

It handles all the functions to communicate with the token, to write the Bitfile into theFPGA and to communicate with the FPGA. The STM waits until a USB is plugged in.

36


STM InitializationAll the pins are set, and the

initialization procedure is completed

LEDs 1 & 2 ONLEDs 1 and 2 of STM are initialized

and are switched on to communicatethat the microcontroller is ready

Communication TOKENWhen the TOKEN is put in,

identification of the token isperformed, the writing of the

configuration file of FPGA into theQSPI is performed, and the

configuration of FPGA is made.

Identification TOKEN

The Token is Identify, and if the Token isRight, it is possible to write its content

into the QSPI

Write QSPI

The Configuration file of the FPGA fromthe USB is written into the Flash

Memory. If the write operations arecompleted successfully, the FPGA is

programmed

FPGA Configuration

The FPGA is configured and the bitfile isdownloaded into the FPGA SRAM. If the

configuration is completed withouterrors, the microprocessor is turned on.

IMX6 Power OnAll the configurations are done andthe IMX6 is turned on to start che

network communication

Figure 3.7: Flow Chart of STM software

37


When a USB is put in, an interrupt is sent to the STM, so the machine passes froma Disconnected state to a Connected state. After that, it is necessary to verify that thetoken has the correct serial number of the device. It is a function into an infinite loop;after that the FPGA is configured, and the IMX6 is switched on, STM does nothing.First of all, it is needed to process in loop the USB host Backgroud task, in this waywhen the USB TOKEN is plugged in, an interrupt is sent to the STM and the USB Classpasses from DISCONNECT to HOST_USER_CLASS_ACTIVE so the application stateis : APPLICATION_READY. So when the USB is put in, it is possible to verify thecorrectness of the Token. Then it is written the Bitfile into the QSPI. After that, even ifthe STM is turned off, the bitfile still remains into the Flash Memory but to configurethe FPGA the TOKEN must be plugged in. Then the FPGA is configured and the bitfileis write into the SRAM of FPGA. Details of the functions are reported in the followingsubsections.

Identification Token

When a Token is plugged in, it is necessary to perform an identification to understandif the token is a valid token. Every single IP BOX has a serial number written into theFlash Memory of the STM. So a TOKEN has a unique identify serial number that hasto correspond to the serial number of the machine. The serial number is the name of adirectory into the µSD DISC_1 CARD. If the path with the serial number is correct andthe directory is correctly opened, it is possible to written the bitfile contained into thedirectory.

Write QSPI

The Bitfile is in the folder that has the Serial Number as name, so the first thing to do isto open the folder and read the file "fpga.rbf". After that it is possible to compute the totallength of the file. In the QSPI, it is not included only the bitfile but, before it, an Headeris written and at the end of the bitfile a footer is included. So it is computed the totalsize taking into account of the total length. The QSPI Flash memory can be eresed only512 Bytes every time, so the total number of blocks is computed. Then, all the blocks areerased. The Header contain a number called "Magic", the length of the bitfile and numberof blocks. So the computed Header file is written into the QSPI. Every time a block of512Bytes is read and write, it is verified the correctness of the operations; if there aresome errors or differences between what it is written and what is read, the operation isstop immediately. Then it is verified the correctness of the written data. A reading cycle isperformed and the two data are compared. During the operations a SHA-256 is computedto verify in any time the corruption of the file. At the and of all writing cycles, the finalSha-256 is computed and it is written at the end of the Bitfile into the Flash memory. Aflow chart of the Download of the bitfile into the FPGA is in figures 3.8 and 3.9.

38


FPGA Configuration

Before the FPGA Configuration, it is necessary to power on the FPGA and set pins inproperly way. All the output pins are put in default mode, in this way no conflicts arepossible. The FPGA requires an external clock to perform the configuration and read thedata, so with the STM it is possible to set a special pin (PC9), that is used as clock pin.A clock of 108MHz is selected.Then, the bus that connects the STM with the FPGA has to be initialized and configure.The FPGA pins are placed in different STM ports, so it is necessary to configure differentPort GPIO (D, E, F, G). The FPGA has an SRAM that stores the bitfile, so the FMC(subsection 2.2.1) of the STM has to be configured. It is choosen to use two configurationbanks to perform different tasks. The bank 3 is used for configure the FPGA and has arelaxed time to reduce configuration errors. So it is choosen as Setup Time a value equal to2, that is a multiple of the core clock fHCLK = 216MHz so a period of THCLK = 4.63ns.So the Setup time it is choosen to be ADDSET = 4.63ns ∗ 2 = 9.26ns. From the figure2.8, the setup time is the time needed from when the address is on the bus and the outputenable is pulled down. From figure 2.9 the setup time is the time from when the address ison the bus and the write enable is acivated. The Data setup time is choosen equal to 10.In this way DATAST = 4.63ns ∗ 10 = 46.3ns; during the reading process, it indicates thetime duration of the output enable; so, it is the time during which it is possible to read thedata on the bus. During the writing process , DATAST indicates the time during whichthe data is writing, so during the Configuration with long time, the FPGA has much timeto save the data correctly in the SRAM, reducing this time, the FPGA has to read thedata faster. The bank 0 is used for interface the STM with the registers of FPGA. Theyare used for perform a test to verify the correctness of the bitfile into the FPGA. Afterthe initialization of FPGA, the configuration procedure can start.The configuration of the FPGA is performed; after the power on of the FPGA, it is testedthe integrity of the FPGA; then it is tested if the FPGA is in stand-by state. So it is setto 1 the pin nCONFIG, after a small delay, it is read the pin nSTATUS; if the pin isup, the FPGA is in STAND-BY state, otherwise there is an error ed it is not possibleto perform the configuration, so the Exit Config process is performed. After that, a flagcalled program_done is set to 0; only if the configuration is correctly completed, it is as-serted. Then all the errors are setted to 0; during the process, the errors are removed; thisprocedure guarantees the correctness of the process. At the end of the process, if one ofthis flag remains zero, there is some problem. During the configuration, it is possible thatsome errors could occur, so a reprogramming process is taken into account. The configura-tion, in case of error, is performed maximum twice, after that, if errors continue to occur,the FPGA is switched off. All the possible errors that can occur during the programmingprocess are reported; on every reading cycle or writing cycle, if error occur,the FPGA isswitched off. Before the writing of the bitfile into the FPGA, it is verified that the filestored into the the QSPI contains a right HEADER_BITFILE.(3.10) After the reading ofthe header from the QSPI, the magic number contained into the QSPI is compared withthe Magic number written into the memory of the STM, if the two magic number are thesame, it means that it is a secure file. Then the length contained into the header is analized

39


and if the file has a length equal to zero,error is returned and the process is stopped. Intothe Header file is contained also the number of 512byte blocks. If this number is equal tozero an error is returned. If the HEADER_BITFILE is correct, it is possible to start theconfiguration 3.11. The process configuration ends when the flag program_done is set to1 or if the counter goes to zero.During the process, the SHA256 is computed to guarantee that the data are not cor-rupted. So, the SHA is initialized then the total number of byte it is set to zero. TheFPGA starts the process configuration if a transition from 1 to 0 and then from 0 to 1has to be performed from pin n_CONFIG as indicated in figure 2.12 and the FPGA"responds" moving the pin n_STATUS. If the FPGA pulls down and then up the pin,the reading and writing operations start.An iterative process is performed for every block of 512Bytes (figure 3.12). The block isfirst read from the QSPI, the SHA256 is updated and an iterative cycle is done; one byteper time is write into the FPGA (figure 3.14); when all blocks are read, the pin n_STATUSis read and if it is at one the flag program_done is set to 1; else the program_done stillremains zero and the exit_loop is performed (figure 3.13). When the exit_loop is per-formed with program_done = 0, the counter is decreased and the programming processis retried, because all the blocks are written into the FPGA but it doesn’t pull downthe nSTATUS flag for some errors. Every writing process of 512 bytes is concluded, thepins CONF_DONE, INIT_DONE and CRC_ERROR are checked and if one of this ispulled up, the error flag CONF_DONE_ok is removed (figure 3.14). After that all blocksare written correctly, the final SHA256 is computed. If the computed SHA256 is differentfrom the SHA256 written at the end of the QSPI file, the bitfile written into the FPGAis corrupted, so the exit_config is performed and the FPGA is switched off. If the twoSHA are equal, the bitfile is not corrupted (figure 3.13); so the program_done is checkand if during configuration the nSTATUS pin is pulled down, the flag is set, then theConf_DONE_ok is check and if it is equal to zero, means that the configuration is com-pleted but contains some errors so the FPGA is switched off. If the CONF_DONE_okis equal to 1, the configuration doesn’t contain errors. So, at this point, the initializationprocedure is performed and a dummy cycles for INIT_CY CLE is done. At the end ifthe initialization is correctly completed, both n_STATUS pin and CONF_DONE pinare moved by the FPGA. If one of this is at 1, the initialization is finished but containserrors. If it is correct, other dummy cycles are performed. Then the check of the FPGA isperformed, writing one register and after a delay, the same register is read; the result mustbe congruent with the operations written into the FPGA with the bitfile. If everything iscompleted correctly, the n_CONFIG pin is disabled and the configuration of FPGA issuccessful.

Power on of IMX6

After that the configuration of the FPGA and the tests, the IMX6 can be switched on andthe application can start.

40


3.3 IMX6 Microprocessor Software

The microprocessor IMX6 is the core of the ENA; it handles all the traffic network.The scope of the board is to encrypt IP packets and decrypt them. So the IMX hasto manipulates packets that arrives from one Ethernet interface, send them to the FPGA,then read them from the FPGA and forward them to the second Ethernet interface. TheENA(Embedded Networked Appliance) board is never used for this scope, so deep analysisare performed to verify the performance of the board. Different steps are done before toperform the complete task of the IMX6 in order to report all the data.

3.3.1 Kernel IP Forwarding

The IMX6 has two Ethernet interfaces one is named eth0 and the second is eth1. The firststep is the verification of the correctness work of single ethernet. For this reason two PC areconnected to the board with two copper ethernet wires. The two Ethernet interfaces have tobe configured. The IMX6 has a USB console, so using a microUSB cable is possible to openthe console of IMX6 on a PC. On the PC it is required a Linux Operating system. After theconnection of the IMX6, the console is opened. In this condition the Ethernet interfacescan be configured. The network setup can be done via the interfaces configuration filethat is at etc/network/interfaces. So editing this file it is possible to set-up the network.Here it is possible to give the network card an IP address (or use the DHCP), set up therouting information, configure the IP mask, set the default routes and other options. Theboard has two network interfaces that have to be configured. In figure 3.15 is present thenetwork interfaces that is created. The first interface has a Net-ID different from the otherinterface. The two PCs are configured with its own net ID and a gateway; through thegateway it is possible to know how to reach the destination. From the PC 1 it is sent a pingto the Board and it is verified if it works, the same think is done with the PC 2. So the twoPc are connected respectively to own network. Until now the Two PC are connected withthe board but are not connected together: the two networks are different, so in order toconnect one host to the other host it is needed that the board "connect" the two network;in this way each packet that arrives from the PC1 is forwarded and can be received fromthe PC2. To do this the IP forwarding is used. IP forwarding (or IP routing) is a processused to transfer IP packets from one network to another. So the next step is to enable theIP forwarding on the Board and verify the correct work. It is possible to enable the IPforwarding writing in the IMX6 console : echo 0 > /proc/sys/net/ipv4/ip_forward. Inthis way if the configuration of the hosts and of the board is done correctly, it is possible tosend a ping from the PC 1 to the PC2 and all the packets that arrives to the Board and aredirected to the PC 2 are forward. It is possible in this situation to verify the performanceand the throughput of the connections. Those results are the maximum throughput thatthe ENA can be achieve. The values are used as references for the next experimental tests.

41


3.3.2 User Space application for IP Forward

The second step is the design of an application at User space that handles the trafficnetwork, manipulates every IP packet and forward it from the first Ethernet interface tothe second interface. So an IP forward application is designed. There are some differentpossibilities to perform this task. One of this is the use of Socket Raw. A networking socketis an abstractive software that is an applicative endpoint to access to a communicativechannel through a port. So a bidirectional network communication between two physicalmachine that are separating each other. From a software point of view, a socket is anobject that has the possibility to read data or transmit data. A raw socket is a particularsocket that has the possibility to read, write IP(v4) datagrams with protocols that arenot handle from the kernel and it is possible to determine every section of the packet,like header and payload. Its is possible to categorize raw socket into Network Socket(L3 Socket) and Data-Link Socket(L2 Socket). In L3 socket it is possible to determineheader, payload of the packet in th network layer; in L2 socket instead it is possible to setHeader and payload of packet at datalink layer, so it is possible to modify and manipulateeverything in packet. In the design application, the sockets are first opened, one for eth0and the second for eth1. After that, the application waits until something arrives on thetwo interfaces. If the receiver of the eth0 or eth1 receives datas, all the bytes are saved intoa buffer. Then the destination IP address(32 bits) is extracted from the Ethernet Frameand if the destination address isn’t the IP address of the current interface, the packet isforward and it is sent to the other interface. In this way, every packets that arrives fromone side, are forwarded and sent from the other interface. So sending a ping from PC1 toPC2, the IP packets arrive from the other side and a connection between the two hostesis established. In this situations the tests and the performances are computed and in thechapter 4 are discussed.

3.3.3 Encryption and Decryption of Ethernet Packets

The last step is to include in the application the FPGA scope. The packets that arrivefrom one channel are saved into a buffer; then are sent to the FPGA and after a number ofclock cycles (that depends on the length of the Ethernet frame), if the data were clear, theyare crypted from the FPGA and are read; the crypted informations are sent to the secondinterface. The same think happens when the ethernet data that arrives are crypted; theyare sent to the FPGA and are encrypted. Those operation take time, so the throughputof the ENA decreases. So an analysis is performed in the chapter 4. Those performanceare the real throughput.

42


Open File "fpga.rbf"

FR_OK? Open File ErrorFalse

Compute LengthFile

True

Len==0? Void BitfileTrue

Compute n_blocks toerese

False

Number of processedblocks is less then the

number of blocks.Erese QSPI Block

TrueErase Fail?

Compute Header andWrite Header

i++False

Error Erase Fail

Write Fail? Error Write Fail

True

True

Read Header

False

False

Figure 3.8: Flow Chart for QSPI writing process Part I

43


Read Header

Read Fail?True

Error Read Fail

False

Compare read and writtenHeader

False

Error Compare Fail

True

Sha2Initialization

i=0; i<n_blocksTrue Write in QSPI one

Block Write Fail?

Error Write Fail

i++

Sha2 Finish andwrite at the end

of QSPI

Write Fail? Error Write Fail

False

True

Finish. Bitfile is in the QSPI

True

Read the writtenblock

Compare read and writtenblock

Error Compare Fail

False

False

True

False

Figure 3.9: Flow Chart for QSPI writing process Part II

44


FPGA PowerON

Power OnFail?

Faulty FPGA

return error

True

FPGA_nCONFIG = 1

False

FPGA_nSTATUS?

0

program_done=0Set all the errors

1

Read header,error?

Compare readMagic Number

False

False

Length ==0?

True

True

Number of Blocks == 0?

False

True

Start Configuration

False

True

ERROR -6

goto: Exit Config

ERROR -5

goto: Exit Config

ERROR -4

goto: Exit Config

ERROR -3

goto: Exit Config

ERROR -2

goto: Exit Config

Figure 3.10: Flow Chart for FPGA Configuration Part I

45


Start Configuration

Whileprogram_done = 0

and count>0

True

Try to ConfigureFPGA

count --

Test FPGA

Failed Test?

Exit Config

Disable FPGAProgramming

Some type oferrors?

FPGAprogrammedcorrectly

False

Faulty FPGA, SWITCH OFF!

ERROR -14

goto: Exit Config

False

continue

Break

True

False

True

Figure 3.11: Flow Chart for FPGA Configuration Part II

46


Total bytes =0 FPGA_nCONFIG=0

FPGA_nSTATUS?

FPGA_nCONFIG=1

FPGA_nSTATUS?

False

False

True

True

Try to ConfigureFPGA

count --

ERROR -7

goto: Exit Config

ERROR -8

goto: Exit Config

Write Blocksi++

For i=0;i<n_blocks

True

False

Compute Final Sha256, Read Sha from QSPI

FailedReading?

ERROR -11

goto: Exit Config

True

Compare readsha256

ERROR -12

goto: Exit Config

False

Exit_loop_n

False

True

Loop 1

Figure 3.12: Flow Chart for FPGA Configuration Part III

47


Exit_loop_n

count--

program_done==1?False

CONF_DONE_ok==1?

Retry! Continue

count==0?False

BreakCompleted

configuration butcontains error

Dummy cycle forinitialization

FPGA_nSTATUS== 1 or FPGA_CONF_DONE==1 ?

True Initialization is endedbut contains error

count=0, program_done=0

True

True

True

Break

Figure 3.13: Flow Chart for FPGA Configuration Part IV

48


Write Blocksi++

for n=0; n<512bytes

Read one block

FailedReading?

ERROR -10

goto: Exit Config

True

False

Write one byteinto the FPGA

i >=number_blocks program_done=0 goto: exit_loop_n Exit_loop_nFPGA_nSTATUS == 0?

True

Program_done = 1

False

True

False

Not yet finished n++

True

False

FPGA_CONF_DONE ==1? FPGA_INIT_DONE ==1? FPGA_CRC_ERROR ==1?

conf_done=1 conf_done=1 conf_done=1

True

Loop i++

Figure 3.14: Flow Chart for FPGA Configuration Part V

49


IP Address: 10.9.9.30 Gateway : 10.9.9.10

10.9.9.x/24.10

IP Address: 192.168.0.20 Gateway : 192.168.0.6

192.168.0.x/24.6

Board

Eth0 Eth1

Figure 3.15: Network configuration of the Devices

50

Chapter 4

Throughput Tests

4.1 Description of the test devices

Before the execution of the throughput tests, a detailed description focusing the attentionon the Ethernet interface architectures is performed, in order to compare in the section4.2 devices with similar architecture. In this way, consistent tests can be performed andconclusion can be made. The throughput tests are performed on a commercial board ofROJ company called SMARC Enuc ROJ board. It is an embedded board with the samemicroprocessor IMX6. A deeper analysis on the hardware architecture is performed tounderstand if the two machine can be compared.

4.1.1 Ethernet interface hardware architecture of ENA

In figure 4.1 is present the block diagram of the ethernet interface connections betweenthe physical connector and the IMX6 on the ENA board. The ENA Ethernet Interfaceis composed by two SFP Connectors used to connect Optical Fiber or RJ-45 wire (witha Converter). The Two SFP connectors are interfaced with the IMX6 with two differentchips. The Intel WGI210AS is a Gigabit Ethernet Controller that offers Physical LayerPort and SGMII/SerDes port that can be connected to an external PHY. It also supportsthe PCI Express. So in this case it is used to connect SFP port to the MicroprocessorIMX6 through PCI express. The second interface (red) is connected to a Marvell 88E1512.The Marvell Gigabit Ethernet transceiver is a physical layer device that containing a singletransceiver. It supports RGMII to SGMII/Fiber, SGMII to Copper. In this case it converta SGMII to RGMII and vice-versa. In this way it is possible to interface both SFP modulewith the microprocessor.

4.1.2 Ethernet interface hardware architecture of Smarc ROJ

In figure 4.2 the block diagram of the Ethernet interface architecture of the Smarc isrepresented. The SMARC ROJ Ethernet Interface is composed by two RJ-45 Connectorsused to connect copper wires. The Two RJ-45 connectors are interfaced with the IMX6with two different chips. The Intel WGI210AT is a Gigabit Ethernet Controller that offers

51

4 – Throughput Tests

SFPBlack

SFPRed

COM Express

Intel WGI210AS

Marvell 88E1512 MCIMX6D7CVT08AC

Carrier Board ENA-Main Board

SGMII_TX0+

SGMII_TX0-

SGMII_RX0+

SGMII_RX0-

MDI_2+

MID_2-

MDI_3+

MID_3-

PE_T+

PE_T-

PE_R+

PE_R-

PECLK+

PECLK-

WAKEn

SRTn

PCIe section

SGMII_TX1+

SGMII_TX1-

SGMII_RX1+

SGMII_RX1-

S_out+

S_out-

S_in+

S_in-

TxD[0-3]

RxD[0-3]

WAKEn

Rx_CTRL

RX_CLK

Tx_CLK

Tx_CTRL

RGMII section

Figure 4.1: Ethernet interface architecture of ENA

Physical Layer Port and SGMII/SerDes port that can be connected to an external PHY.It also supports the PCI Express. So in this case it is used to connect the RJ-45 port tothe Microprocessor IMX6 through PCI express. The second interface (red) is connectedto a KSZ 9031RNXIA. The KSZ is a gigabit Ethernet Transceiver that support RGMII.Itis possible to connect the RJ-45 Port to the RGMII IMX6 interface. The two boardsshare the same architecture interface from/to the IMX6. So, to continue the comparisonis necessary to analyse the differences into the software.

4.1.3 Software comparison

The SMARC ROJ is an enterprise product and the kernel is designed and installed bythe ROJ Company. The ENA kernel is designed by another external company. The firstsoftware analysis is performed writing in the console of both devices: uname -a. The twokernel version are shown:ENA: 4.1.29 armv7lSmarc ROJ: 4.9.11 armv7lIt is possible to compare the two kernel versions. Devices have two different kernel version4.1 and 4.19 . Due to the fact that they share the same microprocessor the version ofthe arm is v7l. Other information can be collected from the lspci command that showsall the PCI devices. Writing: lspci -nnk it is possible to compare the drivers of the twoIntel Gigabit controller. The two devices share the same family chip (Intel I210); theyhave two different codes (1533 for the SMARC and 1537 for the ENA) but has the samedriver. So, no difference between the two PCI interfaces are present. The drivers of theRGMII interfaces are write into the kernels; so because of the two kernels are different, the

52


RJ-45ETH2

RJ-45ETH1

Intel WGI210AT

KSZ 9031RNXIA MCIMX6S7CVM08AC

TD1+

TD1-

MDI_2+

MID_2-

MDI_3+

MID_3-

PE_T+

PE_T-

PE_R+

PE_R-

PECLK+

PECLK-

WAKEn

SRTn

PCIe section

TxD[0-3]

RxD[0-3]

WAKEn

Rx_CTRL

RX_CLK

Tx_CLK

Tx_CTRL

RGMII section

TD2+

TD2-

TD4-

TD4+

TD3+

TD3-

MDI_0+

MID_0-

MDI_1+

MID_1-

TD1+

TD1-

TD2+

TD2-

TD2+

TD4-

TD4+

TD3+

TD3-TxRx+_C

TxRx-_C

TxRx+D

TxRx-_D

TxRx+_A

TxRx-_A

TxRx+_B

TxRx-_B

SMARC ROJ

Figure 4.2: Ethernet interface architecture of Smarc ROJ

drivers of the ethernet interface connected through RGMII are different. So, in conclusion,the drivers of the two devices cannot be compared. They share the same microprocessor,the same hardware structure and the same drivers for the chip intel I210, but differentdrivers for the other two ethernet interfaces. Nevertheless, it is possible to compare theperformances of the two devices.

4.2 Throughput performance of Kernel IP Forwarding

One of the way to determine if a device can be used as network handling machine is toperform measures of its performance. There are different indicators to measure networkperformances like the latency and the throughput. In the examined cases, it is performeda UDP measuring network throughput. The UDP protocol is used to carry data over IPnetworks; it is not influenced by the time required to deliver the packets (the latency)because the sender will send a given number of packets per second. A network trafficanalyser Optiview XG is used to perform throughput analysis. The throughput is themaximum rate at which IP packets can be processed. It is measured as the number ofbits that can be processed in the unit of time (bps). In UDP throughput measures, themaximum transmission rate must be chosen. In those tests a speed of 100Mbps is set; so,the local tester sends 100 million of bits in one second. The test system is composed of twotest machine and a DUT (device under test). The DUT has to perform an IP forwarding,so it has to forward the packets that arrive from one port and send them through thesecond port. Three different devices are analysed: a general-purpose system, teh SmarcROJ Board and the designed board (ENA). During the test different sizes of packets are

53


sent. With a maximum fixed throughput and fixed size, it is possible to compute thenumber of packets that are sent in one second. The number of theoretical frames persecond are computed in equation 4.1:

fps = 100Mbps

8bit ∗ size(4.1)

The test system is in the figure 4.3

Figure 4.3: Test System

4.2.1 General Purpose Throughput test

The figure 4.4 represents the throughput rate. The local transmitter sends packet at100Mbps; the receiver of the remote tester receives the packets at different speed rate.Then the remote transmitter sends packets at 100Mbps and the local Rx receives thepackets at different rate. In the ideal case the data are sent and received at 100Mbps. Thetwo testers theoretically send and receive at the same rate. Two aspects have to be takeninto account: the symmetry and the rate. A good device for IP forwarding should have aperfect symmetry, so the received data from one side has to be the same of the receiveddata from the other side, and it should have the maximum throughput (100Mbps in thiscase). Not all the devices have the same performance, so it is necessary to test the differentdevices. A general purpose system is the best device for perform IP forwarding so it isused as reference for the different tests. In the second graph is represented the number ofpackets that are sent and received. This value is strictly related to the size of the packets.Fixed the frequency, the number of packets is inversely proportional to the size of thepacket. In fact if the packet is small, at 100 Mbps, it is sent higher number of packets.Also in this case an ideal device has to be symmetrical and has to send and receive themaximum number of packets. In the case of a general purpose system, the graph showsthat all the curves are superimposed, so it sends packets and receives approximately thesame number of packets. Data are in tables 4.1 and 4.2.From the table 4.2, smaller is thesize of the packet, much packets have to be sent at the same rate, so the device has tobe receive a higher value of packets in one seconds; for this reason with small packets theprobability that some packets are lost is higher than the case with high dimension packets.

54


64 128 256 512 1024 1280 1518

97

97.5

98

98.5

99

99.5

100

100.5

0 200 400 600 800 1000 1200 1400 1600

Mb

ps

Size (Bytes)

Throughput rate(Mbps)

Theoretical Rate

Local Tx

Remote Rx

Local Rx

Figure 4.4: General Purpose System Throughput Test

64

128

256

512

1024 1280 1518

0

20000

40000

60000

80000

100000

120000

140000

160000

0 200 400 600 800 1000 1200 1400 1600

Fram

es p

er

seco

nd

s

Size(Bytes)

Frames per seconds

Local Tx

Remote Rx

Remote Tx

Local Rx

Theoretical Curve

Figure 4.5: Packets vs Size Graph of General Purpose System

4.2.2 ROJ eNUC Throughput test

With the eNUC device, the throughput rate with small packets(64,128,256 Bytes) is lowerrespect the maximum rate; another problem is related to the symmetry of the two lines;in fact the remote device receives at higher rate respect the local receiver (figure 4.6). It ispossible to analyse also the frames that are sent and received. In light blue is represented

55


Table 4.1: Data of Throughput of General Porpose System in Mbps

Size(Bytes) Local Tx(Mbps)

Remote Rx(Mbps)

Remote Tx(Mpbs)

Local Rx(Mbps)

64 100.00 99.94 100.00 97.44128 100.00 100.00 100.00 100.00256 100.00 100.00 100.00 100.00512 100.00 100.00 100.00 100.001024 100.00 100.00 100.00 100.001280 100.00 100.00 100.00 100.001518 99.99 99.99 99.99 99.99

Table 4.2: Number of frames per second of General Porpose System

Size(Bytes) Local Tx Remote Rx Remote Tx Local Rx64 148808 148714 148810 144998

128 84458 84485 84459 84459256 45289 45289 45289 45289512 23496 23496 23496 234961024 11973 11973 11973 119731280 9615 9615 9615 96151518 8127 8127 8127 8127

the ideal curve(figure 4.7); so it is noticed that with small size packets the device is not ableto receive high number of packets, so it lost a lot of packets (higher then 50%). Data arepresent in the tables 4.3 and 4.4. From the data is possible to notice that the performancewith small size packets are very poor; packets of 64Bytes are received from the LocalRX at 190 Kbps, a very low rate compared of the maximum rate. So in conclusion, thecommercialized ROJ eNUC cannot be used as IP forwarder device with packets less then512 bytes.

Table 4.3: Data of Throughput of ROJ Smarc in Mbps


Remote Rx(Mbps)

Remote Tx(Mpbs)

Local Rx(Mbps)

64 100.00 22.14 100.00 0.19128 100.00 43.66 100.00 1.63256 100.00 79.07 99.99 3.88512 100.00 99.98 100.00 97.171024 100.00 100.00 99.99 99.991280 100.00 100.00 99.99 99.991518 100.00 100.00 100.00 100.00

56


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Figure 4.6: ROJ Smarc Throughput Test

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Figure 4.7: Packets vs Size Graph of ROJ Smarc

4.2.3 ENA Throughput test

The ENA device shows a very poor performance with packet dimension lower than 1024Bytes.(figure 4.8) The device is very slow with those packets and also shows a not goodsymmetry. The number of packets that are received are very few respect the theoreticalcurve (figure 4.9). The data are in the tables 4.5 and 4.6. It is possible to notice that theENA with packets less than 1024 , has a very poor performance; the data are received

57


Table 4.4: Number of frames per second of ROJ Smarc


128 84462 36877 84457 1378256 45291 35812 45287 1759512 23496 23492 23496 228301024 11973 11973 11972 119721280 9615 9615 9615 96151518 8127 8127 8127 8127

with throughput rate of Kilobit order, that is 3 order of magnitude less then the idealperformance.

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Figure 4.8: ENA Throughput Test

4.2.4 Performance Conclusions

The tests have shown different trends and performance using different devices. In the fol-lowing graph, a comparison between the three devices is performed. A worst-case analysisis done to consider the worst performance.In conclusion the ENA is the worst device toperform IP forwarding operations because it shows the worst trend respect of the idealcurve. The performance of the ENA are in line with the general purpose device only withpackets larger than 1280 bytes. At 1024 bytes the performance are acceptable (throughput:76 Mbps). A similar but better trend is shown in the eNUC device. So, the causes of theseperformance are probably due to some bugs into the microprocessor IMX6 kernel present

58


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Figure 4.9: Packets vs Size Graph of ENA

Table 4.5: Data of Throughput of ENA in Mbps


Remote Rx(Mbps)

Remote Tx(Mpbs)

Local Rx(Mbps)

64 100.00 0.80 60.03 0.0603128 100.00 4.56 80.05 0.1407256 100.00 28.93 100.00 0.3425512 100.00 51.50 100.00 0.35201024 100.00 100.00 99.99 76.08001280 100.00 100.00 99.99 99.991518 99.99 99.99 99.99 99.99

Table 4.6: Number of frames per second of ENA


128 84460 3849 67609 119256 45290 13104 45289 155512 23496 12100 23496 831024 11973 11973 11973 91101280 9615 9615 9615 96151518 8127 8127 8127 8127

59


in both devices (ENA and eNUC). So from now on, it is considered to work only withpackets of big size (1024,1280,1518) and relative considerations are done in this situation.

64 Bytes

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Figure 4.10: Comparison Throughput test

4.3 Throughput performance with application IP Forward-ing

In this section, throughput performance are done with the user space application. Theapplication performs an Ip Forwarding at higher level respect the Kernel level. The ap-plication open sockets at user space level and forward the packets that arrive from oneinterface to the other. For a consistent analysis, it is performed tests in these conditions,before adding the write and reading operations on the FPGA( for encrypt and decryptthe packets). From figure 4.12 it is possible to notice the throughput, with packet size thatchanges and the maximum throughput that is fixed at 100Mbps. It is possible to noticea not uniform trend. One of the cause of this trend is due to the fact that each packetthat arrives has to be collected from the kernel and has to be sent to the user space levelwhere the packet is managed and is forwarded to the second interface. These operationstakes time and reduce consistently the throughput. Smaller is the packet, at 100Mbps,higher is the number of packets that the CPU has to process; in fact a better performance

60


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Figure 4.11: Comparison Packets vs Size Graph

are achieved when the packets are bigger. So if packets with size higher than 1024 byteare considered, a maximum throughput of 68Mbps is achieved. This means that the realthroughput of the ENA cannot overcome this value, so with the FPGA that encrypts anddecrypts packets, lower values are expected. From the figure 4.13 it is possible to analysethe number of packets that are received. With small packets, the number of packets thatthe CPU has to be handle is so high that it is not able to manage all packets , so thenumber of packets per second that the second interface receives, respect the number ofpackets that are sent, dramatically drops. Better performance are achieved with biggerpackets. Here due to the dimension of packets, that is higher, the number of packets thatthe CPU has to be handled is lower, so the number of received packets per second is higher.In tables 4.7 and 4.8 values of the test performance are represented.

4.4 Throughput performance with Encrypting and Decrypt-ing application

In this section the throughput of the ENA with the Encrypting and Decrypting functionenabled is performed. When a packet arrives, it is collected by the kernel, it is sent to theuser space level and it is encrypted by the FPGA. The FPGA has a 16 bits bus connectedto the IMX so to perform all the operation a consistent number of operations the CPUand the FPGA have to perform, so, this takes time. The throughput is high influenced bythis required time. In figure 4.14 is present the test throughput of the machine. With small

61


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Figure 4.12: Throughput Test of ENA with IP forwarding application

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Figure 4.13: Packets vs Size Graph of ENA with IP forwarding application

62


Table 4.7: Data of Throughput of ENA with IP forwarding application in Mbps


Remote Rx(Mbps)

Remote Tx(Mpbs)

Local Rx(Mbps)

64 100.00 0.0086 100.00 0.0074128 100.00 0.0150 100.00 0.0126256 100.00 0.0244 100.00 0.0230512 100.00 0.0243 100.00 0.01831024 100.00 69.6300 100.00 79.21001280 100.00 36.5600 100.00 38.49001518 100.00 67.4500 100.00 59.3900

Table 4.8: Number of frames per second of ENA with IP forwarding application


128 84477 13 84454 11256 45292 11 45288 10512 23497 6 23495 41024 11973 8337 9615 37011280 9615 3515 9615 37011518 8128 5482 8126 4827

size packets, the CPU has to handle high number of packets so the throughput drops 6order of magnitude lower that the maximum throughput (100Mbps). If it is considered themaximum speed that is reached with 1518 byte packets, it is lower than the throughput,in the same condition, of the application without the Encrypting function. A reduction ofabout 88% is reached; this is caused mainly due to the high time to perform the encryptionof big size packets. From the figure 4.15 it is possible to notice that the number of packetsthat the machine is able to process is very low respect the theoretical value(equal tothe Local Tx sent packets). In tables 4.9 and 4.10 the test throughput performance arerepresented.

4.5 Comparison between ENA with IP Forwarding applica-tion and Encrypting/Decrypting Application

In this section a deeper analysis of the performance of the ENA is performed. Until now, itis imposed a fixed maximum throughput of 100Mbps; so the packets are sent to the ENAat 100Mbps. Now, the maximum throughput is sweeped. So changing the Throughput, itis possible to draw a graph and some final considerations can be done. For each packetsize it is sweeped the throughput starting from small value (1 Mbps). A fixed throughputis selected and the received throughput is computed. The small packet size are present in

63


0.0075

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Figure 4.14: Throughput Test of ENA with Encrypting and Decrypting application

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Figure 4.15: Packets vs Size Graph of ENA with Encrypting and Decrypting application

table for completeness but due to the fact that with those packet sizes the results are verypoor, the analysis is deeper focused on bigger sizes (1024, 1280, 1518)bytes. When thethroughput is low, the machine is able to encrypt and decrypt correctly the informations,so applying for instance, 2 Mbps the encrypted data are received at 2Mbps. So a theory lineis a straight line that in a xy axis has the function y = x. But increasing the throughput

64


Table 4.9: Data of Throughput of ENA with Encrypting and Decrypting application inMbps


Remote Rx(Mbps)

Remote Tx(Mpbs)

Local Rx(Mbps)

64 100.00 0.0100 100.00 0.0075128 100.00 0.0163 100.00 0.0132256 100.00 0.0256 100.00 0.0240512 100.00 0.0238 100.00 0.01921024 100.00 2.0880 100.00 2.10301280 100.00 4.8120 99.99 4.81701518 100.00 7.8670 99.99 7.8630

Table 4.10: Number of frames per second of ENA with encrypting and decrypting appli-cation


128 2533847 412 2533677 335256 1358749 348 1358657 326512 704924 168 74876 1351024 359211 7499 359192 75531280 288459 13880 288451 138941518 243817 19181 243799 19171

the number of packets that are sent (fixing the size) increasing too; furthermore, withsmall packet dimension, the number of packets that has to be processed, is higher respectthe number of packets of bigger packet size. So the performances of small packet is verypoor. Considering for instance, a size of 128 Bytes from the figure 4.16 is possible to noticethat at very low throughput the system is able to encrypt the data but above 4Mbps, theperformance start to drop and after about linear decrease, the system is able to receive verysmall packets per second(in order of units). Increasing the size of packets, the situationgets better. With the biggest packet size (1518 byte) the maximum throughput peak is atabout 15Mbps but the maximum throughput is 20Mbps, so a loss of 22.3% of packets isshown. This loss is too high so the maximum acceptable throughput is at about 15Mbpswhere the losses are less then 2.5%. After a peak, each curve drops; in theory, after thepeak, the curve has to saturate at the peak value because even if the throughput increases,the CPU of IMX6 is able to handle only packets with the maximum peak throughput, butthis doesn’t happen. The causes are different and other analysis and graphs are realized.

One of the possible causes of this decreasing trend, can be attributed to the necessarytime to perform the Encrypting operation through the FPGA, so an analysis with thesweep of throughput also with the IP Forwarding application without the Encrypting andDecrypting application is performed and a comparison is made. In figure 4.17 the Sweep

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Figure 4.16: Sweep Throughput Test of ENA with Encrypting and Decrypting application

throughput test of the ENA with the IP forwarding application and with the Encryptingapplication is represented. Some considerations can be done considering the trends. Withlow throughputs, the system is able to process all informations and encrypt the data; inthis case the speed for encrypting the data is not the limiter. Increasing the throughput,the number of packets that have to manage, increases, so the FPGA has to manage a lotof packets in small time, for this reason after a throughput value of 15Mbps , the machineis not able to perform the encryption process faster so, comparing the trend of the IPForwarding application is possible to notice that after 15Mbps the FPGA computationis the "bottleneck" of the system.It is possible to see in figure 4.18 a zoom that betterexplains the trend. In fact the IP forwarding application reaches higher performance alsoabove 15 Mbps. However both applications has a similar trend, in fact, after their peak,the throughput drops down. This cause is because the CPU is not able to manage so highpackets and due to limits in internal buffer dimension, interrupt kernel management, andother types of process that cannot be managed at user space level.

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Figure 4.17: Comparison between Throughput test of IP Forwarding Application andEncrypting Application

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Figure 4.18: Zoom of comparison between Throughput test of IP Forwarding Applicationand Encrypting Application

67

Chapter 5

Conclusion

Thanks to the throughput tests, it is possible, in conclusion, to analyse the results andthe final specification of the product, so, it is possible to highlight the limits of the mi-croprocessor and all the restrictions. All the results are summarized and discussed in thissection. The final goal of the system is reached after some intermediate steps. The firststep is performed to declare and find the maximum physical throughput that the ENA canreach. So a throughput test with IP forwarding is performed and a comparison with othercommercial system is done. Before this, a comparison is made between the ENA and thecommercial ROJ Smarc to perform consistent tests. It is discovered that the two machinesare similar and have the same hardware network interfaces but two different Linux Kernel.So, the IP forwarding is performed and throughput tests are executed.It is discovered that a general purpose system is the best machine to perform network op-erations related to IP communication protocols and it is the best way to handle Ethernetframes and forward them. In fact, with a maximum throughput of 100 Mbps, it is able toforward all packets, without losses, and the packets are received from the Test machine at100 Mbps.After that, it is performed throughput tests on a commercial embedded system called ROJEnuc Smarc. The performance of ROJ Enuc are lower than the general purpose system.The number of small packets(up to 256byte) at 100Mbps are higher respect bigger packetsize, so the system has to handle higher number of frames, for this reason the system is notable to forward all the packets and at the receiver the number of packets are less. So theperformance are very poor, with a losses higher than 96% with packet size less than 256byte. The 100 Mbps are reached with packets size equal and higher than 512byte. Withpackets of 512 byte all the packets are received without losses.Thanks to this results, it ispossible to understand and forecast the trends of the ENA due to the similarity with theROJ device.The last test with Kernel IP forwarding is performed on the ENA device. The 100 Mbpsof maximum throughput is reached only with packets equal and higher than 1024 byte. Inthis condition all the packets are received and there are no losses, but a not symmetricaltrend is shown. In fact, the receiver of the local machine test, receives lower packets, andconsistent losses are found (24% of losses). So acceptable performance are reached only

68

5 – Conclusion

with packets higher than 1280byte where the two receivers are symmetrical and there areno transmission losses. In conclusion, with the first throughput test step, it is possible tofix the minimum frame size that the system is able to handle. So the next tests are focusedmainly on packets with size higher than 1280byte.The second step is the introduction of the application at user space that handles theEthernet frames. In this situation the CPU has to manage packets that arrives and fromthe kernel level has to send them at user space level. These operations take time and theperformance consistently reduces. With 1024 byte packet size, a maximum throughput of68 Mbps is achieved. This value fixed the maximum throughput that the ENA with IPforwarding application is able to manage. So it is expected that the maximum throughputwith the Encryption and the decryption of the packets is less than this value.The last step is the final application that allows to encrypt or decrypt the Ethernet framesthat arrive. The packets are collected from the kernel, after the opening of the socket, theyare saved into a buffer and send into the FPGA. Due to the 16-bit bus between the micro-processor and the FPGA, the frame have to be sent 16-bit at time; this operation requirestime that lowers the maximum throughput. With small packets, despite of their size, soless number of read/write operations in the FPGA for one complete frame, the number ofpackets is higher, so the performance are very lower, not sufficient. The maximum through-put reachable is 7.8 Mbps. So this is the real received throughput that the system reaches.In this condition, however, the losses are very high, due to the fact that the packets aresent at 100 Mbps and are received at 7.8 Mbps. So a final analysis is performed.In this last tests, the packets are sent not at fixed frequency of 100 Mpbs but at variablethroughput. In this way it is possible to understand the maximum throughput where thereare no losses. A sweep test is performed starting from 1 Mbps. With low throughput, themachine is able to encrypt and decrypt correctly the information. For instance, with 2Mbps the data are received at 2 Mbps without losses. So a theory trend is a straight line.However, increasing the throughput, the number of frame increases and with small pack-ets(so, high number of packets), the performance starts to drop. A better trend is shownwith big size packets, but, at a certain throughput point, the performance dramaticallydrops. The maximum throughput with no losses is 15Mbps, after this value the losses startto begin consistent and the performance drops. The same tests are performed on the ENAwith IP forwarding application without the encryption and it is possible to notice thatthe maximum peak is at about 60Mbps;so, the system has better performance. Thanksto this measurements, it is possible to understand that the FPGA computation is the"bottleneck" of the system. However after a peak, both trends start to drop. In theory,after the peak, the curve saturates at that value, but this no happens, because with highthroughput the number of packet frames is so high that the CPU is not able to manageall these informations and drops.So, at the end, it is possible to assert that the maximum throughput that the machineis able to manage is 15 Mbps with 1518 byte packet size. Thanks to this work, it hasbeen possible to highlight the limits of the microprocessor and, although with the currentrestriction of the ENA could not be suitable for being an enterprise product, it representsa good proof of the concept of how deeply military companies have to deal with the topicof encryption of information for security applications.

69

Appendix A

Open SystemInterconnection/InternationalStandard Organization

Open System Interconnection/International Standard Organization(OSI/ISO) is a modelthat standardizes the communication functions to ensure a compatible national and world-wide data communication. In this model, there are several partitions called abstractionlayers. It is a seven layer architecture that defines a complete system. The different levelsare:

1. Physical Layer

2. Datalink Layer

3. Network Layer

4. Transport Layer

5. Session Layer

6. Presentation Layer

7. Application Layer

• The Physical Layer is the lowest layer of the model, in fact, it defines the electrical,optical and all the physical specifications. So it includes medium(optical fiber,coaxialcable), pins, voltages, line impedence, signal timing, frequency,ecc. The transmissioncan be simplex, half duplex or full duplex(allows communications in both directions).

• The Datalink Layer synchronizes the information. So its main function is to makesure that there aren’t errors in the physical layer. The data frames that are trans-mitted and received are managed by this layer. It is divided in two sublayers:

70

A – Open System Interconnection/International Standard Organization

– Logical link control(LLC) layer, that is the upper sublayer. It provides a mech-anism in order that different protocols can exist together and to transport theinformation onto the same medium. It also provides the flow control and therequest errors. The LLC is also an interface between the Media Access Con-trol(MAC) and the Network upper layer.

– Medium access control(MAC) layer: In this layer, the MAC provides channelaccess control; so it ensures that signals sent from different points across thesame channel don’t collide. To do this, MAC protocol is used; it assigns a uniqueidentifier number that is assigned to all ports on a switch. The MAC address isan hexadecimal number(6 byte) that is divided into different parts in specificformats.

• The Network Layer provides the procedure to transfer different data sequences fromone node to another; it acts as a network, managing the traffic. It also dividesthe messages into packets. It chooses the best path for each message to arrive atdestination.

• Transport Layer provides services for the transport of data. It has the task to openand close the communications, to split the messages in smaller units that pas on thenetwork layer, decides if the data transmission should be on parallel or single andhandles the multiple connections.

• The Session layer controls and manages the conversation between computers. Itensures that the messages are not cut or data are not lost. So its main task is tocarry out a session.

• Presentation Layer takes care that the information is sent in a "good way", so thatthe receiver will understand the information and is able to use it. So it is able toprovide independent data compared to different representation by translating theinformation.

• Application Layer is the topmost layer. It interacts with the software applicationsthat implement the communication for example an email service software.

71

Appendix B

IP-Internet Protocol

B.1 Overview and main characteristicsThe Internet Protocol (IP) is a network protocol included into the TCP/IP protocolSuite;so it is a set of rules to exchanging messages across a series of interconnected net-works. It is the main Inter-Networking Protocol of the layer 3 of the ISO/OSI model. Itis a simple protocol based on connectionless packets and best-effort type. It is not reli-able so it doesn’t ensure any type of communication reliability in terms of error checkingand flow control. The packet sent can be lost, duplicated or delayed but the IP protocoldoesn’t inform both receiver and transmitter. It is connectionless, this means that everypacket is processed independently by other packets. So for example different packets withthe same transmitter and receiver can proceed with different path and can be received ornot. The first major protocol is the IPv4; there is also a new version, IPv6 that tries tosolve the principal limitations of the IPv4 protocol like the number of IP address, thatare almost not-sufficient but the IPv6 reaches nowadays 20% of the internet traffic, so theIPv4 remains the most used. The most important functions that the IP protocol performsare:

• It distinguishes every host that is a network card with an identifier, called IP address.A single (unicast) IP address identifies a single host, but a single host can have manyunicast IP, according to the number of network cards. For example a router has manyaddresses because it is a sorting centre with different network cards.

• It receives the data (in form of PDU-Protocol Data Unit) from the Transport Layer(layer 4).

• It encapsulates each PDU in different packets with a maximum dimension and addsan header.

• It splits the packets during the transport to insert them into layer 2.

• It routes the packets on the network.

• It identifies the errors, but it doesn’t correct them.

72

B – IP-Internet Protocol

• It extracts the data (PDU) from the Transport Layer.

• It delivers the data to the transport layer in the order in which they arrived atdestination, that can be different from the departure order.

B.2 IPv4 packetEvery IP packet is composed by a header and a data section that is the portion of datato be sent. An IP packet(IPv4) has:

• a fixed part of 20 bytes;

• a second optional part with variable length, but it must be a multiple of 4 byte.

It is structured as follows:

• Version: it is the first header field of 4 bits and it indicates the version of the protocolIP that has generated the packet. It is used by the receiver to understand the typeof format of the packet.

• HLEN (4 bits): it indicates the length of the header IP in a word of 4 bytes. Theheader fields have a fixed length, except for the Options field that can vary.

• Type of Service (8 bit): it indicates the type of the transport that is needed to therouter by decide a priority.

• Total Length (16 bits): it indicates the total length of the packet expressed in byte.Often the routers don’t use this field.

• Identification (16 bits): it is used to identify the fragments of a single IP datagram.This happens when a packet is split into different packets.

• Flags (3 bits): it is used to control and identify the fragments.

• Fragment Offset (13 bits): it indicates the number of bytes of data that are presentin the previous packet. If the fragment is the first the field is 0.

• Time to Live (8 bits): it is a time that indicates the living time of a packet, afterthat time, the packet can be rejected. The value is initialized at 255 from the senderhost. Every time that the packet is processed by a router, time is decremented by 1unit. It avoids an infinity loop inside a network.

• Protocol (8 bits): it indicates the type of the transported data, that is the type ofprotocol of layer 4.

• Header Checksum (16 bits): it verifies the integrity of the header when it arrives todestination.

• Source IP (32 bits): it contains the IP address of the source

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B – IP-Internet Protocol

• Destination IP (32 bits): it contains the IP address of the final destination of the IPdatagram.

• Options: it is not often used. It is a variable length field and due to the fact that thefield must have a fixed multiple length of 4 bytes, it is used to complete the packetwith the padding.

74

Appendix C

Secure Hash Algorithm

The term SHA is the acronym of Secure Hash Algorithm and it is a family of five differentcryptographic hash functions. The SHA produces a digest message that is a sort of digitalprint of the message, that has a fixed length even if the message is not fixed. The mainfeature is that it is a non reversible function. So, it is not possible to know the originalmessage knowing only this data. It has also the feature that it is no possible to generate twodifferent message with the same digest. The algorithms are SHA-1, SHA-224, SHA-256,SHA-384 and SHA-512. The last four algorithms are indicated as SHA-2. The differencebetween the different SHA is in the number of bits of the digest. A message is processedby blocks of 512 and it requires 64 rounds to be compute. The SHA is used mainly todiscover if a data was corrupted.

75

Appendix D

Networking

Internetworking is "the concept of interconnecting different types of networks to build alarge, global network"[19], in this way any pair of host can exchange packets and cancommunicate. Internet is a set of networks connected by routers that are configured insuch that the traffic pass among any computers that are attached to the network. Todaymillions of computers are connected world-wide. To create a network: a stardard schemeis needed to address the packets to any host; then a standardized protocol that defines theformat and handles the transimitted packets is needed and a components that routes thepackets to their destination. The smallest network is formed by two LANs of computersthat are connected to each other via router. A Local area network(LAN) is a network thatinterconnects computer in a limited area. The internet protocol is designed to providea not guaranteed packet service. To transfer the data, the applications must utilize anappropriate protocol such as the TCP(Transmission Control Protocol) that is a reliableprotocol(so guaranteed transmission) or the use of UDP(User Datagram Protocol) thatis a connection-less transport protocol, used principally for data that require real-timeservice like voice or video streaming. Each host and router is defined through addresswith fixed length, that are grouped in IP network. An IP address has a fixed length of 32bit. They are written in sequence of four decimal number with values from 0 to 255 andseparated by a dot. The address identifies the interconnection point of one host with anet. But with an address it is possible to identify not an host but one of its interface. soOne host can have more than one IP address like in the designed board. The IP addressis subdivided in two parts:- Network ID : it is a prefix that identifies the network;-Host ID : it identifies the host interface.The Network ID occupies the left part of the address and te Host ID the right part. TheNet-ID can have different dimensions and Classes are defined to differentiate the networks.Different classes of addresses are present:

• A class : The Net-ID that identifies an IP network has the first decimal numberfixed. So it is possible to index numbers from 0.0.0.0 to 127.255.255.255.

• B class : Addresses from 128.0.0.0 to 191.255.255.255

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D – Networking

• C class: From 192.0.0.0 to 223.255.255.255

• D class: From 224.0.0.0 to 239.255.255.255

• E class: From 240.0.0.0 to 255.255.255.255

It is possible to decide locally a sub-ripartition of the NET/Host ID. So it is possible tofragment the Host ID in two parts:- The first part identifies the subnet;- The second part identifies each interface host of the subnet;For th subdivision it is necessary to use the Netmask; it must be configured to route theIP address correctly. For example if it is used a network of B class (ex: 192.168.0.0) itis possible to use the first byte of the Host-Id as subnet index ; in this way from thenetwork of B class it is possible to extract 254 network of C Class dimension. To do thisa netmask of 255.255.255.0 is used. The netmask is used to identify its own NET-ID fromthe IP address. The subnetting is identifies using a specific notation: IP Address/(Net-IDdimension + Subnet-ID). For example 192.168.5.0/24. Each packet that travels has to beroute, so the routers create a structure: in this way a datagram passes from one to anotherrouter until it reaches the destination.

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Bibliography

[1] ALTERA. Cyclone IV Device Handbook, Volume 1. Version Rev 2.0. 2016. url:https://www.altera.com/en_US/pdfs/literature/hb/cyclone-iv/cyclone4-handbook.pdf (cit. on p. 21).

[2] William Fornaciari Carlo Brandolese. “Sistemi Embedded - Caratteristiche, tec-nologie e mercato”. In: Mondo Digitale 3 (2009), pp. 3–10. url: https://home.deib.polimi.it/fornacia/lib/exe/fetch.php?media=papers:2009:2009_mondodigitale_embedded_p_3_10.pdf (cit. on p. 3).

[3] Micron. Micron Serial NOR Flash Memory Reference manual. Version Rev B. 2014.url: https://www.micron.com/resource-details/2dd46e97-8a6c-4ed2-81c8-7d77528076c2.

[4] [Online]. url: https://www.ic3.gov/media/annualreports.aspx (cit. on p. 1).[5] [Online]. url: https://www.zionmarketresearch.com/news/embedded-systems-

market (cit. on p. 4).[6] [Online]. url: https://en.wikipedia.org/wiki/ARM_architecture.[7] [Online]. url: http://www.st.com/en/microcontrollers/stm32f7x6.html?

querycriteria=productId=LN1902.[8] [Online]. url: https://developer.arm.com/products/processors/cortex-

m/cortex-m7.[9] [Online]. url: https://en.wikipedia.org/wiki/ARM_Cortex-A.

[10] [Online]. url: https://en.wikipedia.org/wiki/Small_form-factor_pluggable_transceiver.

[11] [Online]. url: https://en.wikipedia.org/wiki/Ethernet#Frame_structure.[12] [Online]. url: https://en.wikipedia.org/wiki/OSI_model.[13] [Online]. url: https://en.wikipedia.org/wiki/IPv4.[14] [Online]. url: https://en.wikipedia.org/wiki/Microcontroller.[15] [Online]. url: https://www.eleccircuit.com/why-use-microcontroller/.[16] [Online]. url: https://www.elprocus.com/embedded- systems- real- time-

applications/.[17] [Online]. url: https://en.wikipedia.org/wiki/Internet_Protocol.

78

https://www.altera.com/en_US/pdfs/literature/hb/cyclone-iv/cyclone4-handbook.pdf

https://www.altera.com/en_US/pdfs/literature/hb/cyclone-iv/cyclone4-handbook.pdf

https://home.deib.polimi.it/fornacia/lib/exe/fetch.php?media=papers:2009:2009_mondodigitale_embedded_p_3_10.pdf



https://www.micron.com/resource-details/2dd46e97-8a6c-4ed2-81c8-7d77528076c2

https://www.micron.com/resource-details/2dd46e97-8a6c-4ed2-81c8-7d77528076c2

https://www.ic3.gov/media/annualreports.aspx

https://www.zionmarketresearch.com/news/embedded-systems-market

https://www.zionmarketresearch.com/news/embedded-systems-market

https://en.wikipedia.org/wiki/ARM_architecture

http://www.st.com/en/microcontrollers/stm32f7x6.html?querycriteria=productId=LN1902

http://www.st.com/en/microcontrollers/stm32f7x6.html?querycriteria=productId=LN1902

https://developer.arm.com/products/processors/cortex-m/cortex-m7

https://developer.arm.com/products/processors/cortex-m/cortex-m7

https://en.wikipedia.org/wiki/ARM_Cortex-A

https://en.wikipedia.org/wiki/Small_form-factor_pluggable_transceiver

https://en.wikipedia.org/wiki/Small_form-factor_pluggable_transceiver

https://en.wikipedia.org/wiki/Ethernet#Frame_structure

https://en.wikipedia.org/wiki/OSI_model

https://en.wikipedia.org/wiki/IPv4

https://en.wikipedia.org/wiki/Microcontroller

https://www.eleccircuit.com/why-use-microcontroller/

https://www.elprocus.com/embedded-systems-real-time-applications/

https://www.elprocus.com/embedded-systems-real-time-applications/

https://en.wikipedia.org/wiki/Internet_Protocol

BIBLIOGRAPHY

[18] [Online]. url: https://en.wikipedia.org/wiki/Internetworking.[19] Bruce S. Peterson Larry L.; Davie. Computer Networks: a systems approach. Ed. by

Anche Leggoo. Elsevier, Inc., 2012 (cit. on p. 76).[20] NXP Semiconductors. i.Mx 6Quad applications Processors for Industial Products.

Version Rev 5.0. 2017. url: https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-6-processors/i.mx-6quad-processors-high-performance-3d-graphics-hd-video-arm-cortex-a9-core:i.MX6Q (cit. on p. 19).

[21] STMicroelectronics. STM32F756xxx Reference manual. Version Rev 1. url: https://www.st.com (cit. on pp. 12, 13, 15–17).

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https://en.wikipedia.org/wiki/Internetworking

https://www.nxp.com/products/processors-and-microcontrollers/applications-processors/i.mx-applications-processors/i.mx-6-processors/i.mx-6quad-processors-high-performance-3d-graphics-hd-video-arm-cortex-a9-core:i.MX6Q




https://www.st.com

https://www.st.com

Documents

Development of an embedded system for networking applications · An embedded system is a system where diﬀerent areas work together; it integrates hardware circuitry with software