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1 | Energy Efficiency and Renewable Energy eere.energy.gov DOE “Big Idea” concept proposed by DOE Labs March 06, 2017 NICE Workshop at IBM Research-Almaden Dev Shenoy Chief Engineer Advanced Manufacturing Office www.manufacturing.energy.gov

Dev Shenoy DOE “Big Idea” concept Chief Engineer proposed ... · • Petabit cm-2 Densities • Replaces DRAM & flash •

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Page 1: Dev Shenoy DOE “Big Idea” concept Chief Engineer proposed ... · • Petabit cm-2 Densities • Replaces DRAM & flash •

1 | Energy Efficiency and Renewable Energy eere.energy.gov

DOE “Big Idea” concept proposed by DOE LabsMarch 06, 2017NICE Workshop at IBM Research-Almaden

Dev ShenoyChief EngineerAdvanced Manufacturing Officewww.manufacturing.energy.gov

Page 2: Dev Shenoy DOE “Big Idea” concept Chief Engineer proposed ... · • Petabit cm-2 Densities • Replaces DRAM & flash •

0

2000

4000

6000

8000

10000

2000 2005 2010 2015 2020 2025 2030

TWHr

Year

Projection based on consumer electronics + data centers

IT challenge for future electricity supply

Do NothingEnergy ~ 100Pj/op

New Moore scalingIn 20 yrsEnergy = 20fj/opIT=30-40% growth

New Moore scaling in 10 yrsEnergy = 20fj/opIT=hold to 8%

www.alliancetrustinvestments.com/sri-hub/posts/Energy-efficient-data-centreswww.iea.org/publications/freepublications/publication/gigawatts2009.pdf

Page 3: Dev Shenoy DOE “Big Idea” concept Chief Engineer proposed ... · • Petabit cm-2 Densities • Replaces DRAM & flash •

Beyond Moore Co-design FrameworkModeling

Atomistic and Ab-Initio Modeling• DFT – VASP, Socorro• MD – LAMMPS

Circuit/IP Block Design and Modeling• SPICE/Xyce model

Compact Device Models• Single device electrical models• Variability and corner models

Device Physics Modeling• Device physics modeling (TCAD)• Electron transport, ion transport• Magnetic properties

10,000x improvement: 20 fJ per instruction equivalent Experimental

Microarchitecture Models• McPAT, CACTI, NVSIM, gem5

Computer System Architecture Modeling • Next generation of Structural Simulation Toolkit• Heterogeneous systems HPC models

Algorithms and Software Environments• Application Performance Modeling

Process Module Modeling• Diffusion, etch, implant • Simulation• EUV and novel lithography models

On Chip Universal Memory:• Stacked ReRAM • Petabit cm-2 Densities• Replaces DRAM & flash• <1 pJ per write/read

Silicon

On Chip Memristor Accelerator:• Vector or matrix operations• fJs per operation On Chip Photonics

• Chip to chip communication • <1 pJ per bit transfer

High Performance Logic:• TFET, NcgFET

To next node

x2

x2

x2

x2

w1,1

w2,1

w3,1

w4,1

w1,2

w2,2

w3,2

w4,2

w2,x

w2,x

w3,x

w4,x

...

...

...

...

++++

--

--

--

++

VTE

+

++

+

+

--

+

++++

+ +

--

--

-

PtTaOxTa

Algorithms &

SW

Environments

Hardware &

Circuit Architectures

Comm

., Mem

ory &

Computation Devices

Materials

Component Fabrication • Processors, ASICs• Photonics• Memory

Device Measurements• Single device electrical behavior• Parametric variability

Device Structure Integration and Demonstration• Novel device structure

demonstration

Process Module Demonstrations• EUV and novel lithography• Diffusion, etch, implant simulation

Test Circuit Fab and Measurement• Subcircuit measurement

Fundamental Materials Science• Understanding Properties/Defects via

Electron, Photon, & Scanning Probes• Novel Materials Synthesis

Example activities within a MCF

Page 4: Dev Shenoy DOE “Big Idea” concept Chief Engineer proposed ... · • Petabit cm-2 Densities • Replaces DRAM & flash •

4

Microelectronics:

1) Beyond von-Neumann architectures

2) Clear industry value proposition

3) Strong Partnerships

4) Ability to address critical challenges

5) A balanced portfolio of projects

Industry-Academia-Government Partnership

Open Consortium—new members able to join