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Design of a Simple Customizable Microprocessor. SIMP – A Simple Customizable Microprocessor* Basic Features A Load/Store Machine , with each Instruction Cycle of 4 Machine (Clock) Cycles, 16-bit Data Bus, 12-bit Address Bus - PowerPoint PPT Presentation
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NDG-L37-41 Introduction to ASIC Design 1
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
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al S
yste
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roto
typi
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SIMP – A Simple Customizable Microprocessor* Basic Features
A Load/Store Machine, with each Instruction Cycle of 4 Machine (Clock) Cycles,
16-bit Data Bus, 12-bit Address Bus Two 16-bit Working Registers, A and B, Directly
Accessible to the Programmer Memory-Mapped I/O Operations All Data Transformations are Performed in Working
Registers Supports “Direct Access”, “Implicit” and “Stack”
Addressing Modes Custom Defined Instructions and Functional Blocks
NDG-L37-41 Introduction to ASIC Design 2
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
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SIMP – A Simple Customizable Microprocessor* - Cont’d Programmable Model – User Directly Accessible Registers
Invisible Registers: PC, SP, TEMP, and ST
Fig-01: SIMP Programming Model
NDG-L37-41 Introduction to ASIC Design 3
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
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15,
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SIMP – A Simple Customizable Microprocessor* - Cont’d Instruction Set and Instruction Format – All Instructions are
16-bit wide (One Memory Word) Direct Addressing Mode: 4 MSBs represent OPCODE
and 12 LSBs represent Memory Address
Implicit or Stack Addressing Mode -
OPCODE(4) ADDRESS(12)
OPCODE(8) NOT USED(8)
NDG-L37-41 Introduction to ASIC Design 4
(cont’d)
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
igit
al S
yste
m D
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d P
roto
typi
ng”
SIMP – A Simple Customizable Microprocessor* - Cont’d Instruction Set and Instruction Format – Cont’d
NDG-L37-41 Introduction to ASIC Design 5
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
igit
al S
yste
m D
esig
n an
d P
roto
typi
ng”
SIMP – A Simple Customizable Microprocessor* - Cont’d Instruction Set and Instruction Format – Cont’d
Memory Reference Instructions – Direct or Stack Addressing Mode (Depending on Bit-15)
NDG-L37-41 Introduction to ASIC Design 6
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
igit
al S
yste
m D
esig
n an
d P
roto
typi
ng”
SIMP – A Simple Customizable Microprocessor* - Cont’d Instruction Set and Instruction Format – Cont’d
Other SIMP Core Instructions – All Implicit Mode
NDG-L37-41 Introduction to ASIC Design 7
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
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15,
“D
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SIMP – A Simple Customizable Microprocessor* - Cont’d SIMP DatapathFig-02: SIMP Datapath
NDG-L37-41 Introduction to ASIC Design 8
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
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m D
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typi
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SIMP – A Simple Customizable Microprocessor* - Cont’d SIMP Control Flow – Fetch (T0/T1), Decode (T2),
Execute (T3)
Fig-03: SIMP Control Flow Diagram
NDG-L37-41 Introduction to ASIC Design 9
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
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al S
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m D
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SIMP – A Simple Customizable Microprocessor* - Cont’d SIMP Instruction Execution FlowchartFig-04: Instruction Execution Cycle
NDG-L37-41 Introduction to ASIC Design 10
Design of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable MicroprocessorDesign of a Simple Customizable Microprocessor
* C
hapt
er 7
and
15,
“D
igit
al S
yste
m D
esig
n an
d P
roto
typi
ng”
SIMP – A Simple Customizable Microprocessor* - Cont’d SIMP Implementation – Datapath + Control Unit
Datapath consists of all registers + interconnect structures (such as Muxes) and ALU etc.
Control Unit provides proper timing, sequencing, and synchronization of micro-operations, other activation signals + control signals for external world
Fig-05: Basic Partition of SIMP Design
