Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver VLSI Design Using PC-Based Tools Cherrice Traver Union College Schenectady,

Design Automation Conference June, 2000

PC-Based VLSI Design ToolsCherrice Traver

VLSI Design Using PC-Based Tools

Cherrice Traver

Union College

Schenectady, NY



Why use PC-based tools?



Outline

Tanner Research Tools for Education

• Practical issues

• Tool flow and capabilities

• Example use

• Curriculum examples



Practical Issues System Requirements

Minimum requirements

• 100 MHz PCs, 32M RAM

Recommended

• 500 MHz PCs, 256M RAM

• 3-button mouse



Practical IssuesInstallation

• Tool installation - Install-Shield Wizard

• License server– Sentinel LM on NT Server– Floating individual tool licenses



Practical IssuesTool Choices

L-Edit DRC EXT SPR

L-Edit Pro

Tspice S-Edit W-Edit

T-Spice Pro

Design Pro

CM

OS

Libraries

Tanner Tools Pro



Practical Issues Cost and Maintenance

• Educational pricing• Quantity pricing• Free support for 60 days• No annual maintenance fee required• 15% maintenance fee per year for updates

and continued support



Practical IssuesDocumentation

Help Menu Indexed PDF Manual



Contact Information

Janice Barthelemy

Account Manager

[email protected]

Tanner EDA

2650 East Foothill Blvd.

Pasadena, CA 91107

Toll free (877) 325-2223

Fax (626) 792-0300

www.tanner.com



Simplified Tanner Tool Flow

S-Edit TM

Schematic EditorS-Edit TM

Schematic Editor

T-Spice TM

Circuit SimulatorT-Spice TM

Circuit Simulator

L-Edit TM

Full Custom Layout EditorL-Edit TM

Full Custom Layout Editor

W-Edit TM

Waveform ViewerW-Edit TM

Waveform Viewer

GDS II & CIF



Overview of Examples

• Layout Editor - L-Edit

• Schematic Editor - S-Edit

• Standard Cell Place and Route - SPR

• Spice simulator - T-Spice



L-Edit: Tool Flow

L-Edit TM



L-Edit/SPR TM

Standard CellPlace & Route

L-Edit/SPR TM


L-Edit/Extract TM

General DeviceExtractor

L-Edit/Extract TM

General DeviceExtractor

L-Edit/DRC TM

On-line DesignRule Checker

L-Edit/DRC TM

On-line DesignRule Checker

Cross SectionViewer

Cross SectionViewer

Layout LibrariesSCMOSLib

...


...

S-Edit TM T-Spice TM



L-Edit: Layout Editor Features



L-Edit: Example

CMOS Inverter

• Layout Editing

• DRC

• Cross Section Viewing

• Extract Spice File



S-Edit: Tool Flow

S-Edit TM

Schematic EditorS-Edit TM

Schematic Editor

Technology MappingLibrarySCMOS

...

Technology MappingLibrarySCMOS

...

SchemLib TM

Technology Independent

Library

SchemLib TM

Technology Independent

Library

T-Spice TM

L-Edit TM

SPR

NetTran netlistextract



S-Edit: Schematic Editor Features



S-Edit: Example

Full Adder Circuit

• Schematic Drawing

• Spice Export

• Tanner Place and Route Export



SPR: Tool Flow

L-Edit TM



L-Edit/SPR TM


L-Edit/SPR TM


S-Edit TM

.tpr file


...


...



SPR: Example

Full Adder Circuit

• L-Edit - Place and Route

• Core + Padframe

• Extract Spice Circuit



T-Spice and W-edit: Tool Flow

T-Spice TM

Circuit SimulatorT-Spice TM

Circuit SimulatorW-Edit TM

Waveform ViewerW-Edit TM

Waveform Viewer

S-Edit TM

L-Edit TM

netlist extract

device extract



T-Spice and W-edit: Features

• Menu-based command insertion

• Integrated W-Edit waveform viewer

• Circuit Probing from S-Edit



T-Spice and W-edit: Example

Full Adder simulation

– Simulation of schematic netlist

– Waveform probing

– Simulation of extracted layout



Tool Integration in VLSI Design Course

Laboratories– Tool use– Reinforcement of lecture topics

Project– Behavior --> Layout design experience



Laboratories

Lab 1 - L-Edit/T-Spice• Extract/simulate NAND gate • Layout/extract/simulate inverter

Lab 2 - L-Edit/T-Spice• Manual placement/routing standard cells• Manual stick diagrams• Extraction/simulation

Lab 3 - S-Edit/L-Edit/SPR/T-Spice• Schematic capture - netlist simulation• Standard cell place/route



Kitchen Timer Projectfrom Modern VLSI Design: Systems on Silicon, Wayne Wolf



Buzz Circuit

Schematic Given - Lab Exercise



Display Circuit

Block Diagram Given - Lab Exercise



Controller

• Specified by state diagram and VHDL model • Logic simulation outputs provided



Timer



Support Provided

• VHDL “Golden” behavioral model

• Simulation output results

• Lots of guidance on debugging



Top Level Schematic



Kitchen Timer Chip Statistics

• 600 Gates

• 8000 Transistors

• Layout area: 1550 um x 1375 um



Final Layout



MOSIS Fabrication

• Pads provided

• Flatten layout

• Export CIF file



Other Past DesignsUsing Tanner Tools

• Quadrature Decoderhttp://doc.union.edu/154/Quad.decode.project/index.html

• Simple Floating-Point Multiplierhttp://doc.union.edu/154/Mult.project/mult.project.html



Conclusion

• Ease of Installation/Maintenance

• Reasonable Design Flow

• Good Interface for MOSIS Fabrication

Documents

Design Automation Conference June, 2000 PC-Based VLSI Design Tools Cherrice Traver VLSI Design Using PC-Based Tools Cherrice Traver Union College Schenectady,