IJVD: 3(1), 2012, pp. 15-20

DESIGN AND VERIFICATION OF LSR OF THE MPLS NETWORK USINGVHDL

Suvarna A. Jadhav1 and U.L. Bombale2

1,2Department of Technology Shivaji university, Kolhapur, 1E-mail: suvarna_jadhav@rediffmail.com2E-mail: uttam_bombale@rediffmail.com

Abstract: With extremely wide bandwidth and good channel properties, optical fibers have brought fast andreliable data transmission to today's data communications. However, to handle heavy traffic flowing throughoptical physical links, much faster processing speed is required or else congestion can take place at networknodes. Also, to provide people with voice, data and all categories of multimedia services, distinguishingbetween different data flows is a requirement. To address this router performance, Quality of Service /Classof Service and traffic engineering issues, Multi Protocol Label Switching (MPLS) was proposed for IP-basedInternetworks. In addition, routers flexible in hardware architecture in order to support ever-evolving protocolsand services without causing big infrastructure modification or replacement are also desirable. Therefore,reconfigurable hardware implementation of MPLS was proposed in this project to obtain the overall fastprocessing speed at network nodes. The long-term goal of this project is to develop a reconfigurable MPLSrouter, which uniquely integrates the best features of operations being conducted in software and in run-timereconfigurable hardware. Here we are designing one component i.e LSR of MPLS network.

1. INTRODUCTION

The TCP/IP protocol is a classic and standardsolution to the network information transport.Currently, however, Internet Service Providers(ISPs) have the challenge to manage extensive andcomplex networks with increasing Quality ofService (QoS) and bandwidth requirements. In thisregard the natural evolution of IP networks andTCP/IP applications lead to the development of theMPLS architecture as an alternative to meet theserequirements. MPLS, an open industry standardbased on technology pioneered by Cisco Systems,bridges the gap between frame relay and IPnetworking. MPLS delivers the privacy and securitythat frame relay users are used to, with the any-to-any connectivity they want from IP networks.

MPLS is an IETF framework that integrates layer2 and layer 3 of the OSI model withoutdiscontinuities, and therefore combines the routingcontrol functions of the layer 3 and commutationspeed of layer 2 through a network. The MPLStechnology may be applied to any layer 3 networkprotocol, although almost all of the interest is inusing MPLS with IP Traffic Engineering. TrafficEngineering is concerned with performanceoptimization of operational networks. In general, it

encompasses the application of technology andscientific principles to the measurement, modelling,characterization, and control of Internet traffic, andthe application of such knowledge and techniquesto achieve specific performance objectives. Theaspects of Traffic Engineering that are of interestconcerning MPLS are measurement and control.Since MPLS works over any transport technologyincluding Asynchronous Transfer Mode (ATM) itcan facilitate the migration to future opticalnetworks that integrates IP and WDM (WavelengthsDivision Multiplexing) networks. Furthermore,MPLS offer several services that IP networks cannotprovide because they are limited to routing basedon destiny address. MPLS also provides QoS,supports IP traffic engineering and the creation ofVirtual Private Networks (VPNs).

Figure 1: MPLS Shim Header

16 Suvarna A. Jadhav and U.L. Bombale

It can be seen that the shim header is a 32 bitlength value where 20 bits represent the labelassigned to the frame, 3 bits are used for the EXPfield, 1 bit is assigned to the S field to indicate if labelstack is present and the Time to Live (TTL) fieldprevents packets from looping forever in thenetwork. The label transforms the packet from onethat is forwarded based on its IP routing informationto one that is forwarded based on informationassociated with the label. In MPLS, data transmissionoccurs on label switched paths (LSPs). LSPs are asequence of labels at each and every node along thepath from the source to the destination. LSPs areestablished either prior to data transmission (controldriven) or upon detection of a certain flow of data(data driven). The labels, which are underlyingprotocol specific identifiers, are distributed using alabel distribution protocol (LDP).

Each data packet encapsulates and carries thelabels during their journey from source todestination. High speed switching of data is possiblebecause of the fixed-length labels are inserted at thevery beginning of the packet or cell, and can be usedby hardware to switch packets quickly betweenlinks. The devices that participate in the MPLSprotocol mechanisms can be classified into labeledge routers (LERs) and label switching routers(LSRs) (see Figure 2).

multiple ports connected to dissimilar networks(such as Frame Relay, ATM, and Ethernet) and usingthe label signaling protocol at the ingress forwardsthis traffic to the MPLS network after establishingLSPs, and distribute the traffic back to the accessnetworks at the egress. The LER plays a veryimportant role in the assignment and removal oflabels, as traffic enters or exits an MPLS network.Another concept of MPLS networks is the forwardequivalence class (FEC) which is a representationof a group of packets that share the samerequirements for their transport. All packets in sucha group are provided the same treatment in routeto the destination. As opposed to conventional IPforwarding, in MPLS, the assignment of a particularpacket to a particular FEC is done just once, as thepacket enters the network. FECs are based on servicerequirements for a given set of packets or simplyfor an address prefix. Each LSR builds a table tospecify how a packet must be forwarded. The packetis then forwarded to the next router in the LSP. Thisrouter and all subsequent routers in the LSP do notexamine any of the IP routing information in thelabelled packet. Rather, they use the label to lookup information in their label forwarding table. Theythen replace the old label with a new label andforward the packet to the next router in the path.When the packet reaches the egress router, the labelis removed, and the packet again becomes a nativeIP packet and is again forwarded based on its IProuting information.

2. VHDL

VHDL (VHSIC Hardware Description Language) isbecoming increasingly popular as way to expresscomplex digital design concepts for bothsimulations and synthesis. The power of VHDLmakes it easy to describe very large digital designsand systems, and the wide variety of design toolsnow available make the translation of thisdescription into actual working hardware muchfaster and less error-prone than in the past.

The Power and depth of VHDL does have itsprice, however. To make effective use of VHDL asa design entry tool, you must invest time to learnthe language and, perhaps more importantly, tolearn to use the higher-level design methods madepossible by this powerful language.

3. LSR DESIGN

The LSR and LER are the node equipments of theMPLS network. LER works as intermediate node

Figure 2: Nodes in MPLS Network

An LSR is a high-speed router device in the coreof an MPLS network that participates in theestablishment of LSPs using the appropriate labelsignaling protocol and high-speed switching of thedata traffic based on the established paths. An LERis a device that operates at the edge of the accessnetworks and MPLS network. LERs support

Design and Verification of LSR of the MPLS Network Using VHDL 17

between access networks and MPLS domain; andLSR works as the high speed MPLS router withinthe MPLS network.

In this chapter, we focus on the pin details ofthe LSR, its specifications and its top level design.

table, decodes the configured instruction and givesvalid new modified output label and output portnumber on which packet is to be transmitted. Whenthe Control state machine module receives the newlabel, it transmits the new label, reads the data fromthe respective FIFO and transmits all the data. It alsoenables the arbiter module for the next grant.

4. THE LSR VERIFICATION

The LSR module needs to verify for push, pop andswap operation for all combination of the input portsand output ports. Also read write operations of thecontrol registers needs to verify. The block diagramof the verification environment is given below. Theinitial values of the control registers and few datapattern are written into the control registers andread back to verify the read and write operations.

To verify the LSR for different input labels,instructions and port information, the input labelregisters, output labels registers and control registersneeds to write with the valid values. These values arelisted into the input_state.txt files with other testscenarios.

The packet control module reads theinput_state.txt file and generates enable signals forthe other modules as per the data listed into theinput_state.txt file. The read/write control moduleis responsible for verifying the read write operationand configuration of the control registers fordifferent input labels and its instructions usingconfiguration interface.

The packet gen modules are responsible forgenerating packets of the different length and label.The monitor modules receive the packetstransmitted by the LSR and write them intomonitor.txt files.

The checker module reads the input andmonitors files, compares the data sequentially andgenerates the final result file.

4.1 Simulation

As shown in figure 6, input port2 and port 3 aregiving data to the LSR and as per the LIB instructionit is forwarded on the port1.Before output port 1completes transactions for Input Port2, input port 3starts giving data. The LSR continue with thetransactions for input Port2 until the FIFO2 is emptyand after that it starts transactions for the input port3.Also as first data written into the FIFO3, lsr_busy_3is asserted high to indicates LSR is busy on inputport3 and not able to receive the next packet.

Figure 3: Pin Diagram of the LSR

When packet Val input is asserted, the data onto the packet_in input is written into the respectiveFIFO. If unread data are present into the FIFO, itgenerates the request for the process to the arbitermodule. When arbiter module is enabled by thecontrol state machine module, it gives grant as perthe request given by the FIFO modules and itspriority. Once the control state machine receives thegrant, it disables the arbiter module and request ofthe respective FIFO. It reads the first data of therespective FIFO and retrieves the label and requeststhe label information base module to compare it withthe internal static table. The label information basemodule reads the input label, compares it with the

18 Suvarna A. Jadhav and U.L. Bombale

Figure 4: Block Diagram OF the LSR

Design and Verification of LSR of the MPLS Network Using VHDL 19

5. THE LSR NETWORK DESIGNAND VERIFICATION

The MPLS network is created by interconnectionbetween number of LSRs and LERs. The design andverification of the LSRs are explained above. UsingLSR’s instances and interconnections between them,network is created. The simulation result is shownin figure 7.

Figure 5: Block Diagram of Verification of LSR

Figure 6: Simulation of LSR Verification

Figure 7: Block Diagram of LSR Network

Figure 8: Simulation Result

5.1 Design

Five LSRs are connected to create a network withsix external input and output ports. Interconnections between the LSRs with the port numberand external input and output ports interfaces areshown in figure 7.

6. CONCLUSION

In this paper, first the MPLS network is explained.Then it explains the layer where the network sits.Wehave seen the implementation of one of theelements of the network, LSR. The LSR deals withthe input LER to get the input packets and afterpackets hopping on the route the last LSR sends thedata packets to the output LER. LSR-LSR hoppinghappens with the use of labels which are attachedto the MPLS packets as they enter into the network.This process takes place using internal modules suchas control state machine, FIFO, arbiter and labelinformation base.Explaining the each module andputting simulation results for all modules, reportgives the details about how exactly LSR works, toforward the packets received by it, showing thesimulation results snapshots. Simulation results alsoshow the time required for data transfer in terms ofthe clock.

The verification of the design is done at twolevels, firstly only one LSR is tested which we cancall as low level abstraction and then the network ofLSRs is tested which we can call as high level ofabstraction. For verification, inputs are given throughtext files and output is received in another text filewhich shows success or failures of the design. Thesynthesis report shows the use of the device inpercentage and maximum frequency (Minimumperiod: 6.962ns Maximum Frequency: 143.637MHz)at which we can work on with the LSR network.

REFERENCES

[1] Modeling an MPLS Network.pdf “http://www.xilinx.com/itp/xilinx92/books/docs/xst/xst.pdf

20 Suvarna A. Jadhav and U.L. Bombale

[2] MPLS, Charter, IETF, http://www.ietf.org/html.charters/mpls-charter.html

[3] Multiprotocol Label Switching (MPLS),International Engineering Consortium, http://www.iec.org/online/tutorials/mpls

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[8] Jack Foo, “A Survey of Service RestorationTechniques in MPLS Networks”, AustralianTelecommunications, Networks and ApplicationsConference, ATNAC December 2003.