Design And Implementation Of Viterbi Decoder Using Trace Forward Method

M.Azarudeen1

Electronics and Communications Engineering

PSNA College of Engineering and Technology

Dindigul, India

Abstrtact-----In today’s digital communication systems, convolutional codes are broadly used in channel coding techniques. The Viterbi algorithm is a widely used for decoding of convolution codes. The

algorithm helps to find a path of the trellis diagram, in which the sequence of output symbols is nearly equal to the received sequence. For this purpose, the decoder measures the distance of the received

symbols sequence by calculating path metric for each path. The branch metric calculates metric distance between the received noisy symbol and the output symbol of the state transition. The

accumulated metric associated with the sequence of transitions (path) to reach a state is computed by ACSU. When more than one path arrives to a state, ACSU selects the path with the lowest metric value,

which is the survivor path. In this proposed system, Trace Forward method is used in survivor memory unit. This method to finds the merged path while the decision bits are being received. The main aim

of proposed method is to reduce power consumption and increasing the speed. Trace Forward method is compared with the normal trace back method and its area reduced by 56%.

Keywords---- convolutional encoder, viterbidecoder,viterbi algorithm, trace forward method.

I. INTRODUCTION:

The Viterbi algorithm is used widely in the digital

transmission field as a means of decoding convolutional forward error correction codes. Viterbi decoders are used for trellis code demodulation in telephone line modems, where the throughput is in the range of tens of kb/s, with restrictive

limits in power dissipation and the area/cost of the chip. Very high speed Viterbi detectors are used in magnetic disk drive read channels, with high throughputs but at this high speed, the area and power are still a limitation. Viterbi algorithm is

commonly used for decoding the convolution codes due to its high performance. It is widely used in different communication standards and communication environments like satellite, Wireless Local Area Network (WLAN), and so

on. It offers an alternative to block codes for transmission over a noisy channel. Viterbi decoder is the most suitable hardware platform for implementing the Viterbi algorithm. Fast developments in the field of communication in the recent

years have created a rising demand for high speed and low power Viterbi decoders with extended battery life, low power

Dr.P.Manirajkumar2

Electronics and Communications Engineering

PSNA College of Engineering and Technology

Dindigul, India

dissipation, and low weight. Regardless of the significant progress in the last decade, the problem of power dissipation in the Viterbi decoders still remains challenging and requires further technical solutions. Thus, a flexible, low power, and high speed Viterbi decoder design is a key challenge for future portable and communication devices. 1.1 CONVOLUTIONAL ENCODER

The main advantage of convolutional coding is that it can be applied to a continuous data stream as well as to blocks of data.In convolutional encoding n-tuple of data is generated for every k-tuple of inputs based on both current and K-1 previous k-tuples where K is called constraint length of the code. A (n, k, m) convolutional code can be implemented with a k-input, n-output linear sequential circuit with input memory ‗m‘. Typically, ‗n‘ and ‗k‘ are small integers with k<n, but the memory order ‗m‘ must be made large to achieve low error probabilities. The constraint length K of the code represents the number of bits in the encoder memory that effect the generation of the n output bits and is defined as K = m+1. The code rate r of the code is a measure of the code efficiency and is defines as r= k/n. A Convolutional Encoder is a Finite state machine i.e. a model of behavior composed of states, action and transition. Contents of first K-1 shift register stages defines the encoder state. Memory register start with 0 and modulo-2 adders among the registers and input generate the encoded data. Generator polynomial defines how the adders (XOR gates) are placed.The proposed Encoder has the following specifications below and schematic in Fig. 1. Constraint Length: K = 3, Input bit: k = 1, Output bit: n = 2 Generator Polynomials: G0 = 1 + X + X2, G1 = 1 + X2.

Fig1: Convlolutional Encoder (Rate ½, K = 3)

II. DESIGN AND IMPLEMENTATION

2.1 VITERBI ALGORITHM

The Viterbi is a maximum likelihood decoding

algorithm for Convolutional codes. When the hamming distance which is used to compute the probability of received signal is called as ―Minimum distance decoding‖ or Maximum likelihood decoding algorithm.‖ In general forward, stop and reverse is a process of ―maximum likelihood sequence‖ generation. The Viterbi algorithm uses the trellis diagram to compute the path metric value (accumulated distance) from the received sequence to the possible transmitted sequences. The total number of such trellis paths increases exponentially with the number of stages in the trellis. It causes potential complexity and memory problems. 2.2VITERBI DECODER

The Viterbi algorithm, implemented in hardware, is referred to as the Viterbi decoder. The block diagram of the Viterbi decoder is shown in Figure 2. It is composed of three functional units: (1) Branch Metric Unit (BMU). (2) PathMetric Unit (PMU) or Add Compare Select Unit (ACSU). (3) Survivor Memory Unit (SMU).

2.2.1 BRANCH METRIC UNIT

The first unit is called Branch metric unit. This unit computes the branch metric of each transition, which is a hamming distance between the received symbol and expected symbol. The architecture of the BMU comprises of a xor gate and a counter. The branch word followed by on the constraint length, the generator matrix, and the code rate. Input to xor

gate is the received code and the other input is the expected sequences which are the encoder output. Xor gate find out the difference in the number of transitions in the inputs and counter counts the total number of differing bits. The BMU for one state is given in Figure 2

Fig 2: Branch Metric Unit 2.2.2 PATH METRIC UNIT (PMU)

The PMU calculates new path metric values and decision values. Because each state can be achieved from two states from the earlier stage, there are two possible path metrics coming to the current state. The PMU adds the branch metric to path metrics and typically selects the smaller one and makes a decision. The PMU stores the result of the addition as path metric for current state. 2.2.3 ADD COMPARE SELECT UNIT

The second unit is called add compare select unit. In the viterbi decoding is ACSU which is the heart of the process and dictates the performance of the decoder. It is consist of adder, comparator and selector. An ACS unit has 4 inputs ,namely, two branch metrices(BM1,BM2),Two path metrics(PM1,PM2),and two outputs namely New path metric and the decision bit.

Fig 3:Add Compare Select unit

In the figure has there are two paths for a single state: one path for upper branch and the other for lower branch. The ACSU which adds the BM1 and BM2 to the Corresponding PMs, PM1, and PM2, respectively, compares the new PMs and stores the selected PMs in the Path Metric Memory (PMM) in addition to the associated survivor path decisions in SMU.

2.2.4 SURVIVOR MEMORY UNIT

The third unit is called survivor memory unit. The Survivor memory unit is designed by using the serial-in-serial-out shift register and the length of the shift register depends on the length of the convolution encoder It is responsible for keeping track of the information bits associated with the surviving paths.SMU uses these bits to find the final survivor path and decode the source bits. To find the survivor path entering each state of the decoder, the BM of a given transition is added to its corresponding PM.This sum (BM + PM) is compared to all the other sums corresponding to all the other transitions entering that state. The transition that has the minimum sum is chosen to be the survivor path. 2.3 DECODING METHODS

There are two basic methods of Viterbi decoder register-exchange method and the trace back method. The register exchange is very easy to understand, and works well for small constraint lengths. The trace back method is a bit more difficult, but works well for longer constraint length codes. So the proposed method is trace forward method . 2.3.1Traceback method: The Trace back method is acceptable for trellises with a large number of states. It stores the decisions from the ACS into a RAM. Later, the decisions are read out. The best path is determined by reading backwards through the RAM, and tracing a path backwards through the trellis. This reads the bits out in backwards order. Further, several reads are required to trace backwards far enough to find where the paths have merged.

Fig 4:Trace back Method

The limitation in TB method is that all the paths of the states have to be traced backward which involve more transitions and switching activity, thereby increasing latency. 2.3.2 TRACE FORWARD METHOD

The TFU approach is acceptable for trellises with a small number of states. The trace-forward units (TFUs) are

used to derive decoded outputs instead of pointing to merged states in trace-back applications. In a typical TB method, the TB operation is commonly divided into two parts: TB read and TB decode. The main difference between them is that TB decode will output the decoded bits in the decode block during TB process, while TB read is only used in the merge block to find a merged state after tracing back a pre-defined length. The merged state is then used as the starting point for the following TB decodes. Since the aim of TB read is to find the merged state, one can form a hybrid structure by replacing the TB read with a TFU to speed up the TB operation . The TFU is employed to keep track of the end state of each survivor path of a state. The end state can be determined at the time when writing data into memory, which is a trace-forward operation.

Fig 5:Trace forward Method

TFU block diagram a A four-state TFU example b A simplified TFU for an N-state trellis The design of a conventional TFU is basically a RE structure with a length of exactly m bits, which corresponds to the state value. Such a

TFU is denoted as the TFU_m described later in this work. For example, a four-state TFU is illustrated in Fig. 3a, which consists of four 2-bit registers, defined as the tail state register in [6], and four 2-to-1 multiplexers. The multiplexers take the

decision bits from ACSU as the selection signals. The wiring between registers and multiplexers is similar to that of the RE method. Note that existing studies take TFU as part of hybrid SMU design and focus on the tradeoff between hardware

complexity and decoding latency. In contrast, this work employs TFU features to perform the RE operation and aims at minimizing the power consumption. Moreover, previous TFU designs require a length of exactly m bits to represent the

state value, which may also be used as part of the decoded results as described.

III RESULTS

The proposed design of Trace forward Viterbi decoder is coded in VHDL language using XILINX 14.7. The obtained results are shown below.

Above table 1 describes the device utilization summary of proposed Viterbi Decoder. The above work requires processing frequency of 492MHZ and requires maximum period of 18.742 ns.

IV CONCLUSION

This work aims at implementing the Trace Forward method in a viterbi decoder and analyzes various parameters such as speed, power and area. This analysis shows that the viterbi decoder with trace forward method provides low area overhead and high speed which as compared to Trace Back method based viterbi decoder.

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