Design and implementation of a hardware fuzzy inference system

NORTH- HOLLAND

D e s i g n a n d I m p l e m e n t a t i o n of a H a r d w a r e ~ z z y I n f e r e n c e S y s t e m

DONALD L. HUNG

Department of Electrical Engineering, Gannon University, Erie, PA 16541

and

WILLIAM F. ZAJAK

Spectrum Control, Inc., 8051 Avonia Road, Fairview, PA 16415

ABSTRACT

This paper discusses the design of a dedicated hardware fuzzy inference system based on the generalized modus ponens (GMP) inference rule, the "mini" fuzzy implication flmction, the "max-min" fuzzy composition rule, and the center of gravity (COG) defuzzification method. As a special ease, the implementation of a two-input (antecedents), one-output (consequent) fuzzy inference system based on the general design idea was implemented on a single field programmable gate array (FPGA) chip with an extra EPROM for defuzzification. Circuitry details and performance data are included. Additional issues such as extendibility and adaptability are also discussed.

1. I N T R O D U C T I O N

In fuzzy applications, when the demand of processing speed reaches a certain level, a hardware fuzzy inference engine often becomes the only solution. In recent years, a number of hardware fuzzy inference systems have been reported or proposed [1-4], [6], [8-15] that reflect the diversity in fuzzy inference methods and in technologies related to hardware design. In general, analog hardware is relatively simple, but lacks accuracy and re- liability; on the other hand, digital hardware is accurate and reliable, but is more complex and lacks speed if an iterative algorithm is unavoidable. In recent years, rapid advances in digital technology allow system designers to design custom computing machines based on a variety of technologies: full

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194 D.L . HUNG AND W. F. ZAJAK

custom application-specific IC (ASIC), standard-cell,, gate array, FPGA, programmable logic device (PLD), standard IC, etc. Among these, FPGA is especially suitable for fast implementation and quick hardware verifica- tion. Besides technology alternatives, design decisions have to be made based on tradeoffs on performance, hardware resource, and flexibility. In general, higher performance can be achieved at the expense of more hardware resource and less flexibility.

In this paper, the design and implementation of a digital hardware fuzzy inference system is discussed. Since the guideline for the design was to pursue high performance, the designed system is algorithm-specific, i.e., instead of trying to support a large number of possible fuzzy inference methods, the system is dedicated to the algorithm which is based on the most widely adopted fuzzy inference mechanism, namely, GMP-based inference with the "mini" operator for fuzzy implication and the "max-min" operator for fuzzy composition. To achieve high performance, a system architecture with a high degree of parallelism was chosen. In order to gen- erate a crisp output as the fuzzy inference result, the design adopted the defuzzification algorithm based on the most favorable COG method. Tra- ditionally, digital hardware designs for COG-based defuzzification employ iterative multiplier and divider circuitry. As will be shown in the paper, this limits the overall throughput of the system and becomes the compu- rational bottleneck of the fuzzy inference process. To increase processing speeds, a table lookup approach for implementing the COG function was proposed which eliminated the need for multiplier and divider circuitry and significantly improved the system's throughput. For hardware verifi- cation, a two-input (antecedents), one-output (consequent) fuzzy inference system based on the general design consideration was implemented with a Xilinx XC4008-6 FPGA and a Cypress CY7C251 EPROM. As expected, the system achieved a very high processing speed. Details of the system's functional blocks and tested performance data are provided, and some remaining issues are discussed as the conclusion of the paper.

2. FUZZY INFERENCE--FROM A HARDWARE POINT OF VIEW

About 40 different fuzzy inference methods have been proposed in the literature [5, 7] as the results of different fuzzy inference rules and different fuzzy implication, composition, and defuzzification methods used in the inference process. In practice, most of the fuzzy applications adopt an inference mechanism which is based on a combination of the following:

• Inference rule: Generalized Modus Ponens (GMP) • Implication operator: Mini

DESIGN AND IMPLEMENTATION OF FUZZY HARDWARE 195

• Composit ion operator: Max Min • Defllzzification method: Center of Gravity (COG)

Our discussion on hardware design is based on the fuzzy inference mechanism listed above.

The GMP fuzzy inference rule is stated as below:

Premise 1: If input is A then output is B Premise 2: Input is A ~

Consequence: Output is B ~

(1)

where A, B, A ~, B ~ are fuzzy sets. Premise 1 in (1) is described by the fuzzy implication function R = A

--~ B, where R is a fuzzy relation and, when the "mini" operator is used, its membership function values are computed as

#R(U, V) = min(pA(u), #B(V)); u C U, v E V. (2)

In (2) #R(u, v), #A(u), and ttB(v) are membership functions of R, A, and B, respectively, and U and V are universes of discourse of A and B, respectively.

The Consequence in (1) is determined by the fuzzy composition B ~ = N°R and, when the "max-min" operator is used, the membership function value of B ~ is computed as

#B' (V) = max min(pA, (u), #R(u, v)) (3)

where >a' (v) and #A' (u) are membership functions of B' and A' respectively. The above procedure deals with a SISO (single-input single-output)

fuzzy inference system. GMP-based multiple-input multiple- output (MIMO) fuzzy inference systems can be partitioned into a set of multiple-input single-output (MISO) subsystems with respect to each output. Further, when the "mini" fuzzy implication function and the "max-min" fuzzy composition rule used, the following relation holds [5]:

B ! l I I 0 = (A 1 ,A2, . . . ,An) (A1 × A2 x . . . × An ~ B) • /0 = A2 (A2 ~ B ) , . . A'°~'A m m [ A 1 (A1 -~ B), ,o ., ,,~ ,,--~ B)] (4)

and the membership function value of B' can be computed as

#B' = min{[min(maxmin(#A,i,#Ai))],#B}, for i = 1 ,2 , . . . ,n. (5)


• x

A'

~ min , Y

~ rain Y

B' zO

Fig. 1. A graphic interpretation of the fuzzy inference computation.

In applications, inputs and outputs of a fuzzy inference system are fuzzy linguistic variables, each of which is characterized by usually more than one fuzzy linguistic values (fuzzy sets). As a consequence, with a sample of observed input values, multiple inference rules can be activated simultaneously. Since a crisp output (decision) is required by most applications, fuzzy inference systems normally adopt certain defuzzification strategies to determine a crisp value in the output space. The computation required by the widely used COG-based defuzzification method is

E WiZi z 0 - E w i (6)

where wi is the weight (membership function value) of the ith activated rule and zi is the correspondent crisp value in the universe of discourse of the output space.

A graphic interpretation of the computation described by (4)-(6) is given in Figure 1, where the simple fuzzy inference system has two inputs and one output with two inference rules: 1) if A1 and B1 then C1, 2) if A2 and B2 then C2, and the observed inputs A t and B t are assumed to be crisp.

With the help of Figure 1, the hardware algorithm for fuzzy inference systems under discussion can be summarized as follows:

HARDWARE ALGORITHM.

1. Perform the "maximum of minimum" operation between each observed input linguistic value (a fuzzy set in general) and the system's input membership functions in the correspondent input space.


2. Perform the "minimum" operation among values obtained from Step 1 and relate to the same inference rule.

3. For all weights obtained from Step 2, perform

(a) the "summation" operation ~ wi,

(b) the "multiplication" operation w izi.

4. Perform the "summation" operation ~ w~z~ for all wizi obtained from Step 3b.

5. Perform the "division" operation ~ w i z i / ~ w~ using the results obtained from Step 3a and Step 4.

The five steps listed above must be executed sequentially, but operations inside each step can be executed concurrently. From a hardware point of view, dataflow from Step 1 to Step 2 clearly bears a parallel architecture, and Steps 3a, 3b can be pipelined. Step 3-Step 5 are for the COG-based defuzzification. In this part, multiplication and division are encountered. since their correspondent arithmetic algorithms are complicated and re- quire a significant amount of iterative operations, hardware fuzzy inference systems that employ multiplier and divider circuitry in their COG design suffer from greater complexity and lower overall processing speed.

3. DESIGN CONSIDERATIONS

A major concern in this design is to keep the system architecture with a high degree of parallelism and eliminate the iterative multiplication and division operations in Step 3b and Step 5 of the hardware algorithm discussed in Section 2. Along with the hardware algorithm, the following constraints have been applied to the design:

DESIGN CONSTRAINTS.

1. The observed inputs of the fuzzy inference system are crisp and digitized.

2. For each input variable, the overlapping degree of its membership functions is limited to 2 (i.e., no more than two input membership functions can be overlapped in the same input space) and the maximum overlap of two adjacent membership functions is 0.5.

3. Output membership functions are symmetric in shape.

The first two constraints are based on practical considerations and experience gained from previous fuzzy applications. The third constraint is basically for simplicity in implementation. These constraints relate to the fbllowing hardware design considerations:

198 D .L . HUNG AND W. F. ZAJAK

DESIGN CONSIDERATIONS.

1. With Design Constraint 1, the "maximmn of minimum" operation in the hardware algorithm (Step 1) discussed before can be simplified as a table search operation. Values of a input membership function can be prestored in a lookup table and the digitized crisp values of the observed input serve as the addresses for accessing the table.

2. Design Constraint 2 means that for a fuzzy inference system with n inputs, given a sample of observed input values, at most 2 n inference rules can be activated. This constraint also ruduces the est imated lengths of the binary sum ~ w~ and ~ wizi in the hardware algorithm (Steps 3a, 4, and 5).

3. Design Constraint 3 significantly reduces the storage and computation required by the COG-based defuzzification by allowing the usage of a simplified version of the COG algorithm in which the zis are considered the center values in the universe of discourse of output membership functions. The i th output membership function therefore can be treated as a fuzzy singleton situated at zi in the universe of discourse of the output space. This approach is known as the truth value fuzzy inference (TVFI). The simplicity of the T V F I leads to the next two alternative design considerations that eliminate the need of iterative multiplication and division hardware according to the hardware algorithm.

4. Since the input and output membership function values have limited resolution (scales), for a particular fuzzy output singleton situated at zi all possible wizi values can be precalculated and stored in a lookup table which has values of wi as the addresses for accessing the table.

5. Since both the ~ wi and ~ wizi in the hardware algorithm have limited length, all possible values as the results of the division ~ w~zi/

wi can be precalculated and stored in a lookup table, and values of the concatenated ~ wizi and ~ w~ serve as the addresses for accessing the table.

The generic data path of a MISO fuzzy inference system based on the above discussion is shown in Figure 2. The Input lookup tables are for Step 1 of the hardware algorithm. The Minimum module performs the "minimum" operation described in Step 2 of the hardware algorithm. The Rule Reduction module selects the activated inference rules based on the current sample of the observed input values, and produces the correspondent set of wi and wizi values. The Summation module is shared by the wi inputs and the wizi inputs and a partial pipeline can be formed here, i.e., while the module is adding up the ~ wi, values of wizis are being fetched from their lookup tables. The ~ w~ and ~ wizi are finally latched to form the


Minimum _ _ Rule

Reduction

D e f u z z i - w~ ~@ ~ca~on Summation Lookup

Table

Fig. 2. The generic da ta path of the proposed MISO filzzy inference system.

address bus to the Defuzzification lookup table. The depth of the tables is T '~, where m is the total length of the concatenated binary data ~ wi and Y~, w~zi. Note that the Defuzzification lookup table only depends on the lengths of ~ wi and ~ wiz~. As long as its address bus is wide enough to cover the length of the concatenated ~ wi and ~ w~zi, the Defuzzification lookup table is independent of changes in the rest of the parts (the fuzzi- fication strategy, the choices of the system's database and rule base, etc.) of the fuzzy inference system.

The control logic of the proposed fuzzy inference system is a simple finite state machine (FSM) which controls operations of the system's data path by generating the following basic commands:

• latch the system inputs • latch the Minimum module inputs • latch the Rule Reduction module inputs • latch the wi inputs to the Summation module • latch the ~ w~ outputs from the Summation module • latch the wizi inputs to the Summation module • latch the ~ wizi outputs from the Summation module • read the Difuzzification lookup table

The basic configuration of the FSM can be easily modified to pipeline the above operations with different overlapping stages.

4. IMPLEMENTATION

Based on discussions in the previous section, a two-input, single-output fuzzy inference system has been implemented. The observed input values are assumed to be digitized into six bits. Each input variable of the system

200 D .L . HUNG AND W. F. ZAJAK

C1(16) 0 0 0 I

Inference D Engine

YO Block Diagram C9(144: l 0 0 l

D1 D2 D3 Not Nccd¢d

0 0 0 0 E1 C1 C2 C3 o o o o

E2 C4 C5 C6

o o o o E3 C7 C8 C9

Input/Output Rule Base

Membership Functions oflnput E (16-levels)

~ x (6-bit input)

Membership Functions of Input D (16-1evels)

~- y (6-bit input)

Membership Functions of Output C (fioxy singletons, 16-1evels)

16 32 48 128 144 D- z (8-bit output)

Fig. 3. I / O a n d k n o w l e d g e b a s e of t he i m p l e m e n t e d s y s t e m .

has three membership functions, which implies that up to nine inference rules can be adopted. All membership function values are represented by four bits of binary, which gives 16 levels of resolution. A maximum of nine distinct fuzzy singletons are equally distributed in the universe of discourse of the output space. The defuzzified output values are represented by eight bits of binary numbers. The fuzzy output singletons are separated 16 units apart from each other; therefore, only four bits are needed to represent their locations. This information has been presented graphically in Figure 3.

Due to Design Constraint 2, for a sample of observed input values, no more than four inference rules can be activated in this system. To select the four active inference rules among a set of possible nine, a rule reduction criterion was derived and shown in Figure 4.

With all the given information, the reader can verify tha t 1) the wiz~ values can be stored in eight-bit binary format, 2) the sum ~ wi can be represented by a five-bit binary number, and 3) the sum ~w~z~ can be represented by a nine-bit binary number.

The Defuzzification lookup table was implemented by using a Cypress CY7C251 16K x 8 EPROM with 50 ns access time. The rest of the system was implemented on a single Xilinx XC4008-6 FPGA. The control logic was designed in a "one hot" fashion using the F P G A ' s on-chip flip-flops.

D E S I G N A N D I M P L E M E N T A T I O N O F F U Z Z Y H A R D W A R E 201

min(E 1,D l)min(E 1,D2)min(El,D3)min(E2,D l)min(E2,D2)min(E2,D3)min(E3,D l)min(E3,D2)min(E3,D3)

I wl

I I I I I L I J

w2 w3 w4 w5 w6 w7 w8 w9

w2 or wg w4 or w6 w5 w I or w3 or w7 or w9

Fig. 4. T h e ru le r e d u c t i o n c r i te r ion .

TABLE 1 Timing Information (FPGA Package Speed Grade: 6 ns/CLB)

Path Delay

Input pin to input register 13.8 ns Input register to Min register 75.0 ns Min register to Rule Reduction input register 75.0 ns Rule Reduction input register to wi pre-sum register 100.0 ns we pre-sum register to sum of wi register 100.0 ns Max register to wizi pre-sum register

(in parallel with the above two steps) (200.0 ns) wizi pre-sum register to sum of ~l)iz i register 100.0 ns Sum of ~l)izi register to EPROM input register 25.0 ns EPROM input register to FPGA output pads 36.0 ns EPROM access time 50.0 ns

In a d d i t i o n to the essent ia l s ta tes , numbers of wai t s ta tes were a d d e d in to cope wi th da taf lows wi th different p ropaga t ion delays. The I n p u t lookup tab les , and the lookup tab les t h a t s tore the p reca lcu la ted wiz~ values, were i m p l e m e n t e d wi th user-configured memor ies by using the XC4000 fami ly ' s comb ina t i ona l logic resources. All of the o ther modules were based on the macros and pr imi t ives avai lable in the XC4000 family l ibrary. Deta i l s of t he M i n i m u m module , the Rule R e d u c t i o n module , the S u m m a t i o n module , and the s implif ied overall s t ruc tu re of the implemented sys tem are shown

in F igures 5, 6, 7, and 8, respectively.

5. T E S T I N G RESULTS

From discussions in the previous section, it is clear t h a t the imp lemen ted fuzzy inference sys t em is d a t a p a t h intensive while a rch i t ec tu ra l ly simple. Af te r the func t iona l i ty of the overall sys tem was verified t h rough simula-

202 D . L . HUNG AND W. F. ZAJAK

E, w, . . . . . . ] , j ,! Dl I

A[3"0] ~ A>~ I OT " 3 I El 4 [ " " " ' 7 A --IH , . J " ' " -I I~, . ~AB: H- for B I ~4 w2 / I / I i,

D2 ~ COMP4 ~,~ 4 LT ~ L ' f ° r A [ i " " min(A'B

B[3:0] A<B 4 X74-257

o ~ ~ I ' " I "~ ' D3 ...................................................................................

The "mini" Block

F ig . 5. T h e M i n i m u m m o d u l e .

I 16xSROM I A[3:0] A>B AB: H-forB I W5 I O^~ t̂':0] I ' . W5*Z5 ~ COMP4 I" L- for A 4 ; max(A,B)

I x , . .

The 16 x g ROM for storing ' : l l i values of WS*Z5 ! .................................................................

32 x 8 ROM

j max28 ~ T ~ : : : : DATA[7:0][ W2 . . :o]

w~ . ] I " 32 x 8 ROM

w, ? ] :ol max_46

W6 ~,]

The "max" Block

w2,z2 or w s ' z s ~ Registered to

Summation Module 4 w2 c¢ ws J'=--'-~ 8 (reduced from rules

4 1X74"374 V El-D2 and E3-D2)

k W 4 * Z 4 o r W 6 * Z 6 ~ Registered to Summation Module

4 w4 or we ~ s (reduced from rules • iX74.374 T " 4 E2-D1 and E2-D3)

Wl 4 GT GT WI or W3 of W7 or W9 4 8

W3 cgistcre d 4 to I I I Je 6 4 x 8 R O M .

max_79 ADDR4 DATA[V:0] •

w9 " 7 I " ' ^DOK~

WI'ZI or W3*Z3 or W7*Z7 or Wg"Z9

Reduced from rules El-D1, El-D3, E3-DI and E3-D3

4 W5 t~

X74-374 ~

16 x 8 ROM Registered to

Summation Module

F ig . 6, T h e R u l e R e d u c t i o n m o d u l e .

DESIGN A N D IMPLEMENTATION OF FUZZY HARDWARE 203

Regis tered

Wi or WiZi

from four

fired rules

88• AIT0] SUM[7:0]] ADDg co I

B[7:01

Cl

B[70]

CI

ADDS

8 SUM[7 0] == --

co ~.

I ° - . . - -

A[70 I

A8

A[II 9] SUM[S 0]

ADDI2

SUM[II 91 =

CO B[7:0] BZ B[II 9]

' • C I

Fig. 7. T he S u m m a t i o n module .

9 '~"" w i or

" ' k ' - - I ~ ,~-.- W i Z i

to be 3 ' b registered

lo-okup T I

Fig. 8. T h e overall s t ruc tu re of the implemented sys tem.


tion, the design was targeted to a Xilinx XC4008-6 FPGA with 6 ns delay per configurable block (CLB). Timing information after physical placement and routing was obtained as shown in Table 1.

With this timing information, appropriate speeds for the system clock can be determined, and the system's control logic was modified accordingly. With a 40 MHz system clock, the designed system produces 1.67 million fuzzy inferences per second (FIPS) without pipelining. For a fully pipelined version of the system, a 20 MHz system clock was chosen, and the system's processing speed exceeds 9 million FIPS.

6. CONCLUSION AND DISCUSSION

The design considerations of a hardware fuzzy inference system in general, and the implementation of a two-input, one-output system as a special case, have been described in previous sections. As a conclusion of this paper, some remaining issues are briefly discussed below.

Performance.

Due to the high degree of parallelism of the system's architecture and the simplicity of its computational modules, successful performance results (measured by FIPS) were obtained compared to those available from other reported systems [1], [8], [9], [11-131. Considering that the implemented system was targeted at a Xilinx XC4000 FPGA with 6 ns delay per CLB, system performance may be further improved by targeting the design to other technologies or to the same device with a better speed grade.

Rule Aggregation.

In the rule base of a certain fuzzy inference system, if several inference rules that relate to the same ouput membership function are activated by the same inputs, e.g., if rules A1 x B1 --* C1 and A2 x B2 - - ~ Cl are activated simultaneously for a given input pair (A', B~), theoretically the two inferred C~s need to be aggregated before entering the defuzzification stage. (The aggregation operator can be either disjunctive, e.g., the "max" operator or conjunctive, e.g., the "min" operator, depending on which one is more appropriate for a specific application.) Based on our experience, when the COG method is used in defuzzification, the rule aggregation stage can be skipped without causing noticeable differences on the final deffuzzified results. For this reason, hardware for the rule aggregation function was not considered in the implemented system discussed in Section 4, although the inclusion of this function may not necessarily increase the complexity of the overall system.


Extendibility.

As stated before, a MIMO fuzzy inference system based on GMP can be decomposed into a number of MISO subsystems in parallel. Theoretically, the concept and architecture of the implemented two-input, one-output fuzzy inference system can be extended to handle any number of inputs. Due to the architecture's high degree of parallelism, the extension should not cause deterioration in overall performance. The real constraint, how- ever, contes from the availability of hardware resource. For a MISO fuzzy inference system with n inputs, assuming that each input is characterized by m membership functions in the input database, the inference system may have up to rn '~ different inference rules in its rule base. With De- sign Constraint 2 mentioned in Section 3, up to 2 '~ inference rules may be activated by a given input sample. These observations show that the required hardware resource increases exponentially with an increase of the system's input. Although the rule reduction circuitry based on Design Constraint 2 will eliminate a considerable portion of the required hardware resource, the complexity of the rule reduction circuitry itself may increase remarkably. To cope with a large number of inputs by using the two-input, one-output fuzzy inference system discussed in Section 4 as a basic module, one possible approach is to decompose an inference rule with a long list of antecedents (inputs linguistic variables) into a set of two-antecedent inference rules tha t are linked by some appropriate connectors. For instance, decompose A x B x C x D --* E into (A x B --, E)&(C x D --+ E) where "&" is the connector and A, B, C, D, E are linguistic variables.

Adaptability.

The adaptabil i ty of a fuzzy inference system is determined by the sys- t em's capability to update its knowledge base, which includes the database for inpu t /ou tpu t membership functions and the rule base for inference rules. The idea in designing the system discussed in Section 4 is to let the system support the maximal amount of inference rules, and the adap- ta t ion of its knowledge base can be done by only updating the input lookup tables and the w~z~ lookup tables. Note that sizes of these lookup tables are small, and therefore they can be easily updated. In a recent design based on the implemented system discussed in this paper, adaptabil i ty was achieved by adding a secondary memory bank which stores a second set of lookup tables. Both the first and the secondary memory banks can be accessed by a host processor. When the fuzzy inference system is operating based on one set of lookup tables, the host processor can update the other set in a burst mode. Communication between the host processor and the fuzzy inference system, as well as switching between the two memory banks are

206 D . L . H U N G A N D W. F. Z A J A K

con t ro l l ed by t h e s y s t e m ' s con t ro l logic t h r o u g h h a n d s h a k i n g . T h e a d d e d

a d a p t a t i o n f ea tu re does n o t affect t h e s y s t e m ' s p roces s ing speed.

Al l s u b j e c t s d i scussed in th is sec t ion are u n d e r f u r t h e r s tudy .

The a u t h o r s w o u l d l ike to t h a n k X i I i n x f o r t h e i r k i n d suppor t .

R E F E R E N C E S

1. W.D. Detloff, K. E. Yount, and H. Watanabe, A fuzzy logic controller with recon- figurable, cascadable architecture, in Proc. 1989 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1989, pp. 474-478.

2. M. A. Eshera and S. C. Barash, Parallel rule-based fuzzy inference on mesh- connected systolic arrays, IEEE Expert, 27-35 (Winter 1989).

3. D .L . Hung and W. F. Zajak, Implementing a fuzzy inference engine using field programmable gate array, in Proe. IEEE International A S I C Conference, 1993, pp. 349-352.

4. C. Isik, Inference hardware for fuzzy rule-based systems, in Fuzzy Computing, M. M. Gupta and T. Yamakawa (Ed.), Elsevier Science Publishers B.V. (North- Holland), 1988, pp. 185-194.

5. C . C . Lee, Fuzzy logic in control systems: Fuzzy logic controller, Part II, IEEE Transactions on Systems, Man, and Cybernetics 20 (20):419-435 (Mar./Apr. 1990).

6. M.-H. Lim and Y. Takefuji, Implementing fuzzy rule-based systems on silicon chips, IEEE Expert 31-45 (Feb. 1990).

7. M. Mizumoto and H. Zimmerman, Comparison of fuzzy reasoning methods, Fuzzy Sets and Systems 18:253-283 (1982).

8. S. Shah and R. Horvath, A hardware digital fuzzy inference engine using standard integrated circuits, in Proc. 1st International Conference on Fuzzy Theory and Technology, Durham, NC, 1992, pp. 109-114.

9. M. Togai and H. Watanabe, Expert system on a chip: An engine for real-time approximate reasoning, IEEE Expert 56-58 (Fall 1986).

10. M. Togai and S. Chiu, A fuzzy logic chip and a fuzzy inference accelerator for real- time approximate reasoning, in Proc. 17th International Symposium on Multiple- Valued Logic, 1987, pp. 25-29.

11. A.P. Ungering, K. Thuener, and K. Goser, Architecture of a PDM VLSI fuzzy logic controller with pipelining and optimized chip area, in Proc. 2nd IEEE International Conference on Fuzzy Systems, Vol. 1, 1993, pp. 447-452~

12. H. Watanabe, W. D. Detloff, and K. E. Yount, A VLSI fuzzy logic inference engine for real-time process controk IEEE Journal of Solid-State Circuits 25 (2):376-382 (1990).

13. H. Watanabe, W. D. Detloff, and K. E. Yount, VLSI fuzzy chip and inference accelerator board systems, in Proc. 21st International Symposium on Multiple- Valued Logic, 1991, pp. 120-127.


14. T. Yamakawa, High-speed fuzzy controller hardware system: The Mega FIPS machine, Information Sciences 42 (1988).

15. T. Yamakawa, Fuzzy microprocessors--Rule chip and defuzzifier chip, in Proc. International Workshop on Fuzzy System Applications, Iizuka, Japan, Aug. 1988, pp. 51-52.

Received 12 June 1993; revised 6 November 1993 and 14 January 1994

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Design and implementation of a hardware fuzzy inference system