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BMAS 2004

Design-Adaptive Device Modeling in Model Compiler for Efficient and

Accurate Circuit Simulation

Bo Wan (Cadence)Emrah Acar, Sani Nassif (IBM Research - Austin)C. -J. Richard Shi (Univ. of Washington)

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Outline

• Background• Motivation• Design-adaptive Device Modeling• Experimental Results• Conclusions

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Manually Coded SPICE Built-in Models

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1

( ) /1

( ) /1ln arctan1 2

B C n V Vt

B C n V Vte C n Ve D

π− + ⋅

− − ⋅

⎛ ⎞ ⎛ ⎞+ − ⋅⎛ ⎞⋅ +⎜ ⎟ ⎜ ⎟⎜ ⎟+ ⎝ ⎠⎝ ⎠⎝ ⎠

Direct JacobianObject Creation

× =

10-30K lines C codesModel & Instance ParametersManually Matrix setup & loading

Compute matrix stampsCompute derivativesImplement multiple, self-consistent entry pointes for analysis types

Boundary / LimitingError prone, debug cost

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Mosfet Model Implementation in Spice3f5

High Cost!

Number Level 1 Level 3 BSIM3 BSIM4 BSIMSOI

If statements 501 609 822 1495 1757

Parameters in codes

32 38 399 610 615

Intermediate Variables

56 56 430 811 972

Total codelines

7,673 8,634 12,348 20,113 20,664

So much work & still NOT stable!

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BSIMSOIv3.2 Bug Fixes Report (2/24/2004)Bug description Involved c-file Bug reporter

1 GDoverlapCap/GSoverlapCap is not cancelled out

B3soild.c b3soiacld.c

M. Ahmed (Mentor Graphics)

2 Vgd/vgs replaced by vgmd/vgms B3soild.c (Renesas)

3 Here->B3SOIqinv for CapMod=2 B3soild.c S. Wu, P. Yao (Cadence)

4 Calculation of gcegb is removed B3soild.c H. Wan (UC Berkeley)

5 Gcegmb term is removed in ceqqb B3soild.c B. Ritchie(Cadence)

6 Vgme replaced by vgmb in ceqqd B3soild.c B. Ritchie(Cadence)

7 Gcegmb term is added in ceqqe B3soild.c H. Wan (UC Berkeley)

8 Vgme replaced by vgmb in ceqqgmid B3soild.c H. Wan (UC Berkeley)

9 Rbogy clamping value changed B3soild.c B. Ritchie (Cadence)

10 pParam->B3SOIacde wrong position B3soitemp.c B. Ritchie (Cadence)

11 dAbult_dVg is added when Abulk<0.01 B3soild.c C. Bittner, J. Watts (IBM)

(*(here->B3SOIDPbPtr)-=(-gddpb-Gmbs+gcdgb+gcddb

+gcdeb+gcdsb)+gcdgmb+gIdtotb);

No Implementation bugs using model compiler!

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Manual Implementation Issues

• Model implementation is more difficult than model creation. (time consuming, error-prone)

• Maintenance is a nightmare (“I hate this”)• A lot of new models created, few implemented• Modification of model is difficult• Requires independent implementations for

different simulator vendor• Same model, different results in different

simulators. Which one is trustworthy? No industrial standard!

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Model Compiler in a Nutshell

A Model Compiler is a design automation tool that supports fast prototyping of device models.

OutputModel CompilerMCAST

Input

1. Input: compact device models described in high level behavioral language VHDL-AMS/Verilog-AMS

2. Output: device code in C/C++ that can be directly compiled in target circuit simulators.

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Model Compiler Solution

• Use VHDL-AMS/Verilog-A for device model definition.

• Use device model compiler and support tools to create automatic device models that can be used in a wide range of simulation platforms.

• Use automation techniques to provide robustness better than manually coded built-in models.

• Use optimization techniques in model compiler to generate efficient models for circuit simulation.

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Related Work

• S. Liu, K. C. Hsu, P. Subramaniam, “ADMIT-ADVICE Modeling Interface Tool”, 1988

• A. T. Yang, and S. M. Kang, “iSMILE: A Novel Circuit Simulation Program with Emphasis on New Device Model Development”, 1989

• R. V. H. Booth, “An Extensible Compact Model Description Language and Compiler”, 2001

• L. Lemaitre, C. McAndrew, and S. Hamm, “ADMS-Automatic Device Model Synthesizer”, 2002

• Model compilers already available: ADS (Tiburon Design Automation), ADMS(Motorola), …

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MCAST ArchitectureV H D L -A M S

d escrip tio n o f a n ew d ev ice m o d e l

M C A S T

C /C ++ files o f th e n ew d ev ice

V H D L -A M S p arser

In term ed ia te fo rm at

D ev ice co d e g en era tio n O p tim iza tio n

A u to -d iffe ren tia tio nA u to -e lem en t

s tam p in g

In terface G en erato r

S P IC E 3f5 A d ap to r

IB M L ead er A d ap to r

S P E C T R E A d ap to r

C M I o f th e n ew d ev ice

C /C + + files o f th e n ew d ev ice

M C A S T

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Motivation of Design-Adaptive Modeling

• Automatically generated model can be slowerthan built-in model. Memory usage is larger (~5x) than built-in model.

• No previous work has taken user designinformation into account when generating device models.

• User design information (model/instance parameters, topology, etc) can be used to simplify the general device model and generate very efficient device models for fast circuit simulation.

• It is only feasible through a design automation tool such as model compiler.

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Design-adaptive Device Model

Adaptive Device Model

General Device Model

Adaptive Table Lookup Model

Fixed-Topology Adaptive Device

Model

Design-adaptive device model is a

more specific model of a device.

Characteristics:

• Fixed model parameters

• Fixed some or all instance parameters

• Specific topology

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MOSFET Design-adaptive Device Models

All model and instance parameters NOT fixed

General model(a)

D

G

S

B

W NOT fixed, L fixedDynamic model

(c)

D

G

S

B

W & L fixedDynamic model

(d)

D

G

S

B

Vbs=0

Vbs=0Dynamic model

(e)

D

G

S

B

Vgd fixed

Vgd fixedDynamic model

(f)

D

S

BG

Model parameters fixedInstance parameters NOT fixed

Dynamic model(b)

D

G

S

B G

+-

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Adaptive Low-dim Table Lookup Models

Vbs=0

Vbs=0Adaptive model

(d+e)

D

G

S

B

Vgd fixed

Vgd fixedAdaptive model

(d+f)

D

S

BG

+

- Vgd fixed

Vgd fixedAdaptive model

(d+e+f)

D

S

B

Vds

Vgs Vgs Vgs

2-D table lookups:IDS=IDS(Vgs,Vds) etc.

Vbs=0

2-D table lookups:IDS=IDS(Vgs,Vbs) etc.

Vbs

1-D table lookups:IDS=IDS(Vgs) etc.

+

-

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New Architecture for Design-adaptiveVHDL-AMS/Verilog-A device source code

Intermediate format

VHDL-A/Verilog-A parser

Optimization core

Code generation

C/C++ device codes for adaptive models

Dynamic linking

Circuit simulator source files

Circuit simulator with ability to simulate new device and user specific

design

User Design Info(original netlist)

Netlist Reader

Compile and linkAs adaptive loaded library or shared

objects

Netlist WritterNew netlist with adaptive models

binding with devices

Control Info(Table lookup density,

threshold #, etc.)

Lookup Table Generator

Lookup tables binding with

adaptive models

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New Netlist

Old netlist read in by MCAST

.MODEL mypmos PMOS (LEVEL=8 TOX=4.2E-9 …)

.MODEL mynmos NMOS (LEVEL=8 TOX=4.2E-9 …)

M1 out in vdd vdd mypmos w=30u l=6uM2 out in gnd gnd mynmos w=10u l=6u

New netlist generated by MCAST

* GENERAL MODEL GPMOS GENERATED BY MCAST .MODEL myp GPMOS TNOM=22 TOX=4.2E-9 ...* GENERAL MODEL GNMOS GENERATED BY MCAST.MODEL myn GNMOS TNOM=22 TOX=4.2E-9 ...

* DYNAMIC MODEL DM1: type (d+e), PMOS* model parameters: TNOM=22 TOX=4.2E-9 ...* instance parameters: w=30u l=6u* topology: Vbs=0 (e).MODEL mypmos DM1

* DYNAMIC MODEL DM2: type (d+e), NMOS* model parameters: TNOM=22 TOX=4.2E-9 ...* instance parameters: w=10u l=6u* topology: Vbs=0 (e).MODEL mynmos DM2

* USE DYNAMIC MODEL* NO INSTANCE PARAMETER NECESSARYN1 out in vdd vdd mypmosN2 out in gnd gnd mynmos

* STILL USE GENERAL MODELN3 out in vdd vdd myp w=25u l=6uN4 out in gnd gnd myn w=8u l=6u

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Experimental Results: Benchmark CircuitsIndex Circuit # MOS # ADM # ADTLM

1 One-Shot 22 4 22 VCO 10 2 23 Power AMP 4 0 24 Ring Oscillator 12 0 25 Boeing Comparator 38 2 26 Complex Cell 30 1 47 INV 2 0 28 INV Chain 8 0 29 NAND2 4 0 210 NOR2 4 0 211 AOI22 8 0 212 OAI22 16 0 213 ACCAS 1038 0 214 DFF 24 0 215 SRAM 6910 9 416 26-bit Adder 4274 18 617 13-bit Multiplier 9545 24 1618 12-bit Divider 3081 22 8

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Experimental Results: Accuracy

Inherently Very Accurate:

No loss of Accuracy

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Performance

1

3. 44

9. 25

13. 97

1

3. 4

8. 43

11. 83

1

3. 4

7. 688. 47

1

3. 3

5. 786. 07

1

3. 155. 08

02468

101214

Eval

Cos

t (N

orm

aliz

ed)

BSI MSOI BSI M4 BSI M3 Level 3 Level 1

AM( d+e) +Tabl e AM( d+e) Bui l t I n Aut o w/ Opt

Normalized Model Evaluation Cost Comparison

to Manually Coded Built-in Model:

Design-adaptive models are > 3x faster!

Adaptive table lookup models up to 9.25x faster!

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Transient Comparison

0123456789

INV

INV4

ACCASAdd

er MulDivid

er VCOP_A

MPCom

pSp

eedU

W/ O t abl e l ookup W/ t abl e l ookup

Speedup: 4x-8x

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Conclusions• High-level behavioral languages (VHDL-AMS/Verilog-AMS):

good for compact device modeling. They are becoming industry standard.

• Model compiler has realized the concept: “Device modeling in a day”

• Design-adaptive generated models are 1) Robust, 2) Efficient and 3) Accurate.

• Model compiler engine future applications:1. hierarchical behavioral design2. circuit optimization3. model debugging 4. statistical analysis