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DELAY INSERTION METHOD IN CLOCK SKEW SCHEDULING. BARIS TASKIN and IVAN S. KOURTEV ISPD 2005. High Performance Integrated Circuit Design Lab. Department of Electrical and Computer Engineering. Outline. Background and Motivation Topological Limitations on CSS Experimental Results - PowerPoint PPT Presentation
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DELAY INSERTION
METHOD IN CLOCK
SKEW SCHEDULING
BARIS TASKIN and IVAN S. KOURTEV
ISPD 2005
High Performance Integrated Circuit Design Lab. Department of Electrical and Computer Engineering
Outline
• Background and Motivation
• Topological Limitations on CSS
• Experimental Results
• Conclusions
Introduction
• High-Performance IC
• Clock skew scheduling
• Target: Minimum clock period
• Observe limitations
– Theoretically
Research Objective
Objective: Improve the efficiency and
results of clock skew scheduling through
systematic delay insertion
• Reconvergent paths
• Edge-sensitive circuits
• Level-sensitive circuits
• Local data path
• Circuit graph
System Modeling
D Q D Q
CLOCKi CLOCKf
DataI n
DataOut
Registeri
COMBI NATI ONALLOGI C
Registerf
CLK CLK
R1 R2
R4
R3R1 R2 R3
R4
Arrival timeAi
di Di
ai
T
Departuretime
CLK at Ri
CWL
Timing Parameters
Flip-Flop Operation
Positive edge-triggered
CLK
DATAI N
DATAOUT
Latch Operation
Positive level-sensitive
CLK
DATAI N
DATAOUT
CLK1
CLK2
CLK3
CLK1
CLK2
CLK3
Time Borrowing
Flip-Flop based Latch based
TFF = DP12 TL DP
12=TFF
Clock Skew
Tskew(i,f) = ti - tf
Clock signal
delay at the
initial register
Clock signal
delay at the
final register
D Q D Q
CLOCKi CLOCKf
DataI n
DataOut
Registeri
COMBI NATI ONALLOGI C
Registerf
CLK CLK
CLKsource
CLKi
CLKf
ti
tf
Tskew(i,f)
Clock Skew Scheduling
CIRCUIT
TOPOLOGY
CLOCKING
METHODOLOGY
MAX OP. FREQUENCY
TIMING SCHEDULE
CLOCKING SCHEDULE
SENSITIVITY*
INPUT OUTPUT
CSS: Edge-Sensitive
Zero clock skew
Non-zero clock skew
CLK1
CLK2
CLK3
TFF = DP12 TFF
skewed DP12=TFF
CLK1
CLK2
CLK3
Edge-Sensitive CSS Model
ifPm
ifskew
ifPM
ifskew
DT
DTTts
T
−≥
−≤..
min Linear Programming
(LP) model
1: J. P. Fishburn, Clock Skew Optimization, IEEE Transactions on Computers, Vol C-39, pp. 945-951, July 1990.
1
CLK1
CLK2
CLK3
CSS for Level-Sensitive
• Flip-flop-based
• Zero clock skew
• Latch-based
• Non-zero clock skew
CLK1
CLK2
CLK3
TFF = DP12 TL
skewed TL DP12=TFF
Level-Sensitive CSS Model
( ) ( )
ff
ff
fiskew
fiPMif
fiskew
fiPmif
iCQM
LWi
iDQMii
iCQm
LWi
iDQmii
ff
ff
j jFaninjjjjj
dD
aA
TTDDA
TTDda
DCTD
DAD
DCTd
Dad
STA
Hats
aADdMT
nn
n
nn
n
≥
≥
−++≥
−++≤
+−≥
+≥
+−≥
+≥
−≤
≥
⎥⎦
⎤⎢⎣
⎡−+++ ∑ ∑
∀ ≥∀
..
min|)(:| 1
Linear Programming
(LP) model
1: B. Taskin and I.S. Kourtev, Linearization of the Timing Analysis and Optimization Level-Sensitive Digital Synchronous Circuits, IEEE Transactions on VLSI, Vol 12, No 1, pp. 12-27, January 2004.
1
CSS Topological Limitations
• Series of data paths– Small practical limitations on CSS
• Data path cycles– Limit minimum clock period
• Reconvergent paths– Unexplored
– They do matter!
Linear Topology
• Series of local data paths
• Small practical limits for clock skew scheduling
€
Tmin = max max∀ if
DPMif −DPm
if( ),max
∀ iSi + H i( )
⎡ ⎣ ⎢
⎤ ⎦ ⎥
R1 R2 R3 R4 R5
Linear Topology Timing 1
DP23
CLK1
CLK2
CLK3
CLK4
CLK5
DP12 DP
45DP34
T T T T
Linear Topology Timing 2
DP23
CLK1
CLK2
CLK3
CLK4
CLK5
DP12 DP
45DP34
T T T T
Data Path Cycles
• Defined for retiming
• Limiting for clock skew scheduling
R1
R2
R3
R4
R5
€
Tmin =
DPM + S + H( )cycle
∑
r
Data Path Cycles Timing
CLK1
CLK2
CLK3
CLK4
CLK5
DP12 DP
23 DP34 DP
51DP45
T T T T T
Reconvergent Paths
• Common topology
• Lower bound Tmin
Rd
R1 Rn
Rc
R2 Rk
||||minmax
min 11 2121
21
+−+
++−
−=
pathpath
cc
pathpath
pathpath
rrHS
rrPDPD
T
Reconvergent Paths Timing
CLKd
CLKc
T T T T T
T T
PDpath1
PDpath2
Delay Insertion
||||intintminmax*
min 11 2121
2121
+−+
++−
−+−=
pathpath
cc
pathpath
pathyuncerta
pathyuncerta
pathpath
rrHS
rrDelayDelayPDPD
T
• Add delays to some paths
• Modify shortest and potentially longest path
delays
Rd
R1 Rn
Rc
R2 Rk
Reconvergent Path Timing DI
CLKd
CLKc
PDpath2
PDpath1+Delay
T*
T* T* T* T* T*
T*
CSS-DI for Edge-Sensitive
ifPm
ifskew
ifPM
ifskew
DT
DTTts
T
−≥
−≤..
min
I Mif
I mif
I mifI M
if
CSS-DI for Level-Sensitive
( ) ( )
ff
ff
fiskew
fiPMif
fiskew
fiPmif
iCQM
LWi
iDQMii
iCQm
LWi
iDQmii
ff
ff
j jFaninjjjjj
dD
aA
TTDDA
TTDda
DCTD
DAD
DCTd
Dad
STA
Hats
aADdMT
nn
n
nn
n
≥
≥
−++≥
−++≤
+−≥
+≥
+−≥
+≥
−≤
≥
⎥⎦
⎤⎢⎣
⎡−+++ ∑ ∑
∀ ≥∀
..
min|)(:| 1
I mif
I Mif
ImifI
Mif
Implementation Highlights
• Corner cases for delays
• Stand-alone frameworks
– Edge-sensitive
– Level-sensitive
• Reasonable run-times
– Under 2 minutes with barrier optimizer
Edge-Sensitive Results
Improvement
CLOCK SKEW SCHEDULING 28%
CLOCK SKEW SCHEDULING WITH
DELAY INSERTION34%
Edge-Triggered Circuits
0
10
20
30
40
50
60
70
80
90
100
s27s208.1
s298 s344 s349 s382 s386 s400s420.1
s444 s510 s526ns641 s713 s820 s832 s953 s1196 s1423s1488s1494s5378s9234s13207s15850s15850.1
s35932s38417s38584Average
ISCAS'89 Benchmark Circuits
Improvement (%)
Clock skew scheduling Clock skew scheduling and delay insertion
Level-Sensitive Results
Improvement
CLOCK SKEW SCHEDULING 29%
CLOCK SKEW SCHEDULING WITH
DELAY INSERTION34%
Level-Sens itive Circuits
0
1020
30
40
50
60
70
8090
100
s27s208.1
s298 s344 s349 s382 s386 s400s420.1
s444 s510 s526ns641 s713 s820 s832 s953 s1196 s1423s1488s1494s5378s9234s13207s15850s15850.1
s35932s38417s38584Average
ISCAS'89 Benchmark Circuits
Improvement (%)
Clock skew scheduling Clock skew scheduling and delay insertion
Quantitative Summary
• Delay insertion applicable to
– 41% of edge-triggered ISCAS’89 circuits
– 34% of the level-sensitive
• Improvement over conventional CSS
– 10% for edge-triggered (26% when applicable)
– 9% for level-sensitive (27% when applicable)
Conclusions
• Delay insertion to logic
– Systematic
• Requires topological analysis
– Linear, cycle, reconvergent
• Practical requirements
– Design budget for delay insertion
– Discrete delay values
– Placement
DELAY INSERTION METHOD IN CLOCK SKEW SCHEDULING
QUESTIONS?
Clock Period Minimization Problem - 1
• Objective function : min T
• Problem variables
– For each register Ri
• Earliest/latest arrival times ai, Ai
• Earliest/latest departure times di, Di
• Clock signal delay ti
Clock Period Minimization Problem - 2
• Problem Parameters
– For each register Ri
• Clock-to-output delay DCQ
• Data-to-output DDQ
• Setup time Si
• Hold time Hi
– For each local data path Ri Rj
• Data propagation time DPif
Practical Causes of Clock Skew
• Size Mismatches
– Buffer Size, Interconnect length
• Process Variations
– Leff, Tox etc.
• Temperature Gradients
• Power Supply Voltage Drop