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Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

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Page 1: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

Data Stack

Lecture 8.2

A VHDL Forth Core for FPGAs: Sect. 3

Page 2: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

ReturnStack

RmuxPmux

PCclrclk

pload

pinc

IRclrclkirload

FC16_control

plus1

R

Tin

Rin

R T

P

Pin

M

M P1

R

M

The FC16Forth Core

clkclr

rpop

rpush

psel rinsel

tsel(2:0)

rload

rdec

rsel

T

icode

E1(15:0)

B(1:4) DataStackclkclr

dpopdpush

ssel

nloadnsel

tload

y1(15:0)

T

0 11

1

0

0 2 3Tmux

Funit16

NN2

y(15:0)

y NN2E2E1S

S(1:16)

54 6 7

E2(15:0)

P(15:0)

M(15:0)

clr

clk

T(15:0)

N(15:0)

oe

we

Fcode(5:0)

digload

cs

LCD_RW

LCD_RS

LCD_E

FC16Forth Core

Page 3: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

Data Stack

Page 4: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

A 32 x 16 Stack

d(15:0) q(15:0)

clr

push

pop

clk

stack32x16 full

empty

Page 5: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

A 32 x 16 Stack Module

d(15:0)

clk

clr

push

pop

full

empty

q(15:0)

we

wr_addr

rd_addr

stack_ctrl32wr2_addr

dpram32x16amsel

0

1

DINA (DI)

ADDRA (A)

CLKA (WR_CLK)

ADDRB (DPRA)

DOUTB (DPO)

WEA (WR_EN)

stack32x16

open(SPO)

Page 6: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

entity stack_ctrl is port ( clr: in STD_LOGIC; clk: in STD_LOGIC; push: in STD_LOGIC; pop: in STD_LOGIC; we: out STD_LOGIC;

amsel: out STD_LOGIC; wr_addr: out STD_LOGIC_VECTOR (4 downto 0); rd_addr: out STD_LOGIC_VECTOR (4 downto 0); full: out STD_LOGIC; empty: out STD_LOGIC );end stack_ctrl; 

00000

11111

stack_ctrl32

rd_addrwr_addr

Page 7: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

 architecture stack_ctrl_arch of stack_ctrl issignal full_flag, empty_flag: STD_LOGIC;begin stk: process(clr, clk, push, pop, full_flag, empty_flag) variable push_addr, pop_addr: STD_LOGIC_VECTOR(4 downto 0); begin if clr = '1' then push_addr := "11111"; pop_addr := "00000"; empty_flag <= '1'; full_flag <= '0'; wr_addr <= "11111"; rd_addr <= "00000"; full <= full_flag; empty <= empty_flag;

stack_ctrl32

Page 8: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

elsif clk'event and clk = '1' then if push = '1' then

if pop = ‘0' then if full_flag = '0' then push_addr := push_addr - 1; pop_addr := push_addr + 1; empty_flag <= '0'; if push_addr = "11111” then full_flag <= '1'; push_addr := "00000"; end if; end if;

else –- write to top of stack (pop_addr) without pushing -- don’t change push_addr and pop_addr

end if;

stack_ctrl32

00000

11111

rd_addrwr_addr

Page 9: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

00000

11111

rd_addrwr_addr

stack_ctrl32

elsif pop = '1' then if empty_flag = '0' then pop_addr := pop_addr + 1; if full_flag = '0' then push_addr := push_addr + 1; end if; full_flag <= '0'; if pop_addr = "00000" then empty_flag <= '1'; end if; end if; end if; wr_addr <= push_addr; rd_addr <= pop_addr; end if;

Page 10: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

00000

11111

rd_addrwr_addr

stack_ctrl

full <= full_flag; empty <= empty_flag; if push = '1' and full_flag = '0' then we <= '1'; else we <= '0'; end if; if push = '1' and pop = ‘1' then amsel <= '1'; else amsel <= '0'; end if; end process stk;end stack_ctrl_arch;

Page 11: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

A 32 x 16 Stack Module

d(15:0)

clk

clr

push

pop

full

empty

q(15:0)

we

wr_addr

rd_addr

stack_ctrl32wr2_addr

dpram32x16amsel

0

1

DINA (DI)

ADDRA (A)

CLKA (WR_CLK)

ADDRB (DPRA)

DOUTB (DPO)

WEA (WR_EN)

stack32x16

open(SPO)

Page 12: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

Data Stack

Page 13: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

WHYP Data Stack InstructionsDUP ( n -- n n )SWAP ( a b -- b a )DROP ( a -- )OVER ( a b -- a b a )ROT ( a b c -- b c a )-ROT ( a b c -- c a b )NIP ( a b -- b )TUCK ( a b -- b a b )ROT_DROP ( a b c -- b c )ROT_DROP_SWAP ( a b c -- c b )2DUP ( a b -- a b a b )Note: 2DUP = OVER OVER

Page 14: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

Hex Opcode Name Function

0000 NOP No operation

0001 DUP Duplicate T and push data stack.N <= T; N2 <= N;

0002 SWAP Exchange T and N.T <= N; N <= T;

0003 DROP Drop T and pop data stack.T <= N; N <= N2;

0004 OVER Duplicate N into T and push data stack.T <= N; N <= T; N2 <= N;

0005 ROT Rotate top 3 elements on stack clockwise.T <= N2; N <= T; N2 <= N;

0006 -ROT Rotate top 3 elements on stack counter-clockwise.T <= N; N <= N2; N2 <= T;

0007 NIP Drop N and pop rest of data stack. T is unchanged.N <= N2;

0008 TUCK Duplicate T into N2 and push rest of data stack.N2 <= T;

0009 ROT_DROP Drop N2 and pop rest of data stack. T and N are unchanged.Equivalent to ROT DROP

000A ROT_DROP_SWAP Drop N2 and pop rest of data stack. T and N are exchanged.Equivalent to ROT DROP SWAP

Data Stack Instructions

Page 15: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

when dup =>

nload <= '1'; dpush <= '1';

Duplicate T and push data stack.

N <= T; N2 <= N;

DUP ( n -- n n )

Page 16: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

R

Tin

M

tsel(2:0)

DataStackclkclr

dpop

dpush

ssel

nloadnsel

tload

T

10 2 3Tmux

Funit1

N2

y(15:0)

y NN2E2E1S

54 6 7

T(15:0)

Fcode(5:0)

N

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

Exchange T and N.

T <= N; N <= T;when swap =>

tload <= '1'; nload <= '1';

tsel <= "111";

SWAP ( a b -- b a )

Page 17: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

R

Tin

M

tsel(2:0)

DataStackclkclr

dpop

dpush

ssel

nloadnsel

tload

T

10 2 3Tmux

Funit1

N2

y(15:0)

y NN2E2E1S

54 6 7

T(15:0)

Fcode(5:0)

N

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

Drop T and pop data stack.

T <= N; N <= N2; when drop =>

tload <= '1'; nload <= '1';

tsel <= "111"; nsel <= "01";

dpop <= '1';

DROP ( a -- )

Page 18: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

R

Tin

M

tsel(2:0)

DataStackclkclr

dpop

dpush

ssel

nloadnsel

tload

T

10 2 3Tmux

Funit1

N2

y(15:0)

y NN2E2E1S

54 6 7

T(15:0)

Fcode(5:0)

N

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

Duplicate N into T and push data stack.

T <= N; N <= T; N2 <= N;

when over => tload <= '1'; nload <= '1';

tsel <= "111";

dpush <= '1';

OVER ( a b -- a b a )

Page 19: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

R

Tin

M

tsel(2:0)

DataStackclkclr

dpop

dpush

ssel

nloadnsel

tload

T

10 2 3Tmux

Funit1

N2

y(15:0)

y NN2E2E1S

54 6 7

T(15:0)

Fcode(5:0)

N

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

Rotate top 3 elements on stack clockwise.

T <= N2; N <= T; N2 <= N;

when rot => tload <= '1'; nload <= '1'; tsel <= "110"; dpush <= '1'; dpop <= '1';

ROT ( a b c -- b c a )

Page 20: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

R

Tin

M

tsel(2:0)

DataStackclkclr

dpop

dpush

ssel

nloadnsel

tload

T

10 2 3Tmux

Funit1

N2

y(15:0)

y NN2E2E1S

54 6 7

T(15:0)

Fcode(5:0)

N

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

Rotate top 3 elements on stack counter-clockwise.

T <= N; N <= N2; N2 <= T; when mrot => tload <= '1'; nload <= '1'; tsel <= "111"; nsel <= "01"; ssel <= '1'; dpush <= '1'; dpop <= '1';

-ROT ( a b c -- c a b )

Page 21: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

Drop N and pop rest of data stack.

T is unchanged.

N <= N2;

when nip => nload <= '1'; nsel <= "01"; dpop <= '1';

NIP ( a b -- b )

Page 22: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

Duplicate T into N2 and push

rest of data stack.

N2 <= T;

when tuck => ssel <= '1'; dpush <= '1';

TUCK( a b -- b a b )

Page 23: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

ROT_DROP ( a b c -- b c )

Drop N2 and pop rest of data stack.

T and N are unchanged.

Equivalent to ROT DROP

when rot_drop =>

dpop <= '1';

Page 24: Data Stack Lecture 8.2 A VHDL Forth Core for FPGAs: Sect. 3

R

Tin

M

tsel(2:0)

DataStackclkclr

dpop

dpush

ssel

nloadnsel

tload

T

10 2 3Tmux

Funit1

N2

y(15:0)

y NN2E2E1S

54 6 7

T(15:0)

Fcode(5:0)

N

Tregclkclr

Nregclkclr

T1

Tin(15:0)

tload

nload

Nmux

Nin

T(15:0)

Smux

stack32x16

N1 T

N2

clkclr

dpop

dpush

empty

full

d

ssel

0

0

1

1

clkclr

dpop

dpush

ssel

nload

nsel(1:0)

tload

DataStack

y1(15:0)y1

2

N(15:0) N2(15:0)

nsel(1:0)

ROT_DROP_SWAP ( a b c -- c b )Drop N2 and pop rest of data stack. T and N are exchanged.Equivalent to ROT DROP SWAP

when rot_drop_swap => tload <= '1'; nload <= '1'; tsel <= "111"; dpop <= '1';