1

BSC072N04LD

Rev.2.0,2018-12-11Final Data Sheet

12

34

56

78

4

12

3

56

78

PG-TDSON-8-4

S1 G1 S2 G2

D1 D1 D2 D2

MOSFETOptiMOSTM-T2PowerTransistor,40V

Features·DualN-channel,logiclevel·FastswitchingMOSFETsforSMPS·OptimizedtechnologyforSynchronousRectification·Pb-freeplating;RoHScompliant·100%Avalanchetested·Halogen-freeaccordingtoIEC61249-2-21·SuperiorthermalresistanceProductValidationQualifiedforindustrialapplicationsaccordingtotherelevanttestsofJEDEC47/20/22

Table1KeyPerformanceParametersParameter Value UnitVDS 40 V

RDS(on),max 7.2 mΩ

ID 20 A

Type/OrderingCode Package Marking RelatedLinksBSC072N04LD SSO8 dual (TDSON-8-4) 072N04LD -

2

OptiMOSTM-T2PowerTransistor,40VBSC072N04LD

Rev.2.0,2018-12-11Final Data Sheet

TableofContentsDescription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

3

OptiMOSTM-T2PowerTransistor,40VBSC072N04LD

Rev.2.0,2018-12-11Final Data Sheet

1MaximumratingsatTA=25°C,unlessotherwisespecified,onetransistoractive

Table2MaximumratingsValues

Min. Typ. Max.Parameter Symbol Unit Note/TestCondition

Continuous drain current ID - - 20 A VGS=10V,TC=25°CPulsed drain current1) ID,pulse - - 80 A TA=25°CAvalanche energy, single pulse2) EAS - - 87 mJ ID=10A,RGS=25ΩGate source voltage VGS -16 - 16 V -

Power dissipation Ptot - - 65 W TC=25°C

Operating and storage temperature Tj,Tstg -55 - 175 °C IEC climatic category; DIN IEC 68-1:55/175/56

2Thermalcharacteristics

Table3ThermalcharacteristicsValues

Min. Typ. Max.Parameter Symbol Unit Note/TestCondition

Thermal resistance, junction - case,bottom RthJC - - 2.3 °C/W -

Device on PCB,6 cm² cooling area3) RthJA - - 60 °C/W -

Device on PCB,minimal footprint4) RthJA - - 100 °C/W -

3ElectricalcharacteristicsatTj=25°C,unlessotherwisespecified

Table4StaticcharacteristicsValues

Min. Typ. Max.Parameter Symbol Unit Note/TestCondition

Drain-source breakdown voltage V(BR)DSS 40 - - V VGS=0V,ID=1mAGate threshold voltage VGS(th) 1.2 1.7 2.2 V VDS=VGS,ID=30µA

Zero gate voltage drain current IDSS --

0.110

1100 µA VDS=40V,VGS=0V,Tj=25°C

VDS=40V,VGS=0V,Tj=125°C

Gate-source leakage current IGSS - - 100 nA VGS=20V,VDS=0V

Drain-source on-state resistance RDS(on)--

6.58.0

7.29.2 mΩ VGS=10V,ID=17A

VGS=4.5V,ID=10A

1) See Diagram 3 for more detailed information2) See Diagram 13 for more detailed information3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection.PCB is vertical in still air.4) device mounted on a minimum pad (one layer, 70 µm thick)

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OptiMOSTM-T2PowerTransistor,40VBSC072N04LD

Rev.2.0,2018-12-11Final Data Sheet

Table5DynamiccharacteristicsValues

Min. Typ. Max.Parameter Symbol Unit Note/TestCondition

Input capacitance1) Ciss - 3070 3990 pF VGS=0V,VDS=20V,f=1MHzOutput capacitance1) Coss - 680 880 pF VGS=0V,VDS=20V,f=1MHzReverse transfer capacitance1) Crss - 36 72 pF VGS=0V,VDS=20V,f=1MHz

Turn-on delay time td(on) - 9 - ns VDD=20V,VGS=10V,ID=20A,RG,ext=11Ω

Rise time tr - 4 - ns VDD=20V,VGS=10V,ID=20A,RG,ext=11Ω

Turn-off delay time td(off) - 50 - ns VDD=20V,VGS=10V,ID=20A,RG,ext=11Ω

Fall time tf - 25 - ns VDD=20V,VGS=10V,ID=20A,RG,ext=11Ω

Table6Gatechargecharacteristics2)Values

Min. Typ. Max.Parameter Symbol Unit Note/TestCondition

Gate to source charge Qgs - 9 13 nC VDD=20V,ID=20A,VGS=0to10VGate to drain charge Qgd - 4.1 8.2 nC VDD=20V,ID=20A,VGS=0to10VGate charge total1) Qg - 39 52 nC VDD=20V,ID=20A,VGS=0to10VGate plateau voltage Vplateau - 3.1 - V VDD=20V,ID=20A,VGS=0to10V

Table7ReversediodeValues

Min. Typ. Max.Parameter Symbol Unit Note/TestCondition

Diode continuous forward current IS - - 20 A TC=25°CDiode pulse current IS,pulse - - 80 A TC=25°CDiode forward voltage VSD - 0.85 1.1 V VGS=0V,IF=17A,Tj=25°CReverse recovery time1) trr - 35 - ns VR=15V,IF=9A,diF/dt=100A/µsReverse recovery charge1) Qrr - 35 - nC VR=15V,IF=9A,diF/dt=100A/µs

1) Defined by design. Not subject to production test.2) See ″Gate charge waveforms″ for parameter definition

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OptiMOSTM-T2PowerTransistor,40VBSC072N04LD

Rev.2.0,2018-12-11Final Data Sheet

4Electricalcharacteristicsdiagrams

Diagram1:Powerdissipation

TA[°C]

Ptot[W

]

0 25 50 75 100 125 150 175 2000

10

20

30

40

50

60

70

Ptot=f(TA),minimalfootprint

Diagram2:Draincurrent

TA[°C]

ID[A

]

0 25 50 75 100 125 150 175 2000

10

20

30

40

50

60

70

80

silicon limit

package limit

ID=f(TA);minimalfootprint

Diagram3:Safeoperatingarea

VDS[V]

ID[A

]

10-1 100 101 10210-1

100

101

102

1 µs

10 µs100 µs

1 ms

10 ms

DC

ID=f(VDS);TC=25°C;D=0;parameter:tp

Diagram4:Max.transientthermalimpedance

tp[s]

ZthJC[K

/W]

10-5 10-4 10-3 10-2 10-1 10010-2

10-1

100

101

single pulse0.010.020.050.10.20.5

ZthJC=f(tp);parameter:D=tp/T

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OptiMOSTM-T2PowerTransistor,40VBSC072N04LD

Rev.2.0,2018-12-11Final Data Sheet

Diagram5:Typ.outputcharacteristics

VDS[V]

ID[A

]

0.0 1.0 2.0 3.0 4.00

10

20

30

40

50

60

70

804 V

4.5 V10 V

3.5 V

3 V

ID=f(VDS),Tj=25°C;parameter:VGS

Diagram6:Typ.drain-sourceonresistance

ID[A]

RDS(on

) [m

Ω]

0 10 20 30 40 50 60 70 800

10

20

30

40

3 V

3.5 V

4 V

4.5 V

10 V

RDS(on)=f(ID),Tj=25°C;parameter:VGS

Diagram7:Typ.transfercharacteristics

VGS[V]

ID[A

]

0 1 2 3 4 50

10

20

30

40

50

60

70

80

175 °C

25 °C

ID=f(VGS),|VDS|>2|ID|RDS(on)max;parameter:Tj

Diagram8:Typ.drain-sourceonresistance

VGS[V]

RDS(on

) [m

Ω]

0 2 4 6 8 100.0

2.5

5.0

7.5

10.0

12.5

15.0

17.5

20.0

175 °C

25 °C

RDS(on)=f(VGS),ID=17A;parameter:Tj

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OptiMOSTM-T2PowerTransistor,40VBSC072N04LD

Rev.2.0,2018-12-11Final Data Sheet

Diagram9:Normalizeddrain-sourceonresistance

Tj[°C]

RDS(on

) (normalizedto

25°C)

-80 -40 0 40 80 120 160 2000.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

RDS(on)=f(Tj),ID=17A,VGS=10V

Diagram10:Typ.gatethresholdvoltage

Tj[°C]

VGS(th) [V]

-80 -40 0 40 80 120 160 2000.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

300 µA

30 µA

VGS(th=f(Tj),VGS=VDS;parameter:ID

Diagram11:Typ.capacitances

VDS[V]

C[p

F]

0 5 10 15 20 25 30 35 40101

102

103

104

Ciss

Coss

Crss

C=f(VDS);VGS=0V;f=1MHz

Diagram12:Forwardcharacteristicsofreversediode

VSD[V]

IF [A]

0.00 0.25 0.50 0.75 1.00 1.25 1.5010-1

100

101

102

25 °C25 °C, max175 °C175 °C, max

IF=f(VSD);parameter:Tj

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OptiMOSTM-T2PowerTransistor,40VBSC072N04LD

Rev.2.0,2018-12-11Final Data Sheet

Diagram13:Avalanchecharacteristics

tAV[µs]

IAV [A]

100 101 102 10310-1

100

101

102

25 °C

100 °C

150 °C

IAS=f(tAV);RGS=25Ω;parameter:Tj,start

Diagram14:Typ.gatecharge

Qgate[nC]

VGS [V]

0 5 10 15 20 25 30 35 400

2

4

6

8

108 V20 V32 V

VGS=f(Qgate),ID=20Apulsed,Tj=25°C;parameter:VDD

Diagram15:Drain-sourcebreakdownvoltage

Tj[°C]

VBR(DSS

) [V]

-80 -40 0 40 80 120 160 20038

39

40

41

42

43

44

VBR(DSS)=f(Tj);ID=1mA

Diagram Gate charge waveforms

9

OptiMOSTM-T2PowerTransistor,40VBSC072N04LD

Rev.2.0,2018-12-11Final Data Sheet

5PackageOutlines

0.05

1.27

Θ

MILLIMETERS

DIMENSIONS

0.90 1.10

D1

A

A1

b

b1

D

D2

E

E1

E2

e

L

aaa

0.34 0.54

0.02 0.22

5.95 6.35

4.035 4.235

0.45 0.65

MIN. MAX.

M 0.45 0.65

8.5° 11.5°

4mm

01

ISSUE DATE

31.07.2018

DOCUMENT NO.

1 3

4.95 5.35

SCALE 5:1

20

Z8B00189767

REVISION

EUROPEAN PROJECTION

0.10ddd

0.15 0.35

4.20 4.40

0.50 0.70

5.70 6.10

4.075 4.275

E3

0.15 0.35E4

Figure1OutlineSSO8dual(TDSON-8-4),dimensionsinmm

10

OptiMOSTM-T2PowerTransistor,40VBSC072N04LD

Rev.2.0,2018-12-11Final Data Sheet

RevisionHistoryBSC072N04LD

Revision:2018-12-11,Rev.2.0

Previous Revision

Revision Date Subjects (major changes since last revision)

2.0 2018-12-11 Release of final version

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