CSE140L: Components and Design CSE140L: Components and Design Techniques for Digital Systems Lab

Introduction

Tajana Simunic Rosing

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Welcome to CSE 140L!

• Instructor: Tajana Simunic Rosing• Email: tajana@ucsd.edu; please put CSE140L in the subject lineEmail: tajana@ucsd.edu; please put CSE140L in the subject line• Ph. 858 534-4868• Office Hours: TW 1-2pm, CSE 2118

• Instructor’s Assistant: Sheila Manalo – Email: shmanalo@ucsd.edua s a a o@ucsd edu– Phone: (858) 534-8873

• TA: Raid Ayoub– Email: rayoub@cs.ucsd.edu– Office hours: WF 10-12pm in CSE 3219p

• Class Website:– http://www.cse.ucsd.edu/classes/wi09/cse140L/

• Grades: http://webct.ucsd.edu

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Course Descriptionp• Prerequisites:

– CSE 20 or Math 15A, and CSE 30. – CSE 140 must be taken concurrently

• Objective:– Introduce digital components and system design concepts throughIntroduce digital components and system design concepts through

hands-on experience in a lab• Grading

– Labs (4): 70%Labs (4): 70%• First two labs will use simulation only, the 2nd two labs will use Xilix HW• Schedule for lab access; need to schedule a demo to TA by lab due date• Go to Robin Knox [rsknox@cs.ucsd.edu] office in CSE 2248 to program

your student ID for access to CSE 3219your student ID for access to CSE 3219– Monday-Thursday 10-12:30 and 2:00-4:00

– Final exam: 30%– Regrade requests: turn in a written request at the end of the class

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gwhere your work is returned

Textbook and Recommended Readingsg• Required textbook:

– Contemporary Logic Design byContemporary Logic Design by R. Katz & G. Borriello

• Recommended textbook:– Digital Design by F. Vahid

• Lecture slides are derived from the

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slides designed for both books

Software and Hardware we will use• Freely available in CSE 3219 lab:

– Xilinx Virtex-II Pro Development SystemXilinx Virtex-II Pro Development System (XUPV2P)

http://www.xilinx.com/univ/xupv2p.htmlPC in the lab already have ISE tools installed– PC in the lab already have ISE tools installed. You can program boards in the lab only!

– You can download on your own PC Webpacktools to implement and test your design; thistools to implement and test your design; this is all that will be needed for the first two labs.

www.xilinx.com/ise/logic_design_prod/webpack.htm

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Outline• Introduction to Xilinx board & tools• Transistors

– How they work– How to build basic gates out of transistors– How to evaluate delayHow to evaluate delay

• Pass gates• Muxes

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Basic FPGA Architecture

Overview• All Xilinx FPGAs contain the same basic

resourcesresources– Slices grouped into configurable logic blocks - CLBs

• Contain combinatorial logic and register resources

– Input/Output Blocks - IOBs• Interface between the FPGA and the outside world

P bl i t t– Programmable interconnect– Other resources

• ProcessorProcessor• Memory• Multipliers• ….

Virtex-II Architecture

I/O Blocks (IOBs)I/O Blocks (IOBs)Block SelectRAM™Block SelectRAM™resourceresource

ProgrammableProgrammable

C fi blC fi bl

Dedicated multipliersDedicated multipliers

Programmable interconnectProgrammable interconnect

ConfigurableLogic Blocks (CLBs)

ConfigurableLogic Blocks (CLBs)

Clock Management (DCMs, BUFGMUXes)Clock Management (DCMs, BUFGMUXes)(DCMs, BUFGMUXes)(DCMs, BUFGMUXes)

Xilinx Design FlowXilinx Design Flow

ISE Project Navigatorj g

• Built around theBuilt around the Xilinx design flow– Access to synthesis

and schematic toolsand schematic tools• Including third-

party synthesis tools

– Implement your design with a simple double-click

• Fine-tune with easy-to-access software options

Xilinx Design Flowg

Plan & HDL RTLCreate Code/Budget

HDL RTLSimulation

SynthesizeFunctionalImplement

Create Code/Schematic

Translate

Map

Synthesizeto create netlist

FunctionalSimulation

Place & Route

CreateBIT File

Attain Timing Closure

TimingSimulation

Combinational circuit building blocks:Transistors gates and timingTransistors, gates and timing

Tajana Simunic Rosing

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The CMOS Circuit• CMOS circuit

– Consists of N and PMOS transistors– Both N and PMOS operate similar to basic switches

A positivevoltage here

...attracts electrons here,turning the channel

01gate

nMOS

gateoxide

voltage here... turning the channelbetween source and drain

into aconductor.

does notconduct

conducts

gate

source drainoxide IC package

conduct

1gate

pMOS0

(a) IC

does notconduct

gate

conductsSilicon -- not quite a conductor or insulator:Semiconductor

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Semiconductor

Non-Ideal Gate Behavior – Delay

a Fa F

a

F

a

Time

• Real gates don’t respond immediately to input changes– Rise/fall time

Delay

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– Delay– Pulse width

Charge/discharge in CMOSg g• Calculate on resistance• Calculate capacitance of the gates circuit is drivingCalculate capacitance of the gates circuit is driving• Get RC delay & use it as an estimate of circuit delay

– Vout = Vdd ( 1- e-t/RpC)

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Source: Prof. Subhashish Mitra

Timing analysis in gatesg y gxy F

OR

Fxy

AND

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F= x or y

1

x y

F’

1y

x

1

F=x & yF’

0

y

0

y

x0

xy

0

CSE140: Components and Design Techniques CSE140: Components and Design Techniques for Digital Systems

Muxes and demuxes

Tajana Simunic Rosing

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Pass transistor – Mux building block

• Connects X & Y when A=1, else X & Y disconnected– A_b = not(A)

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Fig source: Prof. Subhashish Mitra

Multiplexor (Mux)p ( )• Mux routes one of its N data inputs to its one output,

based on binary value of select inputsy p• 4 input mux needs 2 select inputs to indicate which input to route

through• 8 input mux 3 select inputs • N inputs log2(N) selects

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Mux Internal Design

2×1

i0

2×1

i02×1

i0A YA Ai1i0

s01

di1i0

s00

di1i0

s0

dAB Y YA

BAB

2x1 mux

• Selects input to connect to Y– selA == 1: connects A to Y– selB == 1: connects B to Y

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Fig source: Prof. Subhashish Mitra

Multiplexers/selectorsp• 2:1 mux: Z = A'I0 + AI1• 4:1 mux: Z = A'B'I0 + A'BI1 + AB'I2 + ABI34:1 mux: Z A B I0 + A BI1 + AB I2 + ABI3• 8:1 mux: Z = A'B'C'I0 + A'B'CI1 + A'BC'I2 + A'BCI3 +

AB'C'I4 + AB'CI5 + ABC'I6 + ABCI7

2 -1I0I1k=0

n• In general: Z = (mkIk)I1I2I3I4I5

8:1mux

Z

I0

0

– in minterm shorthand form for a 2n:1 Mux

I5I6I7

A B C

I0I1I2I3

4:1mux

ZI0I1

2:1mux Z

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A B CA BA

N-bit Mux Examplep

• Four possible display itemsT t (T) A il ll (A) I t t (I)– Temperature (T), Average miles-per-gallon (A), Instantaneous mpg (I), and Miles remaining (M) -- each is 8-bits wide

– Choose which to display using two inputs x and y– Use 8-bit 4x1 mux

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Use 8 bit 4x1 mux

Multiplexers as general-purpose logicp g p p g• A 2n-1:1 multiplexer can implement any function of n variables

– with n-1 variables used as control inputs and– the data inputs tied to the last variable or its complement

• Example: F(A,B,C) = m0 + m2 + m6 + m7

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Demultiplexers/decodersp• Decoders/demultiplexers: general concept

– single data input, n control inputs, 2n outputsg p , p , p– control inputs (called “selects” (S)) represent binary index of

output to which the input is connected– data input usually called “enable” (G)

1:2 Decoder:O0 = G S’O1 = G S 3:8 Decoder:

data input usually called enable (G)

O1 = G S

2:4 Decoder: O0 = G S1’ S0’

3:8 Decoder: O0 = G S2’ S1’ S0’O1 = G S2’ S1’ S0O2 = G S2’ S1 S0’O3 = G S2’ S1 S0O0 = G S1 S0

O1 = G S1’ S0O2 = G S1 S0’O3 = G S1 S0

O3 = G S2 S1 S0O4 = G S2 S1’ S0’O5 = G S2 S1’ S0O6 = G S2 S1 S0’O7 = G S2 S1 S0

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O7 = G S2 S1 S0

Gate level implementation of demultiplexersp p• 1:2 decoders

• 2:4 decoders

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Demultiplexers as general-purpose logic (cont’d)

• F1 = A'BC'D + A'B'CD + ABCD• F2 = ABC'D' + ABC• F3 = (A' + B' + C' + D')

0 A'B'C'D'1 A'B'C'D2 A'B'CD'3 A'B'CD4 A'BC'D'5 A'BC'D6 A'BCD'7 A'BCD7 A'BCD8 AB'C'D'9 AB'C'D10 AB'CD'11 AB'CD

4:16DECEnable

11 AB CD12 ABC'D'13 ABC'D14 ABCD'15 ABCD

27A B C D

Mux and demux combination• Uses in multi-point connections

B0 B1A0 A1

multiple input sourcesMUX

A B

Sa SbMUX

A B

Sum

multiple output destinationsSs DEMUX

28S0 S1

Mux example: Logical function unitp g• Multi-purpose function block

– 3 control inputs to specify operation to perform on operandsp p y p p p– 2 data inputs for operands– 1 output of the same bit-width as operands

C0 C1 C2 Function Comments0 0 0 1 always 1 00 0 0 1 always 10 0 1 A + B logical OR0 1 0 (A • B)' logical NAND0 1 1 A xor B logical xor

1234

8:1 MUXF

1 0 0 A xnor B logical xnor1 0 1 A • B logical AND1 1 0 (A + B)' logical NOR1 1 1 0 always 0

4567S2 S1 S0

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1 1 1 0 always 0

C2C0 C1

CSE140: Components and Design Techniques CSE140: Components and Design Techniques for Digital Systems

Arithmetic circuits

Tajana Simunic Rosing

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Adder/subtractor

A0 B0B0'A1 B1B1'A2 B2B2'A3 B3B3'

0 1 SelSelSel 0 1 0 10 1 Sel

A B

Cout

Sum

Cin Add'Subtract

A B

Cout

Sum

Cin

A B

Cout

Sum

CinA B

Cout

Sum

Cin

Overflow

S3 S2 S1 S0

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Overflow

Ripple-carry adder critical delay pathAB

Cin Cout

@0@0

@N

@1 @N+1 4 stageadder

A0

0

S0 @2

pp y y p

AB

Cout@0@0

@

@1

@N+2 B0

A1B1

C1 @2

S1 @3C2 @4late

arrivingsignal

two gate delaysto compute Cout

B1

A2B2

C2 @4

S2 @5C3 @6B2

A3B3

C3 @6

S3 @7Cout @8

S0, C1 Valid S1, C2 Valid S2, C3 Valid S3, C4 Valid

Cout @8

32T0 T2 T4 T6 T8

Carry-lookaheady• Evaluate Sum and Ci+1

– Sum = Ai xor Bi xor Ci – Ci+1 = Ai Bi + Ai Ci + Bi Ci

= Ai Bi + Ci (Ai xor Bi)

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Carry-lookahead implementationy p• Adder with propagate and generate outputs

Pi @ 1 gate delay

Ci Si @ 2 gate delays

BiAi

increasingly complexlogic for carries

C0

C0C0

P0P1P2P3

Gi @ 1 gate delay

C0

C0

C0P0

P0

P0G0

G0G0

C1 @ 3P1

P1

P1

G1P2

P2

P2

P2

P3

P3

G3

P0

G0P1

P1

G1

G1

C2 @ 3

P2

P2 G2

G2

C3 @ 3

P3

P3C4 @ 3

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Carry-lookahead implementation (cont’d)y p ( )• Carry-lookahead logic generates individual carries

– sums computed much more quickly in parallelh t f l i i ith t

0 A0B0

0

S0 @2

– however, cost of carry logic increases with more stages

A0B0

S0 @2C1 @2 A1

B1

C1 @3

S1 @4

A1B1

S1 @3C2 @4 A2

B2

C2 @3

S2 @4

A2B2

S2 @5

3

C3 @6

S3 @

A3B3

C3 @3

S3 @4

C4 @3 C4 @3

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A3B3

S3 @7Cout @8

C4 @3 C4 @3

Carry-lookahead adderwith cascaded carry lookahead logicwith cascaded carry-lookahead logic

• Carry-lookahead adder4 four bit adders with internal carry lookahead

G = G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0

4 44 44 44 4

– 4 four-bit adders with internal carry lookahead– second level carry lookahead unit extends lookahead to 16 bits

P = P3 P2 P1 P0

A[15-12] B[15-12]C12

A[11-8] B[11-8]C8

A[7-4] B[7-4]C4

A[3-0] B[3-0]C0@0

4 4

P G

4-bit Adder

4 4

P G

4-bit Adder

4 4

P G

4-bit Adder

4 4

P G

4-bit Adder

@3@2@4

@3@2@5

@3@2@5

@3@2S[15-12] S[11-8] S[7-4]

@7@8@8S[3-0]

@4

4444

Lookahead Carry UnitC0

P0 G0P1 G1P2 G2P3 G3 C3 C2 C1

C0

P3-0 G3-0

C4

@@

@4 @0C16

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P3-0 G3-0@5@3

C1 = G0 + P0 C0C2 = G1 + P1 G0 + P1 P0 C0

Carry-select addery• Redundant hardware to make carry calculation go faster

– compute two high-order sums in parallel while waiting for carry-ini i i 0 d th i i i 1– one assuming carry-in is 0 and another assuming carry-in is 1

– select correct result once carry-in is finally computed

4-bit adder[7:4]

1C8 adderhigh

0C8adder

low

4-bit adder[7:4]

4-Bit Adder[3:0]

C0C4five2:1 mux

0101010101

37C8 S7 S6 S5 S4 S3 S2 S1 S0

What we’ve covered thus far

• Xilinx Virtex II Pro board and tools• Transistor design• Building basic gates from CMOS • Delay estimates• Pass transistors• Muxes• Muxes

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N-MOS Tutorial – channel formation• The Semiconductor-Oxide-Metal Combination in the Gate is effectively

a Parallel Plate Capacitor

gate

nMOS

• Vgs = 0 -> lots of positive charge in p-type material, no current

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• Source: http://www.netsoc.tcd.ie/~mcgettrs/hvmenu/tutorials/TOCcmostran.htm

N-MOS Tutorial – channel formation (cont.)( )• Vgs >0 -> + charge on the gate, - charge attracted to the oxide, +

charge chased away from the oxide

• Vgs=Vt -> channel of negative charge forms under the oxide; the oxide is depleted of + charge; Vt = threshold voltage

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N-MOS Tutorial – channel formation (cont.)( )• Vgs>Vt -> negative charge carriers form under the oxide; free electrons

are thermally generated and form a conduction channel through which t flcurrent can flow

• Vgs>Vt & Vds = 0 -> channel present, but no current flows

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N-MOS Tutorial: Current flow• Vds > 0 -> electric field (E) set up between source and

drain, accelerates electrons with velocity vd, small current , y ,forms between source and drain

– Cox : oxide capacitance = ox / tox (oxide permittivity ox and thickness tox); : mobility of charge carriers; W/L gate width and length y g g g

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N-MOS Tutorial: Current flow• Vds >= Vgs-Vt -> channel pinched off, saturated; constant

current flows from drain to source– Cox : oxide capacitance = ox / tox (oxide permittivity ox and thickness tox);

: mobility of charge carriers; W/L gate width and length

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How about P-MOS?• Everything is the same, but polarities of voltages reverse.

Mobility () is 2x smaller, so 2x less current is generated if y () , gall other parameters are kept constant– e.g. PMOS turns on when Vgs < Vt and both are <0

gate

pMOS

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Resistance• Resistivity

– Function of:• resistivity r, thickness t : defined by technology• Width W, length L: defined by designer

– Approximate ON transistor with a resistorApproximate ON transistor with a resistor• R = r’ L/W• L is usually minimum; change only W

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Source: Prof. Subhashish Mitra

Capacitance & Timing estimatesp g• Capacitor

– Stores charge Q = C V (capacitance C; voltage V)g ( p ; g )– Current: dQ/dt = C dV/dt

• Timing estimateD t C dV/ i C dV / (V/R ) R C dV/V– D t = C dV/ i = C dV / (V/Rtrans) = RtransC dV/V

• Delay: time to go from 50% to 50% of waveform

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Source: Prof. Subhashish Mitra