CSCI-641/EENG-641 Computer Architecture

  • View
    35

  • Download
    1

Embed Size (px)

DESCRIPTION

CSCI-641/EENG-641 Computer Architecture. Khurram Kazi. Major sources of the slides for this lecture. http://fourier.eng.hmc.edu/e85/lectures/instruction/node7.html http://www.ece.ucdavis.edu/~vojin/CLASSES/EEC180B/Spring99/lab6.pdf http://fourier.eng.hmc.edu/e85/lectures/r3000-isa.html - PowerPoint PPT Presentation

Text of CSCI-641/EENG-641 Computer Architecture

  • CSCI 641 EENG 641 *CSCI-641/EENG-641

    Computer ArchitectureKhurram Kazi

    K KaziCSCI 641/EENG 641 *

  • Major sources of the slides for this lecture

    http://fourier.eng.hmc.edu/e85/lectures/instruction/node7.htmlhttp://www.ece.ucdavis.edu/~vojin/CLASSES/EEC180B/Spring99/lab6.pdfhttp://fourier.eng.hmc.edu/e85/lectures/r3000-isa.htmlDigital Design and Computer Architecture book by David Money Harris and Sarah L. Harris. Chapter 6 Architecturehttp://www.hirstbrook.com/cod/Chapter2B.pdf

    K KaziCSCI 641/EENG 641 *

    K KaziCSCI 641/EENG 641 *

  • Assembly languageAssembly language is the human readable representation of computers native languageEach instruction specifies both the operations to perform and the operands on which to operateadd is called the mnemonic and indicates what operation to performThe operation is performed on b and c, the source operands, and results is written to a, the destination operandDesign Principle 1: Simplicity favors regularityInstructions with a consistent number of operands in this case, two sources and one destination are easier to encode and handle in hardware. More complex high-level code translates into multiple MIPS instructionsK KaziCSCI 641/EENG 641 *

    High-level codeMIPS Assembly codea = b + c;add a, b, ca = b c;sub a , b, c

    High-level code (complex)MIPS Assembly codea = b + c d;sub t, c, d # t = c-dadd a , b, t # a=b+t

    K KaziCSCI 641/EENG 641 *

  • Assembly languageTo execute complex operation multiple assembly language instructions are performed Design Principle 2: Make the common case fastThe MIPS instruction set makes the common case fast by including only simple, commonly used instructions. The number of instructions is kept small so that the hardware required to decode the instructions and its operands can be simple, small and fast.Less frequent more elaborate operations are performed using sequence of multiples simple instructions

    K KaziCSCI 641/EENG 641 *

    High-level codeMIPS Assembly codea = b + c;add a, b, ca = b c;sub a , b, c

    High-level code (complex)MIPS Assembly codea = b + c d;sub t, c, d # t = c-dadd a, b, t # a=b+t

    K KaziCSCI 641/EENG 641 *

  • Assembly language: Operands: Registers, Memory, and ConstantsInstruction operates on OperandsVariables a, b, and c, all are called operands. Computer operates on 0s and 1sOperands are stored in registers or memory, or they may be constants stored in the instruction itselfComputers use various locations to hold operands, to optimize for speed and data capacityRegisters are accessed quickly compared to memoryRegisters can hold very limited amount of data whereas memories hold large amounts of dataMIPS architecture uses 32 register, called register set or register fileDesign Principle 3: Smaller is fasterK KaziCSCI 641/EENG 641 *

    K KaziCSCI 641/EENG 641 *

  • Translating high-level code to assemblyK KaziCSCI 641/EENG 641 *

    High level codeAssembly language a = b c;# $s0=a, $s1=b, $s2=c, $s3=f, $s4=g, #s5=h,f = (g + h) (i + j)#$s6=i, $s7=jsub $s0, $s1, $s2 #a = b - cadd $t0, $s4, $s5 #$t0 = g + hadd $t1, $s6, $s7 # $t1 = i + jsub $s3, $t0, $t1 # f = (g + h) (i + j)

    K KaziCSCI 641/EENG 641 *

  • K KaziCSCI 641/EENG 641 *MIPS register set

    NameNumberUse$00The constant value 0$at1Assembler temporary$v0 $v12 3Procedure return values$a0 $a34 7Procedure arguments$t0 $t78 15Temporary variables$s0 $s716 23Saved variables$t8 $t924 25Temporary variables$k0 $k126 27Operating system (OS) temporaries$gp28Global pointer$sp29Stack pointer$fp30Frame pointer$ra31Procedure return address

    K KaziCSCI 641/EENG 641 *

  • Registers within MIPS ProcessorRegister file (RF): 32 registers ($0 through $31), each for a word of 32 bits (4 bytes); $0 always holds zero $sp (29) is the stack pointer (SP) which always points to the top item of a stack in the memory; $ra (31) always holds the return address from a subroutine The table in the previous shows the conventional usage of all 32 registersK KaziCSCI 641/EENG 641 *

    K KaziCSCI 641/EENG 641 *

  • Description of Register FileThere are two read data buses, a_dout and b_dout, two read address buses, a_addr and b_addr. one write data bus, wr_dbus and one write address bus, wr_addr. Each of these address buses is used to specify one of the 32 registers for either reading or writing. The write operation takes place on the rising edge of the clk signal when the wr_en signal is logic 1. The read operation, however, is not clocked - it is combinational. Thus, the value on the a_dout should always be the contents of the register specified by the a_addr bus.Similarly, the value on the b_dout should always be the contents of the register specified by the b_addr bus. So, with this register file, you can write to a register and read two registers simultaneously. It is also possible to read a single register on both of the read buses simultaneously. It essence it is a 3-port memory element that allows two reads and one write simultaneously.K KaziCSCI 641/EENG 641 *

    K KaziCSCI 641/EENG 641 *

  • MemoryK KaziCSCI 641/EENG 641 *

    K KaziCSCI 641/EENG 641 *

  • MemoryCompared to registerfile, memory is large and slowMIPS uses byte-addressable memoryMIPS architecture uses 32-bit memory address and 32-bit data wordsMemory array is word-addressable, i.e., each 32-bit data word has a unique 32-bit addressMIPS uses load word instruction, lw, to read data from memory into a registerlw instrcution specifies the effective address in memory as sum of base address and offset, e.g.lw $s0, 0($0) # read data word 0 into $s0lw $s1, 4($0) # read data word 1 into $s1lw $s2, 0xC($0) # read data word 3 into $s2K KaziCSCI 641/EENG 641 *offsetBase address

    K KaziCSCI 641/EENG 641 *

  • MemoryMIPS uses store word instruction, sw, to write data from a register to a memorysw instrcution specifies the effective address in memory as sum of base address and offset, e.g.sw $s0, 0($0) # write $s0 to memory data word 0 sw $s1, 4($0) # write $s1 to memory data word 1sw $s2, 0xC($0) # write $s2 to memory data word 3K KaziCSCI 641/EENG 641 *offsetBase address

    K KaziCSCI 641/EENG 641 *

  • Instruction set: each instruction in the instruction set describes one particular CPU operation. Each instruction is represented in both assembly language by the mnimonics and machine language (binary) by a word of 32 bits subdivided into several fields. rs is short for register source. rt comes after rs alphabetically and usually indicates second register source. rd is short for register destination.K KaziCSCI 641/EENG 641 *Instruction Set of MIPS Processorshamt shift and mix operationOp - Opcode

    K KaziCSCI 641/EENG 641 *

  • Instruction Set of MIPS Processor: R-type instructionArithmetic/Logical Instructions in MIPSLogical operations are and, or, xor, and norR-type instructions operate bit-by-bit on two source registers and the result is written to the destination addressand is used in masking bits (i.e. forcing unwanted bits to 0)or is useful in combing bits from two registersMIPS does not provide a NOT instruction, NOR can be used for NOT operation, e.g., A NOR $0 = not AK KaziCSCI 641/EENG 641 *

    K KaziCSCI 641/EENG 641 *

  • K KaziCSCI 641/EENG 641 *Instruction Set of MIPS Processor: Machine code for R-type instruction

    K KaziCSCI 641/EENG 641 *

  • Instruction Set of MIPS Processor: I-type instructionImmediate type or I-type instruction use two register operands and one immediate operand. Similar to R-type instructionOperation is solely defined by the opcoders and imm are always used as source operandsrt is used as a destination for some instructions, but never a source for othersK KaziCSCI 641/EENG 641 *

    K KaziCSCI 641/EENG 641 *

  • K KaziCSCI 641/EENG 641 *Instruction Set of MIPS Processor: Machine code for I-type instructions

    K KaziCSCI 641/EENG 641 *

  • Load word (lw) instructionMIPS uses load word instruction, lw, to read a data word from memory into a registerlw $s3 1($0)#read memory word 1 into $s3lw instruction specifies effective address in memory as sum of base address and an offset.Base address (written in parentheses in the instruction) is a registerOffset is constant (written before the parentheses)Base address is $0 and offset is 1 => instruction reads from memory address 1. After instruction register S3 = F2F1AC07

    K KaziCSCI 641/EENG 641 *

    Word addressDataWord0000000340F30788WORD 30000000201EE2842WORD 200000001F2F1AC07WORD 100000000ABCDEF78WORD 0

    K KaziCSCI 641/EENG 641 *

  • lw instructionK KaziCSCI 641/EENG 641 *rt is used as a destination in this instruction