CS42426 114 dB, 192 kHz 6-Ch Codec with PLLalsa- james/datasheets/ 2 table of contents 1 pin descriptions .....6 2 typical connection diagrams

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  • Advance Product Information This document conCirrus Logic reserv

    Copyrig(

    Cirrus Logic, Inc.www.cirrus.com

    CS42426

    114 dB, 192 kHz 6-Ch Codec with PLL

    Features

    Six 24-bit D/A, two 24-bit A/D converters114 dB DAC / 114 dB ADC dynamic range-100 dB THD+NSystem sampling rates up to 192 kHzIntegrated low-jitter PLL for increased systemjitter tolerancePLL clock or OMCK system clock selection7 configurable general purpose outputsADC high pass filter for DC offset calibrationExpandable ADC channels and one-linemode supportDigital output volume control with soft rampDigital +/-15 dB input gain adjust for ADCDifferential analog architectureSupports logic levels between 5 V and 1.8 V

    General DescriptionThe CS42426 CODEC provides two analog-to-digital and sixdigital-to-analog Delta-Sigma converters, as well as an inte-grated PLL, in a 64-pin LQFP package.

    The CS42426 integrated PLL provides a low-jitter systemclock. The internal stereo ADC is capable of independent chan-nel gain control for single-ended or differential analog inputs.All six channels of DAC provide digital volume control and dif-ferential analog outputs. The general purpose outputs may bedriven high or low, or mapped to a variety of DAC mute controlsor ADC overflow indicators.

    The CS42426 is ideal for audio systems requiring widedynamic range, negligible distortion and low noise, such as A/Vreceivers, DVD receivers, digital speaker and automotive audiosystems.

    ORDERING INFORMATIONCS42426-CQ* -10 to 70 C 64-pin LQFPCS42426-DQ* -40 to 85 C 64-pin LQFPCDB42428 Evaluation Board

    *Also available in Lead-Free package

    PLLInternal Voltage

    Reference

    RST

    GPO1

    AD0/CS

    SCL/CCLKSDA/CDOUTAD1/CDIN

    VLC

    AOUTA1+AOUTA1-

    AOUTB1+

    AOUTA3+AOUTA3-

    AOUTA2-

    AOUTB2-

    AOUTA2+

    AOUTB2+

    AOUTB1-

    AOUTB3+AOUTB3-

    AINL+AINL-

    AINR+AINR-

    FILT+REFGND VQ

    ADC#1

    ADC#2

    Digital Filter

    Digital Filter

    Gain & Clip

    Gain & Clip

    ADC_SDOUT

    ADCIN1ADCIN2

    DAC_SCLK

    DAC_LRCK

    DAC_SDIN3

    DAC_SDIN2

    DAC_SDIN1

    VLS

    ADC_LRCK

    DGND VDOMCK RMCK LPFLT

    INT

    ControlPort

    DAC#1

    DAC#2

    DAC#3

    DAC#4

    DAC#5

    DAC#6

    Dig

    italF

    ilter

    Vol

    ume

    Con

    trol

    GPO2GPO3GPO4GPO5GPO6GPO7

    MUTEC

    Mute

    Ana

    log

    Filt

    er

    VA AGND

    ADCSerialAudioPort

    Mult/DivGPO

    ADC_SCLKLeve

    lTra

    nsla

    tor

    Leve

    lTra

    nsla

    tor

    DA

    CS

    eria

    lAud

    ioP

    ort

    tains information for a new product.es the right to modify this product without notice.

    1

    ht Cirrus Logic, Inc. 2003All Rights Reserved)

    MAY 03DS604A1

  • CS42426

    TABLE OF CONTENTS1 PIN DESCRIPTIONS ................................................................................................................. 62 TYPICAL CONNECTION DIAGRAMS ..................................................................................... 83 APPLICATIONS ....................................................................................................................... 10

    3.1 Overview .......................................................................................................................... 103.2 Analog Inputs ................................................................................................................... 10

    3.2.1 Line Level Inputs ................................................................................................. 103.2.2 External Input Filter ............................................................................................. 113.2.3 High Pass Filter and DC Offset Calibration ......................................................... 11

    3.3 Analog Outputs ................................................................................................................ 113.3.1 Line Level Outputs and Filtering ......................................................................... 113.3.2 Interpolation Filter ............................................................................................... 123.3.3 Digital Volume and Mute Control ........................................................................ 123.3.4 ATAPI Specification ............................................................................................ 13

    3.4 Clock Generation ............................................................................................................. 143.4.1 PLL and Jitter Attenuation ................................................................................... 143.4.2 OMCK System Clock Mode ................................................................................ 153.4.3 Master Mode ....................................................................................................... 153.4.4 Slave Mode ......................................................................................................... 15

    3.5 Digital Interfaces .............................................................................................................. 163.5.1 Serial Audio Interface Signals ............................................................................. 163.5.2 Serial Audio Interface Formats ............................................................................ 183.5.3 ADCIN1/ADCIN2 Serial Data Format .................................................................. 213.5.4 One Line Mode(OLM) Configurations ................................................................. 22

    3.6 Control Port Description and Timing ................................................................................ 26

    IMPORTANT NOTICE

    "Advance" product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiar-ies ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change withoutnotice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant infor-mation to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and condi-tions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. Noresponsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items,or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grantsno license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrusowns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use withinyour organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copyingfor general distribution, advertising or promotional purposes, or for creating any work for resale.

    An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies describedin this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/orquota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this materialis subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC.

    CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, ORSEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHO-RIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THEBODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COM-PONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICA-TIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS,STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE,WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USESOR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFYCIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDINGATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES.

    Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to usethose components in a standard I2C system.

    Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document maybe trademarks or service marks of their respective owners.

    Contacting Cirrus Logic SupportFor all product questions and inquiries contact a Cirrus Logic Sales Representative.To find one nearest you go to www.cirrus.com/

    2

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  • CS42426

    3.6.1 SPI Mode .........................