Course Name: BCA / MCA

Subject Name:

Introduction To Microprocessor

Prepared by Assistant Professor’s Team

of

Microtek College of Management & Technology

Under Guidance of

Dr. Pankaj Rajhans

An Alumni of IIT-Delhi

President & Executive Director

Microtek College of Management & Technology

Jaunpur & Varanasi (U.P)

INTRODUCTION TO MICROPROCESSOR

Section I

Introduction to Microprocessor, its historical background and its applications.

INTEL 8085 Introduction, Microprocessor Architecture and its operations, 8085 MPU

and its architecture, 8085 instruction cycle ,8085 Instructions :Data Transfer instructions

Arithmetic instructions, logical instructions, Branch instructions ,RISC v/s CISC

processors.

Section II

INTEL 8086

Introduction, 8086Architecture, real and Protected mode memory Addressing, Memory

Paging Addressing Modes. Various types of instructions: Data movement, Arithmetic

and logic; and program control. Type of instructions, Pin diagram of 8086, clock

generator (8284A)

Section III

INTERRUPTS:

Introduction, 8257 Interrupt controller, basic DMA operation and 8237 DMA Controller,

Arithmetic coprocessor, 80X87 Architecture.

CREATED BY:-

KHUSHBU DOULANI

(IT FACULTY,MICROTEK)

SECTION-I

Introduction to Microprocessor, its historical background and its applications.

INTEL 8085 Introduction, Microprocessor Architecture and its operations, 8085 MPU

and its architecture,8085 instruction cycle ,8085 Instructions :Data Transfer instructions

Arithmetic instructions, logical instructions, Branch instructions ,RISC v/s CISC

processors.

MICROPROCESSOR

A microprocessor is a clock-driven semiconductor device consisting of electronic logic

circuits manufactured by using either a large-scale integration (LSI) or very-large-scale

integration (VLSI) technique. The microprocessor is capable of performing various

computing functions and making decisions to change the sequence of program execution.

In large computers, a CPU performs these computing functions. The Microprocessor

resembles a CPU exactly. The microprocessor is in many ways similar to the CPU, but

includes all the logic circuitry including the control unit, on one chip. The

microprocessor can be divided into three segments for the sake of clarity. – They are:

arithmetic/logic unit (ALU), register array, and control unit’s comparison between a

microprocessor and a computer is shown below:

Arithmetic/Logic Unit: This is the area of the microprocessor where various computing

functions are performed on data. The ALU unit performs such arithmetic operations as

addition and subtraction, and such logic operations as AND, OR, and exclusive OR.

Register Array: This area of the microprocessor consists of various registers identified

by letters such as B, C, D, E, H, and L. These registers are primarily used to store data

temporarily during the execution of a program and are accessible to the user through

instructions.

Control Unit: The control unit provides the necessary timing and control signals to all

the operations in the microcomputer. It controls the flow of data between the

microprocessor and memory and peripherals.

Memory: Memory stores such binary information as instructions and data, and provides that

information to the microprocessor whenever necessary. To execute programs, the microprocessor

reads instructions and data from memory and performs the computing operations in its ALU

section. Results are either transferred to the output section for display or stored in memory for

later use. Read-Only memory (ROM) and Read/Write memory (R/WM), popularly known as

Random- Access memory (RAM).

1. The ROM is used to store programs that do not need alterations. The monitor program

of a single-board microcomputer is generally stored in the ROM. This program interprets

the information entered through a keyboard and provides equivalent binary digits to the

microprocessor. Programs stored in the ROM can only be read; they cannot be altered.

2. The Read/Write memory (RIWM) is also known as user memory It is used to store

user programs and data. In single-board microcomputers, the monitor program monitors

the Hex keys and stores those instructions and data in the R/W memory. The information

stored in this memory can be easily read and altered.

I/O (Input/output): It communicates with the outside world. I/O includes two types of

devices: input and output; these I/O devices are also known as peripherals.

System Bus: The system bus is a communication path between the microprocessor and

peripherals: it is nothing but a group of wires to carry bits.

HISTORY

Name of the microprocessor Manufacture Distinction

4004 INTEL The first Microprocessor

(1971)

8008 INTEL First 8-bit Microprocessor

(1972)

8080A INTEL First n-channel, second

generation Microprocessor

(1974)

6800 MOTOROLA First+5V only

microprocessor (1974)

PACE National Semi-conductor First 16-bit conductor (1974

1802 RCA First MOS microprocessor

(1974)

8048 INTEL First 8-bit single-chip

microprocessor (1976)

8088 INTEL First 8-bit processor with

16-bit internal Architecture

2920 INTEL First analog single

processor (1979)

32032 NATIONAL 32-bit microprocessor

Microprocessor is a multi-use device which finds applications in almost all the fields.

Here is some sample applications given in variety of fields.

Electronics:

Digital clocks & Watches

Mobile phones

Measuring Meters

Mechanical:

Automobiles

Lathes

All remote machines

Electrical:

Motors

Lighting controls

Power stations

Medical:

Patient monitoring

Most of the Medical equipments

Data loggers

Computer:

All computer accessories

Laptops & Modems

Scanners & Printers

Domestic:

Microwave Ovens

Television/CD/DVD players

Washing Machines

ARCHITECHTURE

or

FUNCTIONAL BLOCK DIAGRAM OF 8085

The functional block diagram or architecture of 8085 Microprocessor is very

important as it gives the complete details about a Microprocessor. Fig. shows the

Block diagram of a Microprocessor.

ARCHITECTURE

8085 Bus Structure:

Address Bus:

1. The address bus is a group of 16 lines generally identified as A0 to A15.

2. The address bus is unidirectional: bits flow in one direction-from the MPU to

peripheral devices.

3. The MPU uses the address bus to perform the first function: identifying a peripheral or

a memory location.

Data Bus:

1. The data bus is a group of eight lines used for data flow.

2. These lines are bi-directional - data flow in both directions between the MPU and

memory and peripheral devices.

3. The MPU uses the data bus to perform the second function: transferring binary

information.

4. The eight data lines enable the MPU to manipulate 8-bit data ranging from 00 to FF

(28 = 256 numbers).

5. The largest number that can appear on the data bus is 11111111.

Control Bus:

1. The control bus carries synchronization signals and providing timing signals.

2. The MPU generates specific control signals for every operation it performs. These

signals are used to identify a device type with which the MPU wants to communicate.

Registers of 8085:

1. The 8085 have six general-purpose registers to store 8-bit data during program

execution.

2. These registers are identified as B, C, D, E, H, and L.

3. They can be combined as register pairs-BC, DE, and HL-to perform some 16-bit

operations.

Accumulator (A):

1. The accumulator is an 8-bit register that is part of the arithmetic/logic unit (ALU).

2. This register is used to store 8-bit data and to perform arithmetic and logical

operations.

3. The result of an operation is stored in the accumulator.

Flags:

1. The ALU includes five flip-flops that are set or reset according to the result of an operation.

2. The microprocessor uses the flags for testing the data conditions.

3. They are Zero (Z), Carry (CY), Sign (S), Parity (P), and Auxiliary Carry (AC) flags. The most

commonly used flags are Sign, Zero, and Carry.

4. The bit position for the flags in flag register is,

1. Sign Flag (S):

After execution of any arithmetic and logical operation, if D7 of the result is 1, the

sign flag is set. Otherwise it is reset. D7 is reserved for indicating the sign; the remaining

is the magnitude of number. If D7 is 1, the number will be viewed as negative number. If

D7 is 0, the number will be viewed as positive number.

2.Zero Flag (z):

If the result of arithmetic and logical operation is zero, then zero flag is set otherwise

it is reset.

3. Auxiliary Carry Flag (AC):

If D3 generates any carry when doing any arithmetic and logical operation, this flag

is set. Otherwise it is reset.

4 .Parity Flag (P):

If the result of arithmetic and logical operation contains even number of 1's then this

flag will be set and if it is odd number of 1's it will be reset.

5. Carry Flag (CY):

If any arithmetic and logical operation result any carry then carry flag is set

otherwise it is reset.

Arithmetic and Logic Unit (ALU):

1. It is used to perform the arithmetic operations like addition, subtraction,

multiplication, division, increment and decrement and logical operations like AND,

OR and EX-OR.

2. It receives the data from accumulator and registers.

3. According to the result it set or reset the flags.

4. Program Counter (PC):

5. This 16-bit register sequencing the execution of instructions.

6. It is a memory pointer. Memory locations have 16-bit addresses, and that is why this

is a 16-bit register.

7. The function of the program counter is to point to the memory address of the next

instruction to be executed.

8. When an opcode is being fetched, the program counter is incremented by one to point

to the next memory location.

Stack Pointer (SP):

1. The stack pointer is also a 16-bit register used as a memory pointer.

2. It points to a memory location in R/W memory, called the stack.

3. The beginning of the stack is defined by loading a 16-bit address in the stack pointer

(register).

Temporary Register:

It is used to hold the data during the arithmetic and logical operations.

Instruction Register:

When an instruction is fetched from the memory, it is loaded in the instruction

register.

Instruction Decoder:

It gets the instruction from the instruction register and decodes the instruction. It

identifies the instruction to be performed.

Serial I/O Control:

It has two control signals named SID and SOD for serial data transmission.

Timing and Control unit:

1. It has three control signals ALE, RD (Active low) and WR (Active low) and three

status signals IO/M (Active low), S0 and S1.

2. ALE is used for provide control signal to synchronize the components of

microprocessor and timing for instruction to perform the operation.

3. RD (Active low) and WR (Active low) are used to indicate whether the operation is

reading the data from memory or writing the data into memory respectively.

4. IO/M (Active low) is used to indicate whether the operation is belongs to the memory

or peripherals.

5. PIN DIAGRAM

1. The microprocessor is a clock-driven semiconductor device consisting of electronic

logic circuits manufactured by using either a large-scale integration (LSI) or very-

large-scale integration (VLSI) technique.

2. The microprocessor is capable of performing various computing functions and

making decisions to change the sequence of program execution.

3. In large computers, a CPU implemented on one or more circuit boards performs these

computing functions.

4. The microprocessor is in many ways similar to the CPU, but includes the logic

circuitry, including the control unit, on one chip.

5. The microprocessor can be divided into three segments for the sake clarity,

arithmetic/logic unit (ALU), register array, and control unit.

6. 8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as

follows

1. Power supply and clock signals

2. Address bus

3. Data bus

4. Control and status signals

5. Interrupts and externally initiated signals

6. Serial I/O ports

. Power supply and Clock frequency signals:

1. Vcc + 5 volt power supply

2. Vss Ground

3. X1, X2: Crystal or R/C network or LC network connections to set the frequency of

internal clock generator.

4. The frequency is internally divided by two. Since the basic operating timing

frequency is 3 MHz, a 6 MHz crystal is connected externally.

5. CLK (output)-Clock Output is used as the system clock for peripheral and devices

interfaced with the microprocessor.

PIN DIAGRAM AND PIN DESCRIPTION OF 8085

1. Power supply and Clock frequency signals:

1 .Vcc + 5 volt power supply

2. Vss Ground

3. X1, X2: Crystal or R/C network or LC network connections to set the frequency of

internal clock generator.

4. The frequency is internally divided by two. Since the basic operating timing

frequency is 3 MHz, a 6 MHz crystal is connected externally.

5. CLK (output)-Clock Output is used as the system clock for peripheral and devices

interfaced with the microprocessor.

6. 8085 is a 40 pin IC, DIP package. The signals from the pins can be grouped as

follows

1. Power supply and clock signals

2. Address bus

3. Data bus

4. Control and status signals

5. Interrupts and externally initiated signals

6. Serial I/O ports

Fig (a) - Pin Diagram of 8085 & Fig (b) - logical schematic of Pin diagram

.

2. Address Bus:

1. A8 - A15 (output; 3-state)

2. It carries the most significant 8 bits of the memory address or the 8 bits of the I/O

address;

3. Multiplexed Address / Data Bus:

1. AD0 - AD7 (input/output; 3-state)

2. These multiplexed set of lines used to carry the lower order 8 bit address as well as

data bus.

3. During the opcode fetch operation, in the first clock cycle, the lines deliver the lower

order address A0 - A7.

4. In the subsequent IO / memory, read / write clock cycle the lines are used as data bus.

5. The CPU may read or write out data through these lines.

4. Control and Status signals:

1. ALE (output) - Address Latch Enable.

2. This signal helps to capture the lower order address presented on the multiplexed

address / data bus.

3. RD (output 3-state, active low) - Read memory or IO device.

4. This indicates that the selected memory location or I/O device is to be read and that

the data bus is ready for accepting data from the memory or I/O device.

5. WR (output 3-state, active low) - Write memory or IO device.

6. This indicates that the data on the data bus is to be written into the selected memory

location or I/O device.

7. IO/M (output) - Select memory or an IO device.

8. This status signal indicates that the read / write operation relates to whether the

memory or I/O device.

9. It goes high to indicate an I/O operation.

10. It goes low for memory operations.

5. Status Signals:

It is used to know the type of current operation of the microprocessor.

TIMING DIAGRAM

Timing Diagram is a graphical representation. It represents the execution time taken

by each instruction in a graphical format. The execution time is represented in T-states.

Instruction Cycle:

The time required to execute an instruction is called instruction cycle.

Machine Cycle:

The time required to access the memory or input/output devices is called machine

cycle.

T-State:

The machine cycle and instruction cycle takes multiple clock periods. A portion of

an operation carried out in one system clock period is called as T-state.

INTRODUCTION

Timing diagram is the display of initiation of read/write and transfer of data operations

under the control of 3-status signals IO / M , S1, and S0. As the heartbeat is required for

the survival of the human being, the CLK is required for the proper operation of

different sections of the microprocessors. All actions in the microprocessor is controlled

by either leading or trailing edge of the clock. If I ask a man to bring 6-bags of wheat, each

weighing 100 kg, he may take 6-times to perform this task in going and bringing it. A

stronger man might perform the same task in 3-times only. Thus, it depends on the

strength of the man to finish the job quickly or slowly. Here, we can assume both weaker

and strong men as machine. The weaker man has taken 6-machine cycle (6-times going

and coming with one bag each time) to execute the job where as the stronger man has

taken only 3-machine cycle for the same job. Similarly, a machine may execute one

instruction in as many as 3-machine cycles while the other machine can take only one

machine cycle to execute the same instruction. Thus, the machine that has taken only one

machine cycle is efficient than the one taking 3-machine cycle. Each machine cycle is

composed of many clock cycle. Since, the data and instructions, both are stored in the

memory, the µP performs fetch operation to read the instruction or data and then execute

the instruction. The µP in doing so may take several cycles to perform fetch and execute

operation. The 3-status signals : IO / M , S1, and S0 are generated at the beginning of each

machine cycle. The unique combination of these 3-status signals identify read or write

operation and remain valid for the duration of the cycle. Table-5.1(a) shows details of the

unique combination of these status signals to identify different machine cycles.

Thus, time taken by any µP to execute one instruction is calculated in terms of the clock

period.

The execution of instruction always requires read and writes operations to transfer

data to or from the µP and memory or I/O devices. Each read/ write operation constitutes

one machine cycle (MC1) as indicated in Fig. 5.1 (a). Each machine cycle consists of

many clock periods/ cycles, called T-states. The heartbeat of the microprocessor is the

clock period. Each and every operation inside the microprocessor is under the control

of the clock cycle. The clock signal determines the time taken by the microprocessor

to execute any instruction. The clock cycle shown in Fig. 5.1 (a) has two edges (leading

and trailing or lagging). State is defined as the time interval between 2-trailing or leading

edges of the clock. Machine cycle is the time required to transfer data to or from memory

or I/O devices.

MICROPROCESSORS, INTERFACINGS AND APPLICATIONS

Table 5.1(a) Machine cycle status and control signals

Status Controls

Machine cycle IO / M S1 S0 RD WR INTA

Opcode Fetch (OF) 0 1 1 0 1 1

Memory Read 0 1 0 0 1 1

Memory Write 0 0 1 1 0 1

I/O Read (I/OR) 1 1 0 0 1 1

I/O Write (I/OW) 1 0 1 1 0 1

Acknowledge of INTR (INTA) 1 1 1 1 1 0

BUS Idle (BI) : DAD 0 1 0 1 1 1

ACK of RST, TRAP 1 1 1 1 1 1

HALT Z 0 0 Z Z 1

HOLD Z X X Z Z 1

X ⇒ Unspecified, and Z ⇒ High impedance state

PROCESSOR CYCLE

a) Machine cycle showing clock periods

PROCESSOR CYCLE

The function of the microprocessor is divided into fetch and execute cycle of any instruction of a program. The program is nothing but number of instructions stored in the memory in se- quence. In the normal process of operation, the microprocessor fetches (receives or reads) and executes one instruction at a time in the sequence until it executes the halt (HLT) instruction. Thus, an instruction cycle is defined as the time required to fetch and execute an instruction. For executing any program, basically 2-steps are followed sequentially with the help of clocks

• Fetch, and • Execute.

The time taken by the µP in performing the fetch and execute operations are called fetch and execute cycle. Thus, sum of the fetch and execute cycle is called the instruction cycle as indicated in Fig. 5.2 (a).

Instruction Cycle (IC) = Fetch cycle (FC) + Execute Cycle (EC)

Fig. 5.2 (a) Processor cycle

TIMING DIAGRAM OF 8085 179

These cycles have been illustrated in Figs. 5.2(a) and (b). Each read or writes operation constitutes a machine cycle. The instructions of 8085 require 1-5 machine cycles containing 3-6 states (clocks). The 1st machine cycle of any instruction is always an Op. Code fetch cycle in which the processor decides the nature of instruction. It is of at least 4-states. It may go up to 6-states.

Fig. 5.2 (b) Ideal wave shape relationship for FC, EC, MC, and IC.

It is well known that an instruction cycle consists of many machine cycles. Each machine cycle consists of many clock periods or cycles, called T-states. The 1st machine cycle (M1) of every instruction cycle is the opcode fetch cycle. In the opcode fetch cycle, the processor comes to know the nature of the instruction to be executed. The processor during (M1 cycle) puts the program counter contents on the address bus and reads the opcode of the instruction through read process. The T1, T2, and T3 clock cycles are used for the basic memory read operation and the T4 clock and beyond are used for its interpretation of the opcode. Based on these interpretations, the µP comes to know the type of additional information/data needed for the execution of the instruction and accordingly proceeds further for 1 or 2-machine cycle of memory read and writes.

The Op. code fetch cycle is of fixed duration (normally 4-states), whereas the instruction cycle is of variable duration depending on the length of the instruction. As an example, STA instruction, requires opcode fetch cycle, lower-order address fetch cycle and higher order fetch cycle and then the execute cycle. Thus opcode fetch cycle is of one machine cycle in this example. A particular microprocessor requires a definite time to performing a specific task. This time is called machine cycle. Thus, one machine cycle is required each time the µP access I/O port or memory. A fetch opcode cycle is always 1-machine cycle, whereas, execute cycle may be of one or more machine cycle depending upon the length of the instruction.

Instruction Fetch (FC) ⇒ An instruction of 1 or 2 or 3-bytes is extracted from the memory locations during the fetch and stored in the µP’s instruction register.

Instruction Execute (EC) ⇒ The instruction is decoded and translated into specific activities during the execution phase. Thus, in an instruction cycle, instruction fetch, and instruction execute cycles are related as depicted in Fig. 5.2 (a). Every instruction cycle consists of 1, 2, 3, 4 or 5-machine cycles as indicated in Fig. 5.2 (c). One machine cycle is required each time the µP access memory or I/O port. The fetch cycle, in general could be 4 to 6-states whereas the execute cycle could of 3 to 6-states. The 1st machine cycle of any instruction is always the fetch cycle that provides identification of the instruction to be executed.

The fetch portion of an instruction cycle requires one machine cycle for each byte of instruction to be fetched. Since instruction is of 1 to 3 bytes long, the instruction fetch is one to 3-machine cycles in duration. The 1st machine cycle in an instruction cycle is always an opcode

MICROPROCESSORS, INTERFACINGS AND APPLICATIONS

fetch. The 8-bits obtained during an opcode fetch are always interpreted as the Opcode of an instruction. The machine cycle including wait states is shown in Fig. 5.2 (c).

Fig. 5.2 (c) Machine cycle including wait states

Note : Some instructions do not require any machine cycle other than that necessary to fetch the instruction. Other instructions, however, require additional machine cycles to write or read data to or from memory or I/O devices.

A typical fetch cycle is explained in Fig. 5.2 (d). In Fig. 5.2 (d) only two clock cycles have been shown as the requirement to read the instruction. Since the access time of the memory may vary and it may require more than 2-clock cycles, the microprocessor has to wait for more than 2-clocks duration before it receives the opcode instruction. Hence, most of the microprocessors have the provisions of introducing wait cycle within the fetch cycle to cope up with the slow memories or I/O devices.

Fig. 5.2 (d) Fetch cycle

Opcode Fetch

A microprocessor either reads or writes to the memory or I/O devices. The time taken to read or write for any instruction must be known in terms of the µP clock. The 1st step in communicating between the microprocessor and memory is reading from the memory. This read- ing process is called opcode fetch. The process of opcode fetch operation requires

minimum 4- clock cycles T1, T2, T3, and T4 and is the 1st machine cycle (M1) of every instruction.

In order to differentiate between the data byte pertaining to an opcode or an

address, the

machine cycle takes help of the status signal IO / M , S1, and S0. The IO / M = 0

indicates

memory operation and S1 = S0 = 1 indicates Opcode fetch operation.

The opcode fetch machine cycle M1 consists of 4-states (T1, T2, T3, and T4). The 1st 3- states are used for fetching (transferring) the byte from the memory and the 4th-state is used to decode it.

Thus, thorough understanding about the communication between memory and microprocessor can be achieved only after knowing the processes involved in reading or writing into the memory by the microprocessor and time taken w.r.t. its clock period. This can be explained by examples.

TIMING DIAGRAM OF 8085

The process of implementation of each instruction follows the fetch and execute cycles. In other words, first the instruction is fetched from memory and then executed. Figs. 5.2 (e) and (f) depict these 2-steps for implementation of the instruction ADI 05H. Let us assume that the accumulator contains the result of previous operation i.e., 03H and instruction is held at memory locations 2030H and 2031H.

The fetch part of the instruction is the same for every instruction. The control unit puts the contents of the program counter (PC) 2030H on the address bus. The 1st byte (opcode C6H in this example) is passed to the instruction register. In the execute cycle of the instruction, the control unit examines the opcode and as per interpretation further memory read or write operations are per- formed depending upon whether additional information/ data are required or not. In this case, the data 05H from the memory is transferred through the data bus to the ALU. At the same time the control unit sends the contents of the accumulator (03H) to the ALU and performs the addition operation. The result of the addition operation 08H is passed to the accumulator overriding the previous contents 03H. On the completion of one instruction, the program counter is automatically incremented to point to the next memory location to execute the subsequent instruction.

MICROPROCESSORS, INTERFACINGS AND APPLICATIONS

Note : The slope of the edges of the clock pulses has been shown to be much exaggerated to indicate the existence of rise and fall time.

5.3 TIMING DIAGRAM OF OPCODE FETCH

The process of opcode fetch operation requires minimum 4-clock cycles T1, T2, T3, and T4 and is the 1st machine cycle (M1) of every instruction.

Example

Fetch a byte 41H stored at memory location 2105H.

For fetching a byte, the microprocessor must find out the memory location where it is stored. Then provide condition (control) for data flow from memory to the microprocessor. The process of data flow and timing diagram of fetch operation are shown in Figs. 5.3 (a), (b), and (c). The µP fetches opcode of the instruction from the memory as per the sequence below

• A low IO / M means microprocessor wants to communicate with memory. • The µP sends a high on status signal S1 and S0 indicating fetch operation.

• The µP sends 16-bit address. AD bus has address in 1st clock of the 1st machine

cycle,

T1 .

• AD7 to AD0 address is latched in the external latch when ALE = 1.

• AD bus now can carry data. • In T2, the RD control signal becomes low to enable the memory for read operation.

• The memory places opcode on the AD bus

• The data is placed in the data register (DR) and then it is transferred to IR.

Fig. 5.3 (a) Opcode fetch

TIMING DIAGRAM OF 8085 183

• During T3 the RD signal becomes high and memory is disabled.

• During T 4 the opcode is sent for decoding and decoded in T4.

• The execution is also completed in T4 if the instruction is single byte.

• More machine cycles are essential for 2- or 3-byte instructions. The 1st machine cycle M1 is meant for fetching the opcode. The machine cycles M2 and M3 are required either to read/ write data or address from the memory or I/O devices.

Example

Opcode fetch MOV B,C.

T1 : The 1st clock of 1st machine cycle (M1) makes ALE high indicating address latch enabled which loads low-order address 00H on AD7 ⇔ AD0 and high-order address 10H simultaneously on A15 ⇔ A8. The address 00H is latched in T1.

T2 : During T2 clock, the microprocessor issues RD control signal to enable the memory and memory places 41H from 1000H location on the data bus.

Fig. 5.3 (b) Data flow from memory to microprocessor

T3 : During T3, the 41H is placed in the instruction register and RD = 1 (high) disables signal. It means the memory is disabled in T3 clock cycle. The opcode cycle is completed by end of T3 clock cycle.

T4 : The opcode is decoded in T4 clock and the action as per 41H is taken accordingly. In other word, the content of C-register is copied in B-register. Execution time for opcode 41H is

Clock frequency of 8085 = 3.125 MHz

Time (T) for one clock = 1/3.125 MHz = 325.5 ns = 0.32 µS

Execution time for opcode fetch = 4T = 4*0.32 µS = 1.28 µS

Explain the execution of MVI B,05H stored at locations indicated below

MICROPROCESSORS, INTERFACINGS AND APPLICATIONS

Fig. 5.3 (c) Opcode fetch (MOV B,C)

Fig. 5.3 (d) Timing diagram for MVI B,05H

The MVI B,05H instruction requires 2-machine cycles (M1 and M2). M1 requires 4-

states and M2 requires 3-states, total of 7-states as shown in Fig. 5.3 (d). Status signals IO /

M , S1 and S0 specifies the 1st machine cycle as the op-code fetch.

In T1-state, the high order address {10H} is placed on the bus A15 ⇔ A8 and low-order

address {00H} on the bus AD7 ⇔ AD0 and ALE = 1. In T 2 -state, the RD line goes low, and

the data 06H from memory location 1000H are placed on the data bus. The fetch cycle becomes complete in T3-state. The instruction is decoded in the T4-state. During T4-state, the contents of

the bus are unknown. With the change in the status signal, IO / M = 0, S1 = 1 and S0 = 0, the 2nd machine cycle is identified as the memory read. The address is 1001H and the data byte

TIMING DIAGRAM OF 8085 185

[05H] is fetched via the data bus. Both M1 and M2 perform memory read operation, but the M1

is called op-code fetch i.e., the 1st machine cycle of each instruction is identified as the opcode fetch cycle. Execution time for MBI B,05H i.e., memory read machine cycle and instruction cycle is

Mnemonic Instruction Byte

MVI B,05H Opcode

Immediate Data

Clock frequency of 8085 = 3.125 MHz

Machine Cycle T-sstates

Opcode Fetch 4

Read Immediate Data 3

7

Time ( T ) for one clock = 1/3.125 MHz = 0.32 µS

Time for Memory Read = 3T = 3*0.320 µS = 0.96 µS

Total Execution time for Instruction = 7T = 7*0.320 µS = 2.24 µS

Read Cycle

The high order address (A15 ⇔ A8) and low order address (AD7 ⇔ AD0) are

asserted on

1st low going transition of the clock pulse. The timing diagram for IO/M read are shown

in Fig.

5.3 (e) and ( f ). The A15 ⇔ A8 remains valid in T1, T2, and T3 i.e. duration of the bus cycle, but AD7 ⇔ AD0 remains valid only in T1. Since it has to remain valid for the whole bus cycle, it must be saved for its use in the T2 and T3.

Fig. 5.3 (e) Memory read timing diagram

ALE is asserted at the beginning of T1 of each bus cycle and is negated towards the end of T1. ALE is active during T1 only and is used as the clock pulse to latch the address (AD7 ⇔ AD0) during T1. The RD is asserted near the beginning of T2. It ends at the end of T3. As soon

as the RD becomes active, it forces the memory or I/O port to assert data. RD becomes inactive towards the end of T3, causing the port or memory to terminate the data.

186 MICROPROCESSORS, INTERFACINGS AND APPLICATIONS

Fig. 5.4 (f) I/O Read timing diagram

Write Cycle

Immediately after the termination of the low order address, at the beginning of the T2,

data

is asserted on the address/data bus by the processor. WR control is activated near the

start of

T2 and becomes inactive at the end of T3. The processor maintains valid data until after

WR is

terminated. This ensures that the memory or port has valid data while WR is active.

It is clear from Figs. 5.3 (g) and (h) that for READ bus cycle, the data appears on the

bus as a result of activating RD and for the WR bus cycle, the time the valid data is on

the bus overlaps the time that the WR is active.

Fig. 5.3 (g) Memory write timing diagram.

TIMING DIAGRAM OF 8085

Fig. 5.3 (h) I/O write timing diagram

STA

The STA instruction stands for storing the contents of the accumulator to a memory location whose address is immediately available after the instruction (STA). The 8085 have 16-address lines, it can address 2

16 = 64 K. Since the STA instruction is meant to store the

contents of the accumulator to the memory location, it is a 3-byte instruction. 1st byte is the opcode, the 2nd and 3rd bytes are the address of the memory locations. The storing of the STA instruction in the memory locations is as

Opcode 1st byte

Low address 2nd byte

High address 3rd byte

Three machine cycles are required to fetch this instruction : opcode Fetch transfers the opcode from the memory to the instruction register. The 2-byte address is then transferred, 1-byte at a time, from the memory to the temporary register. This requires two Memory read machine cycles. When the entire instruction is in the microprocessor, it is executed. The execution process transfers data from the microprocessor to the memory. The contents of the accumulator are transferred to memory, whose address was previously transferred to the microprocessor by the preceding 2-Memory Read machine cycles. The address of the memory location to be written is generated as

Mnemonic Instruction Byte Machine Cycle T-states

Opcode Opcode Fetch 4

LOW Address Memory Read 3

STA HIGH Address Memory Read 3

Memory Write 3

13

The high order address byte in the temporary register is transferred to the address latch and the low order address byte is transferred to the address/data latch. This data transfer is affected

MICROPROCESSORS, INTERFACINGS AND APPLICATIONS

by a Memory Write machine cycle. Thus 3-byte STA instruction has four machine cycles in its instruction cycle.

The timing and control section of the microprocessor automatically generates the proper machine cycles required for an instruction cycle from the information provided by the opcode. The

timing diagram of the instruction STA is shown in Fig. 5.3 (i). The status of IO / M , S1 and S 0

for 4-machine cycles are obtained from Table 5.1. The condition of IO / M , S1 and S0 would be 0, 1 and 1 respectively in MC1. The status of ALE is high at the beginning of 1st state of each machine cycle so that AD7 ⇔ AD0 work as the address bus. RD remains high during 1st state of each machine cycle, since during 1st state of each machine cycle AD7 ⇔ AD0 work as address bus. It remains high during 4th state of the 1st machine cycle also as the 4th state is used to decode the op code for generating the required control signals.

Fig. 5.3 (i) STA timing diagram

The opcode fetch of STA instruction has 4-states (clock cycles). Three states have been used to read the opcode from the main memory and the 4th to decode it and set up the subsequent machine cycle.

The action of memory read or write cycles containing 3-states i.e., T1, T2, and T3

are explained as

TIMING DIAGRAM OF 8085

T1 : During this period the address and control signals for the memory access are set

up.

T2 : The µP checks up the READY and HOLD control lines. If READY = 0, indicating

a

slow memory device, the µP enters in the wait state until READY = 1, indicating DMA

request,

then only the µP floats the data transfer lines and enters into wait until HOLD = 0.

T3 : In memory read cycles the µP transfers a byte from the data bus to an internal register and in memory write cycle the µP transfers a byte from an internal register to the data bus.

Thus STA instruction requires 4-machine cycles containing 13-states (clock cycles). With a typical clock of 3 MHz (= 330 ns), the STA instruction requires 13*330 ns = 4.29 ms for its execution.

The 8085 Addressing Modes The instructions MOV B, A or MVI A, 82H are to copy data from a source into a

destination. In these instructions the source can be a register, an input port, or an 8-bit

number (00H to FFH). Similarly, a destination can be a register or an output port. The

sources and destination are operands. The various formats for specifying operands are

called the ADDRESSING MODES. For 8085, they are:

1. Immediate addressing.

2. Register addressing.

3. Direct addressing. 4. Indirect addressing.

Immediate addressing

Data is present in the instruction. Load the immediate data to the destination provided.

Example: MVI R,data

Register addressing

Data is provided through the registers.

Example: MOV Rd, Rs

Direct addressing

Used to accept data from outside devices to store in the accumulator or send the data

stored in the accumulator to the outside device. Accept the data from the port 00H and

store them into the accumulator or Send the data from the accumulator to the port

01H. Example: IN 00H or OUT 01H

Indirect Addressing This means that the Effective Address is calculated by the processor. And the

contents of the address (and the one following) is used to form a second address. The

second address is where the data is stored. Note that this requires several memory

accesses; two accesses to retrieve the 16-bit address and a further access (or accesses) to

retrieve the data which is to be loaded into the register.

7. Instruction Set Classification

An instruction is a binary pattern designed inside a microprocessor to perform a

specific function. The entire group of instructions, called the instruction set, determines what functions the microprocessor can perform. These instructions can be

classified into the following five functional categories: data transfer (copy)

operations, arithmetic operations, logical operations, branching operations, and

machine-control operations.

Data Transfer (Copy) Operations

This group of instructions copy data from a location called a source to another

location called a destination, without modifying the contents of the source. In

technical manuals, the term data transfer is used for this copying function. However,

the term transfer is misleading; it creates the impression that the contents of the

source are destroyed when, in fact, the contents are retained without any modification.

The various types of data transfer (copy) are listed below together with examples of

each type:

Types Examples

1. Between Registers. 1. Copy the contents of the register B into

register D.

2. Specific data byte to a register or a 2. Load register B with the data byte 32H.

memory location.

3. Between a memory location and a 3. From a memory location 2000H to register

register. B.

4. Between an I/O device and the 4.From an input keyboard to the

accumulator. accumulator.

Arithmetic Operations These instructions perform arithmetic operations such as addition, subtraction, increment, and decrement.

Addition - Any 8-bit number, or the contents of a register or the contents of a

memory location can be added to the contents of the accumulator and the sum is

stored in the accumulator. No two other 8-bit registers can be added directly (e.g., the

contents of register B cannot be added directly to the contents of the register C). The

instruction DAD is an exception; it adds 16-bit data directly in register pairs.

Subtraction - Any 8-bit number, or the contents of a register, or the contents of a

memory location can be subtracted from the contents of the accumulator and the

results stored in the accumulator. The subtraction is performed in 2's compliment, and the

results if negative, are expressed in 2's complement. No two other registers can be

subtracted directly.

Increment/Decrement - The 8-bit contents of a register or a memory location can be

incremented or decrement by 1. Similarly, the 16-bit contents of a register pair (such as

BC) can be incremented or decrement by 1. These increment and decrement

operations differ from addition and subtraction in an important way; i.e., they can be

performed in any one of the registers or in a memory location.

Logical Operations

These instructions perform various logical operations with the contents of the

accumulator.

AND, OR Exclusive-OR - Any 8-bit number, or the contents of a register, or of a memory location can be logically ANDed, Ored, or Exclusive-ORed with the contents of the accumulator. The results are stored in the accumulator.

Rotate- Each bit in the accumulator can be shifted either left or right to the next

position.

Compare- Any 8-bit number, or the contents of a register, or a memory location can be

compared for equality, greater than, or less than, with the contents of the

accumulator.

Complement - The contents of the accumulator can be complemented. All 0s are

replaced by 1s and all 1s are replaced by 0s.

Branching Operations

This group of instructions alters the sequence of program execution either

conditionally or unconditionally.

Jump - Conditional jumps are an important aspect of the decision-making process in the programming. These instructions test for a certain conditions (e.g., Zero or Carry flag)

and alter the program sequence when the condition is met. In addition, the instruction set includes an instruction called unconditional jump.

Call, Return, and Restart - These instructions change the sequence of a program either by calling a subroutine or returning from a subroutine. The conditional Call and Return instructions also can test condition flags.

Machine Control Operations

These instructions control machine functions such as Halt, Interrupt, or do nothing.

The microprocessor operations related to data manipulation can be summarized in four

functions:

1. copying data

2. performing arithmetic operations

3. performing logical operations 4. testing for a given condition and alerting the program sequence

Some important aspects of the instruction set are noted below:

1. In data transfer, the contents of the source are not destroyed; only the contents of the destination are changed. The data copy instructions do not affect the flags.

2. Arithmetic and Logical operations are performed with the contents of the

accumulator, and the results are stored in the accumulator (with some

expectations). The flags are affected according to the results.

3. Any register including the memory can be used for increment and decrement.

4. A program sequence can be changed either conditionally or by testing for a given

data condition.

8. Instruction Format

An instruction is a command to the microprocessor to perform a given task on a

specified data. Each instruction has two parts: one is task to be performed, called the

operation code (opcode), and the second is the data to be operated on, called the

operand. The operand (or data) can be specified in various ways. It may include 8-bit

(or 16-bit ) data, an internal register, a memory location, or 8-bit (or 16-bit) address. In

some instructions, the operand is implicit.

Instruction word size

The 8085 instruction set is classified into the following three groups according to

word size:

1. One-word or 1-byte instructions

2. Two-word or 2-byte instructions 3. Three-word or 3-byte instructions

In the 8085, "byte" and "word" are synonymous because it is an 8-bit microprocessor.

However, instructions are commonly referred to in terms of bytes rather than words.

One-Byte Instructions A 1-byte instruction includes the opcode and operand in the same byte. Operand(s) are

internal register and are coded into the instruction.

For example:

Task

Copy the contents of the accumulator in

the register C.

Add the contents of register B to the

contents of the accumulator.

Invert (compliment) each bit in the

accumulator.

Op Operand Binary Hex code Code Code

MOV C,A 0100 1111 4FH

ADD B 1000 0000 80H

CMA 0010 1111 2FH

These instructions are 1-byte instructions performing three different tasks. In the first

instruction, both operand registers are specified. In the second instruction, the operand

B is specified and the accumulator is assumed. Similarly, in the third instruction, the accumulator is assumed to be the implicit operand. These instructions are stored in 8- bit binary format in memory; each requires one memory location.

MOV rd, rs

rd <-- rs copies contents of rs into rd.

Coded as 01 ddd sss where ddd is a code for one of the 7 general registers which is the

destination of the data, sss is the code of the source register.

Example: MOV A,B

Coded as 01111000 = 78H = 170 octal (octal was used extensively in instruction

design of such processors).

ADD r A <-- A + r

Two-Byte Instructions

In a two-byte instruction, the first byte specifies the operation code and the second byte specifies the operand. Source operand is a data byte immediately following the opcode. For example:

Task

Load an 8-bit data

Opcode Operand Binary Code

MVI A, Data

Hex Code

3E First Byte

byte in the

accumulator.

0011 1110

Data Second Byte

DATA

Assume that the data byte is 32H. The assembly language instruction is written as

Mnemonics Hex code

MVI A, 32H 3E 32H

The instruction would require two memory locations to store in memory.

MVI r,data

r <-- data

Example: MVI A,30H coded as 3EH 30H as two contiguous bytes. This is an example of immediate addressing.

ADI data

A <-- A + data

OUT port

where port is an 8-bit device address. (Port) <-- A. Since the byte is not the data but points directly to where it is located this is called direct addressing.

Three-Byte Instructions In a three-byte instruction, the first byte specifies the opcode, and the following two bytes specify the 16-bit address. Note that the second byte is the low-order address and the third byte is the high-order address.

opcode + data byte + data byte

For example:

Task Opcode Operand

Transfer the JMP 2085H

program

sequence to

Binary code Hex Code

C3 First byte 1100 0011

85 Second Byte

the memory

location

2085H.

1000 0101

0010 0000 20 Third Byte

This instruction would require three memory locations to store in memory.

Three byte instructions - opcode + data byte + data byte

LXI rp, data16

rp is one of the pairs of registers BC, DE, HL used as 16-bit registers. The two data

bytes are 16-bit data in L H order of significance.

rp <-- data16

Example:

LXI H,0520H coded as 21H 20H 50H in three bytes. This is also immediate

addressing.

LDA addr

A <-- (addr) Addr is a 16-bit address in L H order. Example: LDA 2134H coded as

3AH 34H 21H. This is also an example of direct addressing.

RISC VERSUS CISC PROCESSOR

RISC and CISC are computing systems developed for computers. Difference between RISC and CISC is critical to

understanding how a computer follows your instructions. These are commonly misunderstood terms and this article intends

to clarify their meanings and concepts behind the two acronyms.

RISC

Pronounced same as RISK, it is an acronym for Reduced Instruction Set Computer. It is a type of microprocessor that has

been designed to carry out few instructions at the same time. Till 1980’s hardware manufacturers were trying to build

CPU’s that could carry out a large number of instructions at the same instant. But the trend was reversed and manufacturers

decided to build computers that were capable of carrying out relatively very few instructions. Instructions being simple and

few, CPU’s could execute them quickly. Another advantage of RISC is the use of fewer transistors making them

inexpensive to produce.

Features of RISC

- Demands less decoding

- Uniform instruction set

- Identical general purpose registers used in any context

- Simple addressing modes

- Fewer data types in hardware

CISC

CISC stands for Complex Instruction Set Computer. It is actually a CPU which is capable of executing many operations

through a single instruction. These basic operations could be loading from memory, carrying out a mathematical operation

etc.

Features of CISC

- Complex instructions

- More number of addressing modes

- Highly pipelined

- More data types in hardware

Over the period of time, the terms RISC and CISC have almost become meaningless as both RISC and CISC have

undergone evolution and the distinction between the two has progressively become blurred with both being used in

computer systems. Many of today’s RISC chips support as many instructions as yesterday’s CISC chips. There are CISC

chips using same techniques that were earlier considered to be used for RISC chips only. However, basic differences

between the two are easy to comprehend and are as follows.

Talking of differences, RISC puts burden on software makers as they have to write more lines for same tasks. RISC is

cheaper than CISC because of fewer transistors required. The speed of the computer is also higher with lesser instructions

to follow at the same instant.

RISC • Simple instructions, few in Number

• Fixed length instructions

• Complexity in compiler • Only LOAD/STORE

Instructions access

Memory

• Few addressing modes

CISC • Many complex instructions

• Variable length instructions

• Complexity in microcode

• Many instructions can Access memory

SECTION-II INTEL 8086

Introduction, 8086Architecture,real and Protected mode memory Addressing,

Memory Paging Addressing Modes.

Various types of instructions: Data movement, Arithmetic and logic; and program

control. Type of instructions, Pin diagram of 8086, clock generator (8284A)

8086 Microprocessor

•It is a 16-bit µp.

•8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).

•It can support up to 64K I/O ports.

•It provides 14, 16 -bit registers.

•It has multiplexed address and data bus AD0- AD15 and A16 - A19.

•It requires single phase clock with 33% duty cycle to provide internal timing.

•8086 is designed to operate in two modes, Minimum and Maximum.

•It can prefetches upto 6 instruction bytes from memory and queues them

in order to speed up instruction execution.

•It requires +5V power supply.

•A 40 pin dual in line package .

Block Diagram of Intel 8086

The 8086 CPU is divided into two independent functional units:

1. Bus Interface Unit (BIU)

2. Execution Unit (EU)

Fig. 1: Block Diagram of Intel 8086

Features of 8086 Microprocessor:

1. Intel 8086 was launched in 1978.

2. It was the first 16-bit microprocessor.

3. This microprocessor had major improvement over the execution speed of 8085.

4. It is available as 40-pin Dual-Inline-Package (DIP).

5. It is available in three versions:

a. 8086 (5 MHz)

b. 8086-2 (8 MHz)

c. 8086-1 (10 MHz)

6. It consists of 29,000 transistors.

Bus Interface Unit (BIU)

The function of BIU is to:

Write the data to memory.

Write the data to the port.

Read data from the port.

Instruction Queue

1. To increase the execution speed, BIU fetches as many as six instruction bytes ahead to time

from memory.

2. All six bytes are then held in first in first out 6 byte register called instruction queue.

3. Then all bytes have to be given to EU one by one.

4. This pre fetching operation of BIU may be in parallel with execution operation of EU, which

improves the speed execution of the instruction.

Execution Unit (EU)

The functions of execution unit are:

To decode the instructions.

To execute the instructions.

The EU contains the control circuitry to perform various internal operations. A decoder in EU

decodes the instruction fetched memory to generate different internal or external control signals

required to perform the operation. EU has 16-bit ALU, which can perform arithmetic and logical

operations on 8-bit as well as 16-bit.

General Purpose Registers of 8086

These registers can be used as 8-bit registers individually or can be used as 16-bit in pair to have AX, BX,

CX, and DX.

1. AX Register: AX register is also known as accumulator register that stores operands for

arithmetic operation like divided, rotate.

2. BX Register: This register is mainly used as a base register. It holds the starting base

location of a memory region within a data segment.

3. CX Register: It is defined as a counter. It is primarily used in loop instruction to store loop

counter.

4. DX Register: DX register is used to contain I/O port address for I/O instruction.

Segment Registers

Additional registers called segment registers generate memory address when combined with other in the

microprocessor. In 8086 microprocessor, memory is divided into 4 segments as follow:

Fig. 2: Memory Segments of 8086

1. Code Segment (CS): The CS register is used for addressing a memory location in the Code

Segment of the memory, where the executable program is stored.

2. Data Segment (DS): The DS contains most data used by program. Data are accessed in the

Data Segment by an offset address or the content of other register that holds the offset

address.

3. Stack Segment (SS): SS defined the area of memory used for the stack.

4. Extra Segment (ES): ES is additional data segment that is used by some of the string to hold

the destination data.

Flag Registers of 8086

Flag register in EU is of 16-bit and is shown in fig. 3:

Fig. 3: Flag Register of 8086

Flags Register determines the current state of the processor. They are modified automatically by CPU

after mathematical operations, this allows to determine the type of the result, and to determine conditions

to transfer control to other parts of the program. 8086 has 9 flags and they are divided into two categories:

1. Conditional Flags

2. Control Flags

Conditional Flags

Conditional flags represent result of last arithmetic or logical instruction executed. Conditional flags are as

follows:

Carry Flag (CF): This flag indicates an overflow condition for unsigned integer arithmetic.

It is also used in multiple-precision arithmetic.

Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow from

lower nibble (i.e. D0 - D3) to upper nibble (i.e. D4 - D7), the AF flag is set i.e. carry given by

D3 bit to D4 is AF flag. This is not a general-purpose flag, it is used internally by the

processor to perform Binary to BCD conversion.

Parity Flag (PF): This flag is used to indicate the parity of result. If lower order 8-bits of the

result contains even number of 1’s, the Parity Flag is set and for odd number of 1’s, the Parity

Flag is reset.

Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else it is reset.

Sign Flag (SF): In sign magnitude format the sign of number is indicated by MSB bit. If the

result of operation is negative, sign flag is set.

Overflow Flag (OF): It occurs when signed numbers are added or subtracted. An OF

indicates that the result has exceeded the capacity of machine.

Control Flags

Control flags are set or reset deliberately to control the operations of the execution unit. Control flags are as

follows:

1. Trap Flag (TP):

a. It is used for single step control.

b. It allows user to execute one instruction of a program at a time for debugging.

c. When trap flag is set, program can be run in single step mode.

2. Interrupt Flag (IF):

a. It is an interrupt enable/disable flag.

b. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the interrupt is

disabled.

c. It can be set by executing instruction sit and can be cleared by executing CLI

instruction.

3. Direction Flag (DF):

a. It is used in string operation.

b. If it is set, string bytes are accessed from higher memory address to lower memory

address.

c. When it is reset, the string bytes are accessed from lower memory address to higher

memory address.

147

Real-Mode and Protected-Mode

Memory Addressing

• Intel® 80386 all the way to Intel® Pentium 4 processors support three

modes of memory addressing: real mode, protected mode, and virtual

8086 mode.

REAL-MODE

• Pentium 4 comes up in the real-mode after it is reset. It will remain in this

mode unless it is switched to protected-mode by software.

• In real mode, the Pentium 4 operates as a very high performance 8086.

• Pentium 4 can be used to execute the base instruction set of the 8086 MPU

(backward compatibility). In addition, a number of new instructions

(called extended instruction set) have been added to enhance its

performance and functionality (such new instructions can be run in the

real-mode as well as the protected-mode).

• In real-mode, only the first 1 M bytes of memory can be addressed with

the typical segment:offset logical address. Each segment is 64K bytes

long.

• Notice that the Pentium 4 microprocessor has 36 bit address bus, which

means it can support up to 236 = 64G bytes of total memory (which cannot

be addressed in real-mode but can be addressed in protected mode).

148

PROTECTED-MODE

• In the protected-mode, memory larger than 1 MB can be accessed.

Windows XP operates in the protected mode.

• In addition, segments can be of variable size (below or above 64 KB).

• Some system control instructions are only valid in the protected mode.

• In protected mode, the base:offset logical memory addressing scheme

(which is used in real mode) is changed.

• The offset part of the logical memory address is still used. However, when

in the protected mode, the processor can work either with 16-bit offsets

(the 16-bit instruction mode) or with 32-bit offsets (the 32-bit instruction

mode). A 32-bit offset allows segments of up to 4G bytes in length. Notice

that in real-mode the only available instruction mode is the 16-bit mode

(during which accessing 32-bit registers requires the prefix 66h).

• However, the segment base address calculation is different in protected

mode. Instead of appending a 0 at the end of the segment register contents

to create a segment base address (which gives a 20-bit physical address),

the segment register contains a selector that selects a descriptor from a

descriptor table. The descriptor describes the memory segment's location,

length, and access rights. This is similar to selecting one card from a deck

of cards in one's pocket.

• Because the segment register and offset address still create a logical

memory address, protected mode instructions are the same as real mode

instructions. In fact, most programs written to function in the real mode

will function without change in the protected mode.

DESCRIPTORS:

• The selector, located in the segment register, selects one of 8192 descriptors

from one of two tables of descriptors (stored in memory): the global and

local descriptor tables. The descriptor describes the location, length and

access rights of the memory segment.

• Each descriptor is 8 bytes long and its format is shown below:

149

• The 8192 descriptor table requires 8 * 8192 = 64K bytes of memory. The

main parts of a descriptor are:

• Base (B31 - B0): indicates the starting location (base address) of the

memory segment. This allows segments to begin at any location in the

processor's 4G bytes of memory.

• Limit (L19 - L0): contains the last offset address found in a segment. Since

this field is 20 bits, the segment size could be anywhere between 1 and 1M

bytes. However, if the G bit (granularity bit) is set, the value of the limit is

multiplied by 4K bytes (i.e., appended with FFFH). In this case, the

segment size could be anywhere between 4K and 4G bytes in steps of 4K

bytes.

• Example,

• Base = Start = 10000000h

• Limit = 001FFh and G = 0

• So, End = Base + Limit = 10000000h + 001FFh = 100001FFh

• Segment Size = 512 bytes

• Base = Start = 10000000h

• Limit = 001FFh and G = 1

• So, End = Base + Limit * 4K = 10000000h + 001FFFFFh = 101FFFFFh

• Segment Size = 2M bytes

150

• AV bit: is used by some operating systems to indicate that the segment is

available (AV = 1) or not available (AV = 0).

• D bit: If D = 0, the instructions are 16-bit instructions, compatible with the

8086-80286 microprocessors. This means that the instructions use 16-bit

offset addresses and 16-bit registers by default. This mode is the 16-bit

instruction mode or DOS mode. If D = 1, the instructions are 32-bits by

default (Windows XP works in this mode). By default, the 32-bit

instruction mode assumes that all offset addresses and all registers are 32

bits. Note that the default for register size and offset address can be

overridden in both the 16- and 32-bit instruction modes using the 66h and

67h prefixes. In 16-bit protected-mode, descriptors are still used but

segments are supposed to be a maximum of 64K bytes.

• Access rights byte: allows complete control over the segment. If the

segment is a data segment, the direction of growth is specified. If the

segment grows beyond its limit, the microprocessor's operating system

program is interrupted, indicating a general protection fault. You can

specify whether a data segment can be written or is write-protected. The

code segment can have reading inhibited to protect software. This is why it

is called protected mode. This kind of protection is unavailable in real-

mode.

SELECTORS:

• Descriptors are chosen from the descriptor table by the segment register.

There are two descriptor tables:

• Global descriptors table: contains segment definitions that apply to all

programs (also called system descriptors).

• Local descriptors table: usually unique to an application (also called

application descriptors).

• Each descriptor table contains 8192 descriptors, so a total of 16,384

descriptors are available to an application at any time. This allows up to

16,384 memory segments to be described for each application.

• The Figure below shows the segment register in the protected mode. It

contains:

151

• 13-bit selector field: chooses one of the 8192 descriptors from the

descriptor table (213 = 8192).

• Table indicator (TI) bit: selects either the global descriptor table (TI = 0) or

the local descriptor table (TI = 1).

• Requested privilege level (RPL) field: requests the access privilege level

of a memory segment. The highest privilege level is 00 and the lowest is 11.

If the requested privilege level matches or is higher in priority than the

privilege level set by the access rights byte, access is granted. Windows

uses privilege level 00 (ring 0) for the kernel and driver programs and level

11 (ring 3) for applications. Windows does not use levels 01 or 10. If

privilege levels are violated, the system normally indicates a privilege

level violation.

• Example:

• Real Mode: DS = 0008h, then the data segment begins at location 00080h

and its length is 64K bytes.

• Protected Mode: DS = 0008h = 0000 0000 0000 1000, then the selector

selects Descriptor 1 in the global descriptor table using a requested

privilege level of 00. The global descriptor table is stored in memory as

shown below.

152

• Descriptor number 1 contains a descriptor that defines the base address as

00100000h with a segment limit of 000FFh. This refers to memory locations

00100000h - 001000FFh for the data segment.

PROGRAM-INVISIBLE REGISTERS:

• The global and local descriptor tables are found in the memory system. In

order to specify the address of these tables, Pentium 4 contains program-

invisible registers LDTR and GDTR (these registers are not directly

addressed by software).

• The GDTR (global descriptor table register), LDTR (local descriptor table

register) and IDTR (interrupt descriptor table register) contain the base

address of the descriptor table and its limit. The limit of these descriptor

tables is 16 bits because the maximum table length is 64K bytes (but of

course, the table could be smaller than 64K byte, hence the need for the

limit).

• Before using the protected mode, the interrupt descriptor table, global

descriptor table along with the corresponding registers IDTR and GDTR

must be initialized. This is why the Pentium 4 boots in the real mode not

protected mode, and why the maximum descriptor table size is 64K bytes.

153

• Each of the segment registers also contains a program-invisible portion

used as a cache to store the corresponding 8 byte descriptor to avoid

repeatedly accessing memory every time the segment register is referenced

(hence the term cache).

• These program-invisible registers are loaded with the base address, limit,

and access rights each time the number in the segment register is changed.

• The TR (task register) holds a selector, which accesses a descriptor that

defines a task. A task is most often a procedure or application program.

The descriptor for the procedure or application program is stored in the

global descriptor table, so access can be controlled through the privilege

levels. The task register allows a context or task switch in multitasking

systems in about 17µs.

• Notice: The memory system for the Pentium 4 is 4G bytes in size, but

access to the area between 4G and 64G is enabled with bit position 4 of the

control register CR4 and is accessible only when 4M paging is enabled.

When in this paging mode, address lines A35 - A32 are enabled with a

special new addressing mode, controlled by other bits in CR4.

154

Memory Paging

• Paging is enabled when the PG bit in control register CR0 is set. The

paging mechanism can function in both the real and protected modes.

• When paging is enabled, physical memory is divided into small blocks

(typically 4K bytes or 4M bytes) in size, and each block is assigned a page

number. The operating system keeps a list of free pages in its memory.

When a program makes a request for memory, the OS allocates a number

of pages to the program.

• A key advantage to memory paging is that memory allocated to a program

does not have to be contiguous, and because of that, there is very little

internal fragmentation - thus little memory is wasted.

• Example: Show memory page allocation for the following sequence:

• Program A requests 3 pages of memory.

• Program C requests 2 pages of memory.

• Program D requests 2 pages of memory.

• Program C terminates, leaving 2 empty pages.

• Program B requests 3 pages of memory, and it is allocated the 2 empty

pages that program C left, plus an additional page after program D.

Page Number Program Allocated to Physical Memory Address

0 Program A.0 0000 - 0FFF

1 Program A.1 1000 - 1FFF

2 Program A.2 2000 - 2FFF

3 Program B.0 3000 - 3FFF

4 Program B.1 4000 - 4FFF

5 Program D.0 5000 - 5FFF

6 Program D.1 6000 - 6FFF

7 Program B.2 7000 - 7FFF

• Consequently, Program A's page tables would contain the following

mapping (Program's Page # =>OS Page # ): (0=>0, 1=>1, 2=>2); Program

B's: (0=>3,1=>4,2=>7); and Program D's : (0=>5, 1=>6). And these

programs operate as if they have contiguous memory space.

155

• Another advantage of paging is the use of virtual memory, where the OS

keeps track of pages that have not been used for some time. Then, when

the OS deems fit, the OS swaps out a page to disk, and brings another page

into memory. In this way, you can use more memory than the computer

physically has. Linear address space

FFFFFFFFh Physical memory

Table(s)

Page (4K) Directory

Page (4K)

Hard Disk

00000000h

swap pages when needed

• When paging is enabled, a logical address is mapped into a linear address

(anywhere between 0 and 4G bytes). Then this linear address is mapped to

another physical address (depending on the amount of physical memory).

• The linear address is defined as the address generated by a program. The

physical address is the actual memory location accessed by a program.

• Translation from the linear address to the appropriate physical address is

done at the hardware level, and is handled by the memory management

unit (MMU), and the process is transparent to the Assembly programmer.

THE PAGE DIRECTORY AND PAGE TABLE

• To convert a 32-bit linear address into a 32-bit physical address, we need to

understand that the most significant 20 bits of the linear address indicate

the linear page number, while the least significant 12 bits of the linear

address indicate the offset within this page. The offset should remain the

same but the linear page number has to be converted into a physical page

number.

156

31 12 11 0

Linear address: Linear page number Offset

Convert to a Physical page number using page directory and table structure

31 12 11 0

Physical address: Physical page number Offset

page size is 4K bytes

• To translate to a physical page number, you have to look up a page

directory, which contains page directory entries. The page directory

contains 1024 page directory entries, each of which is 4 bytes (32 bits). This

means the page directory is 4 K bytes long. There is only one page

directory in memory and its base address is contained in CR3. Note that

this address locates the page directory at any 4K boundary in the memory

system because it is appended internally with 000h.

• Each page directory entry is a physical address pointing to a page table,

which contains page table entries. Each page table contains 1024 page

table entries, each of which is 4 bytes (32 bits). This means that each page

table is 4 K bytes long.

• Each page table entry points to the starting physical address of a page in

memory (i.e., the physical page number).

• This means that if we have one page directory and 1024 page tables, then

157

we have a total of 1M table entries or 1 M pages. Since each page is 4K

bytes long, this will cover a total of 4G bytes of maximum physical

memory.

• The figure below Part (a) shows the linear address (generated by the

software) and how it selects one of the 1024 page directory entries from the

page directory (using the left most 10 bits) and then selects one of the 1024

page table entries (using the next 10 bits). Part (b) of the figure shows the

page table entry, which contains the physical page number that must be

associated with the offset.

• For example, the linear addresses 00000000h-00000FFFh access the first

page directory entry, and the first page table entry. Notice that one page is

a 4K-byte address range. So, if that page table entry contains 00100000h,

then the physical address of this page is 00100000h-00100FFFh for linear

address 00000000h-00000FFFh. This means that when the program accesses

a location between 00100000h and 00100FFFh, the microprocessor

physically addresses location 00100000h-00100FFFh.

158

• The procedure for converting linear addresses into physical addresses:

• A numerical example is shown below:

159

• Because the act of re-paging a 4K-byte section of memory requires access to

the page directory and a page table, which are both located in memory,

Intel has incorporated a special type of cache called the TLB (translation

look-aside buffer). This cache holds the most recent page translation

addresses, so if the same area of memory is accessed, the address is already

present in the TLB, and access to the page directory and page tables is not

required.

• If the entire 4G byte of memory is paged, the system must allocate 4K bytes

of memory for the page directory, and 4K times 1024 or 4M bytes for the

1024 page tables. This represents a con considerable investment in memory

resources. On the Pentium 4 microprocessors, pages can be either 4K bytes

in length or 4M bytes in length. Although no software currently supports

the 4M-byte pages, as the Pentium 4 and more advanced versions pervade

the personal computer arena, operating systems of the future will

undoubtedly begin to support 4M-byte memory pages.

8086 Instruction Set Summary

The following is a brief summary of the 8086 instruction set:

Data Transfer Instructions

MOV

IN, OUT

LEA

LDS, LES

PUSH, POP

XCHG

XLAT

Logical Instructions NOT

AND

OR

XOR

TEST

Move byte or word to register or memory

Input byte or word from port, output word to port Load effective address

Load pointer using data segment, extra segment Push word onto stack, pop word off stack

Exchange byte or word

Translate byte using look-up table

Logical NOT of byte or word (one's complement) Logical AND of byte or word

Logical OR of byte or word

Logical exclusive-OR of byte or word

Test byte or word (AND without storing)

Shift and Rotate Instructions

SHL, SHR

SAL, SAR

ROL, ROR

RCL, RCR

Arithmetic Instructions ADD, SUB

ADC, SBB

INC, DEC

NEG

CMP

MUL, DIV

IMUL, IDIV

CBW, CWD

AAA, AAS, AAM, AAD

DAA, DAS

Transfer Instructions JMP

JA (JNBE)

JAE (JNB)

JB (JNAE)

JBE (JNA)

JE (JZ)

JG (JNLE)

JGE (JNL)

Logical shift left, right byte or word by 1 or CL

Arithmetic shift left, right byte or word by 1 or CL

Rotate left, right byte or word by 1 or CL

Rotate left, right through carry byte or word by 1 or CL

Add, subtract byte or word

Add, subtract byte or word and carry (borrow)

Increment, decrement byte or word

Negate byte or word (two's complement)

Compare byte or word (subtract without storing)

Multiply, divide byte or word (unsigned)

Integer multiply, divide byte or word (signed)

Convert byte to word, word to double word (useful before multiply/divide)

ASCII adjust for addition, subtraction, multiplication,

division (ASCII codes 30-39)

Decimal adjust for addition, subtraction (binary coded decimal numbers)

Unconditional jump

Jump if above (not below or equal)

Jump if above or equal (not below)

Jump if below (not above or equal)

Jump if below or equal (not above)

Jump if equal (zero) Jump if greater (not less or equal)

Jump if greater or equal (not less)

JL (JNGE)

JLE (JNG)

JC, JNC

JO, JNO

JS, JNS

JNP (JPO)

JP (JPE)

LOOP

LOOPE (LOOPZ)

LOOPNE (LOOPNZ)

JCXZ

Jump if less (not greater nor equal)

Jump if less or equal (not greater) Jump if carry set, carry not set Jump

if overflow, no overflow

Jump if sign, no sign

Jump if no parity (parity odd)

Jump if parity (parity even)

Loop unconditional, count in CX

Loop if equal (zero), count in CX

Loop if not equal (not zero), count in CX Jump if CX equals zero

Subroutine and Interrupt Instructions

CALL, RET Call, return from procedure

INT, INTO Software interrupt, interrupt if overflow

IRET Return from interrupt

String Instructions MOVS Move byte or word string

MOVSB, MOVSW Move byte, word string

CMPS Compare byte or word string

SCAS Scan byte or word string

LODS, STOS Load, store byte or word string

REP Repeat REPE, REPZ Repeat while equal, zero

REPNE, REPNZ Repeat while not equal (zero)

Processor Control Instructions STC, CLC, CMC Set, clear, complement carry flag

STD, CLD Set, clear direction flag

STI, CLI Set, clear interrupt enable flag

LAHF, SAHF Load AH from flags, store AH into flags

PUSHF, POPF Push flags onto stack, pop flags off stack ESC Escape to external processor interface

LOCK Lock bus during next instruction

NOP No operation (do nothing)

WAIT Wait for signal on TEST input

HLT Halt processor

PIN CONFIGURATION OF 8086

•The following signal descriptions are common for both modes. •AD15-AD0: These are the time multiplexed memory I/O address and data lines.

• Address remains on the lines during T1 state, while the data is available on the data bus

during T2, T3, Tw and T4.

•These lines are active high and float to a tristate during interrupt acknowledge and local bus

hold acknowledge cycles.

•A19/S6,A18/S5,A17/S4,A16/S3: These are the time multiplexed address and status

lines. •During T1 these are the most significant address lines for memory operations. •During I/O operations, these lines are low. During memory or I/O operations, status

information is available on those lines for T2,T3,Tw and T4.

•The status of the interrupt enable flag bit is updated at the beginning of each clock cycle. •The S4 and S3 combinedly indicate which segment register is presently being used for

memory accesses as in below fig.

•These lines float to tri-state off during the local bus hold acknowledge. The status line S6 is

always low.

•The address bit are separated from the status bit using latches controlled by the ALE

signal.

S4 S3

0 0

0 1

1 0 1 1

Indication

Alternate Data

Stack

Code or none Data

• BHE /S7: The bus high enable is used to indicate the transfer of data over the higher

order ( D15-D8 ) data bus as shown in table. It goes low for the data transfer over D15-

D8 and is used to derive chip selects of odd address memory bank or peripherals. BHE is low

during T1 for read, write and interrupt acknowledge cycles, whenever a byte is to be

transferred on higher byte of data bus. The status information is available during T2, T3 and

T4. The signal is active low and tristated during hold. It is low during T1 for the first pulse of

the interrupt acknowledges cycle.

BHE A0

0 0

0 1

1 0 1 1

Indication

Whole word

Upper byte from or to evenaaddres s

Lower byte from or to even address

None

• RD Read: This signal on low indicates the peripheral that the processor is performing s

memory or I/O read operation. RD is active low and shows the state for T2, T3, Tw of

any read cycle. The signal remains tristated during the hold acknowledge.

•READY: This is the acknowledgement fro m the slow device or memory that they have completed the data transfer. The signal made available by the devices is synchronized by the 8284A clock generator to provide ready input to the 8086. the signal is active high.

•INTR-Interrupt Request: This is a triggered input. This is sampled during the last

clock cycles of each instruction to determine the availability of the request. If any

interrupt request is pending, the processor enters the interrupt acknowledge cycle.

•This can be internally masked by resulting the interrupt enable flag. This signal is active high and internally synchronized.

• TESTThis input is examined by a ‘WAIT’ instruction. If the TEST pin goes low,

execution will continue, else the processor remains in an idle state. The input is

synchronized internally during each clock cycle on leading edge of clock.

•CLK- Clock Input: The clock input provides the basic timing for processor operation and bus control activity. Its an asymmetric square wave with 33% duty cycle.

•MN/ MX : The logic level at this pin decides whether the processor is to operate in either

minimum or maximum mode.

•The following pin functions are for the minimum mode operation of 8086. •M/ IO - Memory/IO: This is a status line logically equivalent to S2 in maximum mode.

When it is low, it indicates the CPU is having an I/O operation, and when it is high, it

indicates that the CPU is having a memory operation. This line becomes active high in the

previous T4 and remains active till final T4 of the current cycle. It is tristated during local

bus “hold acknowledge “.

• INTA Interrupt Acknowledge: This signal is used as a read strobe for interrupt

acknowledge cycles. i.e. when it goes low, the processor has accepted the interrupt.

•ALE - Address Latch Enable: This output signal indicates the availability of the valid address on the address/data lines, and is connected to latch enable input of latches. This signal is active high and is never tristated.

•DT/ R - Data Transmit/Receive: This output is used to decide the direction of data

flow through the transreceivers (bidirectional buffers). When the processor sends out

data, this signal is high and when the processor is receiving data, this signal is low.

•DEN - Data Enable: This signal indicates the availability of valid data over the address/data lines. It is used to enable the transreceivers ( bidirectional buffers ) to

separate the data from the multiplexed address/data signal. It is active from the middle of

T2 until the middle of T4. This is tristated during ‘ hold acknowledge’ cycle.

•HOLD, HLDA- Acknowledge: When the HOLD line goes high, it indicates to the processor that another master is requesting the bus access.

•The processor, after receiving the HOLD request, issues the hold acknowledge signal on

HLDA pin, in the middle of the next clock cycle after completing the current bus

cycle.•At the same time, the processor floats the local bus and control lines. When the processor detects the HOLD line low, it lowers the HLDA signal. HOLD is an

asynchronous input, and is should be externally synchronized.

•If the DMA request is made while the CPU is performing a memory or I/O cycle, it will release the local bus during T4 provided:

1.The request occurs on or before T2 state of the current cycle.

2.The current cycle is not operating over the lower byte of a word. 3.The current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A Lock instruction is not being executed. •The following pin function are applicable for maximum mode operation of 8086.

•S2, S1, S0 - Status Lines: These are the status lines which reflect the type of operation,

being carried out by the processor. These become activity during T4 of the previous cycle

and active during T1 and T2 of the current bus cycles.

S2 S1 S0 Indication

0 0 0 Interrupt Acknowledge 0 0 1 Read I/O port 0 1 0 Write I/O port 0 1 1 Halt 1 0 0 Code Access 1 0 1 Read memory 1 1 0 Write memory 1 1 1 Passive

• LOCK This output pin indicates that other system bus master will be prevented from

gaining the system bus, while the LOCK signal is low.

•The LOCK signal is activated by the ‘LOCK’ prefix instruction and remains active until

the completion of the next instruction. When the CPU is executing a critical instruction

which requires the system bus, the LOCK prefix instruction ensures that other processors

connected in the system will not gain the control of the bus. •The 8086, while executing the prefixed instruction, asserts the bus lock signal output, which may be connected to an external bus controller.

•QS 1, QS0 - Queue Status: These lines give information about the status of the code-

prefetch queue. These are active during the CLK cycle after while the queue operation is

performed.

•This modification in a simple fetch and execute architecture of a conventional microprocessor offers an added advantage of pipelined processing of the instructions.

•The 8086 architecture has 6-byte instruction prefetch queue. Thus even the largest (6-

bytes) instruction can be prefetched from the memory and stored in the prefetch. This

results in a faster execution of the instructions.

•In 8085 an instruction is fetched, decoded and executed and only after the execution of this instruction, the next one is fetched.

•By prefetching the instruction, there is a considerable speeding up in instruction execution in 8086. This is known as instruction pipelining.

•At the starting the CS:IP is loaded with the required address from which the execution is to be started. Initially, the queue will be empty an the microprocessor starts a fetch

operation to bring one byte (the first byte) of instruction code, if the CS:IP address is odd

or two bytes at a time, if the CS:IP address is even.

•The first byte is a complete opcode in case of some instruction (one byte opcode instruction) and is a part of opcode, in case of some instructions ( two byte opcode instructions), the remaining part of code lie in second byte.

•The second byte is then decoded in continuation with the first byte to decide the

instruction length and the number of subsequent bytes to be treated as instruction data.

SECTION-III

INTERRUPTS:

Introduction, 8257 Interrupt controller, basic DMA operation and 8237 DMA

Controller,

Arithmetic coprocessor, 80X87 Architecture.

The Intel* 8257 is a 4-channel direct memory access (DMA) controller. It is specifically designed to simplify the

transfer of data at high speeds for the Intel® microcomputer systems. Its primary function is to generate, upon a

peripheral request, a sequential memory address which will allow the peripheral to read or write data directly to or

from memory. Acquisition of the system bus in accomplished via the CPU's hold function. The 8257 has priority logic

that resolves the peripherals requests and issues a composite hold request to the CPU. It maintains the OMA cycle

count for each channel and outputs a control signal Jo notify the peripheral that the programmed number of OMA

cycles is complete. Other output control signals simplify sectored data transfers. The 8257 represents a significant

savings in component count for DMA-based microcomputer systems and greatly simplifies the transfer of data at

high speed between peripherals and memories.

1.

Interrupt is signals send by an external device to the processor, to request the processor to perform a

particular task or work.

Mainly in the microprocessor based system the interrupts are used for data transfer between the peripheral

and the microprocessor.

The processor will check the interrupts always at the 2nd T-state of last machine cycle.

If there is any interrupt it accept the interrupt and send the INTA (active low) signal to the peripheral.

The vectored address of particular interrupt is stored in program counter.

The processor executes an interrupt service routine (ISR) addressed in program counter.

It returned to main program by RET instruction.

.