Continuous-time, multibit, complex ¢†â€ ®£ jesus/analog/ctds/slides_des.pdf 320 Ms/s, 16x oversampling,

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  • Continuous-time, multibit, complex ∆Σ ADC

    320 Ms/s, 16x oversampling, 3-bit quantizer, 10-bit ENOB.

    J. Arias, P. Kiss, V. Prodanov

    -100

    -80

    -60

    -40

    -20

    0

    -60 -40 -20 0 20 40 60

    A m

    pl . (

    dB )

    Freq. (MHz)

  • Motivation

    ➯ Why complex ∆Σ:

    ✔ Channel selection and image rejection are done in the digital domain by the decimation filter.

    ✔ Easy analog filtering. (good IQ imbalance, low power)

    ➯ Why continuous-time (CT):

    ✔ Capable of operation at high sampling frequencies.

    ✔ Low power consumption.

    ✔ Implicit anti-aliasing property.

    ➯ Why multibit:

    ✔ Good SNR for low oversampling ratios. (16)

    ✔ Good stability.

  • Drawbacks

    ➯ ∆Σ ADCs:

    ∆Σ ADCs requires high sampling rates ( oversampling 16, typical)

    A digital filter/decimator is needed (several Kgates).

    ∆Σ ADCs consume more power than Nyquist-rate ADCs. (But the total power bill can be lower)

    ➯ CT ∆Σ modulators:

    Involves DT to CT transformations (NTF) Tedious mathematics & controllability issues.

    CT modulators are more sensitive to clock jitter.

    ➯ Multibit ∆Σ modulators:

    Sensitive to DAC nonlinearity. Dynamic element matching (scrambler) needed.

  • IEEE 802.11a/g, low-IF, receiver with Nyquist-rate ADC

    lo1 I

    lo2

    �����

    �����

    25

    2

    26

    �����

    1 1 2

    �����

    26

    Q

    fS 1 � 0 � 1 � 0

    0 � 1 � 0 � 1 Q

    I

    CBPF

    10-20 -10 20 [MHz] -40 -20 0 20 40

    fS

    0

    BW 20 MHz, SNDR 55 dB

    Nyquist ADC (1 ):

    7-pole Chebyshe v filter 10-bit pipelined ADC

    BW 20 MHz, fIF 10 MHz

    AAF

    fS

    Complex BPF (1 ):

    (Vladimir) (Jesús)

    ADC FFTLNA

  • IEEE 802.11a/g, low-IF, receiver with ∆Σ ADC

    lo1 I

    lo2

    �����

    �����

    25

    2

    26

    �����

    1 1 2

    �����

    26

    Q

    CBPF

    [MHz] 00 20-20-20 20 -320 320

    fS

    Q I

    Complex BPF:

    BW 20 MHz, SNDR 55 dB

    fS fS

    1 � 0 � 1 � 0

    0 � 1 � 0 � 1Q

    IfSOSR

    2nd-or der 3-bit 16 oversampled

    Complex CT ∆Σ ADC: BW 20 MHz, fIF 10 MHz

    AAF

    3-pole Butterw or th filter

    (Vladimir) (Peter/Vladimir/Jesús)Proposed architecture

    FFTLNA D E CADC

    ∆Σ

  • Modulator architecture (Real DSM)

    -80

    -60

    -40

    -20

    0

    20

    1 10 100 G

    a in

    ( d

    B )

    Freq. (MHz)

    NTF

    u(t) v[n]

    v[n]u(t)

    After amplitude equalization

    Starting modulator

    1

    DAC RZ

    −3.5

    11

    Ts

    1

    Ts

    DAC RZ

    −3.5

    1

    Ts

    1

    Ts

    1.660.6

    −1.2

    − Second−order NTF

    − 3−bit ADC and DAC

    − RZ DAC: less sensitive to:

    ADC metastability

    Clock jitter

    − Optimized zero: +3dB SNR

    −0.015

    −0.009

    ADC

    −2

    fs

    ADC

    fs

  • Digital Domain

    clk

    GM2GM1 C1

    u(t) v[n]

    IDAC2IDAC1

    Gm−C Implementation (Real DSM, Single−ended)

    C2

    −GM3

    SCR

    RZ

    ADC

    fs

  • Multibit DACs: Overcoming nonlinearity using dynamic element matching

    -120

    -100

    -80

    -60

    -40

    -20

    0

    1 10 100

    A m

    pl . (

    dB )

    Freq. (MHz)

    ideal DACs 2% mismatch

    2% mismatch & DWA

  • DWA logic (scrambler)

    Rotator

    Thermometer to binary

    RZ

    Reg. Reg.clkclk

    clk

    esp

    esn

    es

    8−bit

    fr om

    A D

    C

    to D

    A C

    s

    DSM output

    Σ

  • Thermal noise

    A/Vµ

    µ A µ A µ A

    µ A

    A/Vµ A/Vµ

    -120

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    -40

    -20

    0

    1 10 100

    A m

    pl . (

    dB )

    Freq. (MHz)

    Noiseless Thermal noise

    GM2: 200

    GM3: 15

    C1: 5.165 pF

    C2: 0.376 pF

    Ib2: 147

    Ib1: 714 Idac1: 95.4

    Idac2: 20.1

    GM1: 1000

    Noise simulation parameters:

    Performance loss: 2 dB SNR

  • Real DSM. Detailed schematic

    Scrambler

    µ S

    µ S µ S

    µ A µ A

    µ A

    µ A

    +

    +

    +

    ++

    +

    +

    +

    GM1

    GM3 level shifter

    DAC1 DAC2

    DSM output analog

    input

    Vdd Vdd

    Ibias1

    CMFB

    − −

    17

    C1 C2

    1000 200

    15

    8 x 95.4 8 x 20.1

    5.16 pF 0.37 pF

    logic

    7−level

    ADC

    147 Ibias2

    714

    GM2

  • Circuit Elements: Transconductors

    − Large dynamic range

    − Unipolar output

    − External tuning

    − Vladimir’s patent (2001)

  • Circuit Elements: Transconductor’s nonlinear Gm

    −1 −0.5 0 0.5 1 0

    1

    2

    3

    4

    5

    x 10 −5

    Vin(diff) [V]

    G m

    [A

    /V ]

    −0.5 0 0.5 4.81

    4.85

    4.89

    x 10 −5 25 × "amplified"

    S: 85C, 74uA N: 25C, 66uA F: 0C, 59uA S: tanh approx N: tanh approx F: tanh approx

    Gm x Gm 0 ∂∂x tanh x 0 � 82

    3 x 3 2 � 14

    5 x 5 0 � 60

    7 x 7

  • Circuit Elements: Small Transconductors (GM3)

    − Pseudodifferential: poor common mode rejection

    − Good linearity

    − Low power efficiency

    − Low accuracy: Gm depends on Vcas and Cm(Vin)

    TriodeTriode

  • S D

    G

    resistance channel

    Cgs

    0

    0.2

    0.4

    0.6

    0.8

    1

    1.2

    0 0.5 1 1.5 2 2.5

    N or

    m . C

    ap ac

    ita nc

    e

    Gate Voltage (V)

    � � � � � � � � � � � � � � � � � � � �

    Channel resistance is not simulated unless

    "nqsmod=1"

    Big capacitors must be split into parallel,

    is specified on every capacitor

    gnd

    small, capacitors to improve their Q

    P

    NP+ + P+N+

    Circuit Elements: Capacitors: Inversion MOSFETs

    C2

    C1

  • Circuit Elements: ADC

    la tc

    h la

    tc h

    la tc

    h la

    tc h

    la tc

    h la

    tc h

    la tc

    h

    Vi−

    p5

    p1

    n4

    p7 n7

    p6 n6

    n5

    p4

    p3

    p2

    n1

    n2

    n3

    p1

    n7

    p2

    n6

    p3

    n5

    p4

    n4

    p5

    n3

    p6

    n2

    p7

    n1

    t7

    t6

    t5

    t4

    t3

    t2

    t1

    70mV

    Vdd

    90 Ω Rnplus

    0.5V

    Input Range

    2.5V

    1.8V

    0V

    Vi+

    Vbias

  • Circuit Elements: ADC biasing

  • Circuit Elements: ADC’s comparators

    ck

    Vi+

    Vi−

    Vdd

    /dck

    /ck

    ck

    out

    NC

    sampling window

    latched

    regen. track.

    transp.

    out N−1

    internal nodes

    dck

    ck

    sample N

    sample

    track.

    Comparator & Latch

    Signal Timming

  • Circuit Elements: Current-mode DACs

    Current cell Signal timming

    Current−mode DACs

    Io+

    Io−

    esp0esn0 esn1 esp1 esn7 esp7

    Vcas

    Vbias

    Vref espesn

    esp

    esn

    ck

  • Circuit Elements: CMFB

  • Real DSM results (spectre simulation with extracted blocks)

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    0

    1 10 100

    A m

    pl . (

    dB )

    Freq. (MHz)

    (2048 samples)

    SNR = 61 dB SNDR = 57 dB

  • Complex DSM schematic

    clk

    clk

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    -60 -40 -20 0 20 40 60

    A m

    pl . (

    dB )

    Freq. (MHz)

    Two real modulators

    GM1

    IDAC1 IDAC2 RZ

    ADCGM2

    C1 C2

    Qv[n]

    Iv[n]

    Qu(t)

    Iu(t)

    SCR

    GM2 ADCGM1 C1

    SCR

    IDAC2

    C2

    RZ

    −GM3

    −GM3

    IDAC1

    fs

    fs

  • Complex DSM schematic

    clk

    clk

    −GM4 GM4 −GM5 GM5

    GM1

    IDAC1 IDAC2 RZ

    ADCGM2

    C1 C2

    Qv[n]

    Iv[n]

    Qu(t)

    Iu(t)

    10 MHz

    Freq. shift

    SCR

    GM2 ADCGM1 C1

    SCR

    IDAC2

    C2

    RZ

    −GM3