1

COMP541COMP541

Memories II:Memories II:DRAMsDRAMs

Montek SinghMontek Singh

Mar 2, 2010Mar 2, 2010

TopicsTopics Random-Access MemoryRandom-Access Memory

DynamicDynamic

2

Dynamic RAMDynamic RAM Capacitor can hold chargeCapacitor can hold charge Transistor acts as gateTransistor acts as gate No charge = ‘0’No charge = ‘0’ Can connect switch & add charge to store a ‘1’Can connect switch & add charge to store a ‘1’ Then disconnect switchThen disconnect switch Can read by connecting switchCan read by connecting switch

Sense ampsSense amps

3

DRAM Bit CellDRAM Bit Cell Contrast w/ SRAMContrast w/ SRAM

4

5-<4>

wordline

bitline bitlinewordline

bitline

DRAM bit cell: SRAM bit cell:

Hydraulic AnalogyHydraulic Analogy

5

StorageFull (1)

Empty (0)Pump fills tank to 1

value

Pump drains tank to 0 value

ReadingReading

6

Tank had a 1 value – raises

water level

Outside water begins at

intermediate level (black wavy line)

Tank had a 0 value – lowers

water level

DRAM CharacteristicsDRAM Characteristics Destructive ReadDestructive Read

When cell read, charge removedWhen cell read, charge removed Must be restored after a readMust be restored after a read

RefreshRefresh Also, there’s steady leakageAlso, there’s steady leakage Charge must be restored periodicallyCharge must be restored periodically

7

DRAM Logical DiagramDRAM Logical Diagram

8

DRAM Read SignalingDRAM Read Signaling Lower pin count by using same pins for row Lower pin count by using same pins for row

and column addressesand column addresses

9

Delay until data

available

DRAM Write TimingDRAM Write Timing

10

DRAM RefreshDRAM Refresh Many strategiesMany strategies Logic on chipLogic on chip Here a row counterHere a row counter

11

TimingTiming Say need to refresh every 64msSay need to refresh every 64ms Distributed refreshDistributed refresh

Spread refresh out evenly over 64msSpread refresh out evenly over 64ms Say on a 4Mx4 DRAM, refresh window for row Say on a 4Mx4 DRAM, refresh window for row

64ms/4096=15.6 us64ms/4096=15.6 us Total time spent is 0.25ms, but spreadTotal time spent is 0.25ms, but spread

Burst refreshBurst refresh Same 0.25ms, but all at onceSame 0.25ms, but all at once May not be good in a computer systemMay not be good in a computer system

Refresh takes low % of total timeRefresh takes low % of total time

12

Bidirectional LinesBidirectional Lines Many chips have one set of data pinsMany chips have one set of data pins Used as input for writeUsed as input for write As output for readAs output for read Tri-stateTri-state Makes sense because don’t need both at onceMakes sense because don’t need both at once

13

Page Mode DRAMPage Mode DRAM DRAMs made to read & write blocksDRAMs made to read & write blocks ExampleExample

Assert RAS, leave assertedAssert RAS, leave asserted Assert CAS multiple times to read sequence of dataAssert CAS multiple times to read sequence of data

Similar for writesSimilar for writes

14

Synchronous DRAM (SDRAM)Synchronous DRAM (SDRAM) Has a clockHas a clock Common type in PCs late-90sCommon type in PCs late-90s

Typical DRAMs still synchronousTypical DRAMs still synchronous

Multiple Multiple banksbanks PipelinedPipelined

Start read in one bank after anotherStart read in one bank after another Come back and read the resulting values one after Come back and read the resulting values one after

anotheranother

15

Read with AutoprechargeRead with Autoprecharge

16

Basic Mode of OperationBasic Mode of Operation

Slowest modeSlowest mode Uses only single row and column addressUses only single row and column address Row access is slow (60-70ns) compared to column access (5-10ns)Row access is slow (60-70ns) compared to column access (5-10ns) Leads to three techniques for DRAM speed improvementLeads to three techniques for DRAM speed improvement

Getting more bits outGetting more bits out of DRAM on one access given timing of DRAM on one access given timing constraintsconstraints

PipeliningPipelining the various operations to minimize total time the various operations to minimize total time Segmenting the dataSegmenting the data in such a way that some operations are in such a way that some operations are

eliminated for a given set of accesseseliminated for a given set of accesses17

Row ColumnAddress

RAS

CAS

DataData

18

Nibble (or Burst) ModeNibble (or Burst) Mode

Several consecutive columns are accessedSeveral consecutive columns are accessed Only first column address is explicitly specifiedOnly first column address is explicitly specified Rest are internally generated using a counterRest are internally generated using a counter

RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS

RA CAD1 D2 D3 D4

RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS

RA CAD1 D2 D3 D4

19

Fast Page ModeFast Page Mode

Accesses arbitrary columns within same rowAccesses arbitrary columns within same row Static column mode is similarStatic column mode is similar

RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS

RA CA1 CA2 CA3 CA4D1 D2 D3 D4

RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS

RA CA1 CA2 CA3 CA4D1 D2 D3 D4

20

EDO ModeEDO Mode

Arbitrary column addressesArbitrary column addresses PipelinedPipelined EDO = Extended Data OutEDO = Extended Data Out Has other modes like “burst EDO”, which allows Has other modes like “burst EDO”, which allows

reading of a fixed number of bytes starting with each reading of a fixed number of bytes starting with each specified column addressspecified column address

RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS CAS CAS CAS

RA CA1 CA2 CA3 CA4 CA5 CA6 CA7D1 D2 D3 D4 D5 D6

RAS ---- ---- ---- ---- ---- ---- ---- ---- ----CAS CAS CAS CAS CAS CAS CAS

RA CA1 CA2 CA3 CA4 CA5 CA6 CA7D1 D2 D3 D4 D5 D6

DRAM on NEXYS2 BoardDRAM on NEXYS2 Board Relatively small at Relatively small at

128Mbits128Mbits 8M X 168M X 16

Internal refreshInternal refresh Supports pipeliningSupports pipelining Bidirectional data Bidirectional data

lines, full set of lines, full set of address linesaddress lines

Async (right) and sync Async (right) and sync modesmodes Page, burstPage, burst 70ns read cycle time70ns read cycle time

21

http://download.micron.com/pdf/datasheets/psram/128mb_burst_cr1_5_p26z.pdf

DDR DRAMDDR DRAM Double Data Rate SDRAMDouble Data Rate SDRAM Transfers data on both edges of the clockTransfers data on both edges of the clock Currently popularCurrently popular Attempt to alleviate the pinout problemsAttempt to alleviate the pinout problems

22

RAMBUS DRAM (RDRAM)RAMBUS DRAM (RDRAM) Another attempt to alleviate pinout limitsAnother attempt to alleviate pinout limits Many (16-32) banks per chipMany (16-32) banks per chip Made to be read/written in packetsMade to be read/written in packets Up to 1200MHz bus speedsUp to 1200MHz bus speeds

XDR – 8 bits per clock, 16-bit wide bus, 6.4GBXDR – 8 bits per clock, 16-bit wide bus, 6.4GB But DDR doing very well alsoBut DDR doing very well also

23

DRAM ControllersDRAM Controllers Very common to have chip/module that Very common to have chip/module that

controls memorycontrols memory Handles banksHandles banks Handles refreshHandles refresh

Multiplexes column and row addressesMultiplexes column and row addresses RAS and CAS timingRAS and CAS timing

Northbridge on PC chip setNorthbridge on PC chip set

24

ConclusionsConclusions RAMs with different characteristicsRAMs with different characteristics

For different purposesFor different purposes

Static RAMStatic RAM Simple to use, small, expensiveSimple to use, small, expensive Fast, used for cacheFast, used for cache

Dynamic RAMDynamic RAM Complex to interface, largest, cheapComplex to interface, largest, cheap Needs periodic refreshNeeds periodic refresh

25

LinksLinks Ram Guides (not very technical)Ram Guides (not very technical)

http://arstechnica.com/paedia/storage.html

DRAM on XSA-100 boardDRAM on XSA-100 boardhttp://www.hynix.co.kr/datasheet/pdf/dram/(2)HY57V2

81620A(L)T-I.PDF

26