Memristors-Based Ternary Content Addressable

Memory (mTCAM) Le Zheng, Sangho Shin, and Sung-Mo Steve Kang*

Jack Baskin School of Engineering

University of California, Santa Cruz

Santa Cruz, CA 95064, USA

{lezheng, sshin}@soe.ucsc.edu

*Korea Advanced Institute of Science and Technology

Daejeon, Korea

kangsm@kaist.ac.kr

Abstract A memristors-based Ternary Content Addressable

Memory (mTCAM) is presented. A unit mTCAM cell consists of

5T2R, five transistors and two memristors to store the ternary

information, having higher storage density than conventional

CMOS TCAMs together with the memristors unique non-volatility. In the write mode, each memristor in the cell is

programmed individually such that high impedance is always

present between searchlines to reduce the direct current. A two-

step write scheme is proposed to reduce the write voltage

compliance, and the search voltage used to drive the search

content was chosen to optimize the sensing margin. Simulation

results for a 24 mTCAM array demonstrate the functionality

and feasibility of the proposed mTCAM structure, in both write

and search modes.

I. INTRODUCTION

Content Addressable Memory (CAM) is a storage system addressed by the content (or data) instead of the memory address. A simplified diagram of a CAM is shown in Fig. 1. The search word is driven on the searchlines (SL) and is compared with the pre-stored data. The matchline (ML) of each stored word indicates the comparison result (match or mismatch). All matchlines are fed into an encoder which will generate an address corresponding to the matched word. Since CAMs have a single clock throughput, they are ideally suited for applications such as Ethernet address lookup, data compression, pattern recognition, search engine and image processing [1]. A ternary CAM (TCAM) is a special type of CAM that allows for storing and searching a wildcard (X) in addition to 0 and 1. Recent efforts have focused on incorporating memristors into the CAM cells [2],[6]. Compared with conventional CMOS TCAMs, memristors-based CAMs have the potential to attain higher storage density, lower average power consumption and more importantly exceptional non-volatility.

While previous literatures have demonstrated basic functionalities of memristors-based CAM/TCAM, their limitations are summarized below. First, when memristors are connected to the matchlines directly, the large parasitics on the matchlines reduces both sensing speed and sensitivity [3],[4],[7]. Second, some designs directly apply voltages to the gates of transistors via memristors, where the sensing reliability is compromised since the high impedance appeared on the gates obscure the resistive states of the memristors

[2],[6]. Third, a high storage density is difficult to be achieved if a cell structure contains a large number of transistors [2],[4]. Last, detailed circuit-level descriptions of the write mode operation are absent [4],[7].

We propose a high-density energy-efficient memristors-based TCAM (mTCAM). The mTCAM cell is comprised of five transistors and two memristors, i.e., 5T2R. A unique write sequence is proposed to write any data into the cell in two clock cycles regardless of its initial content. The voltage compliance during write/search is carefully designed to reduce the direct current and optimize the sensing margin. After describing the matchline scheme and the array architecture, simulations on an illustrative 24 array demonstrate the basic functionalities of the proposed mTCAM in both write and search modes.

The rest of this paper is organized as follows. Section II briefly discusses the desired behaviors of the memristors used in TCAM applications. The cell structure, the matchline scheme and the architecture of the mTCAM array are described in Section III. In Section IV, simulations results on the mTCAM array will be presented. Finally Section V concludes the paper.

II. MEMRISTOR CHARACTERISTICS

The memristor used in this work has the following characteristics: LRS = 10k, HRS = 1M, VSET = 1.5V, VRESET = 1.5V. These properties can all be reflected on SPICE-compatible environments by using our previously reported modular model for memristive devices [8]. The

This work was supported in part by the University of California, in part

by the UC Lab Fees Program (LF 326181), and in part by the National Research Foundation of Korea (NRF-2011-220-D00089).

Fig. 1. Simplified diagram of a CAM.

978-1-4799-3432-4/14/$31.00 2014 IEEE 2253

current-voltage characteristic of the memristor is shown in Fig. 2, where the memristor is tested with an external sinusoidal voltage at a frequency of 1MHz. The observed pinched hysteresis indicates the memory effect of the device and its binary resistance states. The transient waveforms of the resistance switching are shown in the inset of Fig. 2. Under a voltage step from 0V to 2V, the device starts switching from HRS to LRS as soon as the voltage exceeds the SET threshold. Note that the switching time switch, which is defined as the period for the device to switch completely from HRS (LRS) to LRS (HRS), is determined by the intrinsic characteristics of the device and the applied voltage. With a voltage overhead of 0.5V, the device has a switching time of switch 5ns. Both spatial and temporal variations of the devices have been accounted in our model, and their influences on the mTCAM will be discussed briefly in Section III.

III. CIRCUIT LEVEL BUIDLING BLOCKS

A. mTCAM Cell

The relationship between the data stored in the mTCAM cell and the states of the memristors are summarized in Fig. 3(a). The binary data stored on a single memristor can be interpreted by its memristance RM, i.e., D = 0 when RM = HRS and D = 1 when RM = LRS. To store ternary data, an mTCAM cell employs two memristors. The content of the cell is 0 or 1 when two memristors store the complementary data. To represent the wildcard (X), 0 is stored on both memristors. Note that the cell content is designed such that at least one HRS is present for any stored data. As will be discussed later in this Section, this helps to reduce the static power consumption in the search mode by limiting the direct current between searchlines. The schematics of the proposed mTCAM cell in both write and search modes are shown in Fig. 3 (b) and (c) respectively, with irrelevant devices greyed-out. An mTCAM cell consists of five transistors and two memristors, i.e., 5T2R. The memristors M1 and M2 are connected in series but with

opposite polarities, storing data D and D respectively. N1 and N2 are access transistors that can be activated by the wordline

(WL), allowing voltages on searchlines SL and SL to be

applied on M1 and M2. N3 is a pull-down transistor connected to ML and is activated only in the search mode by the voltage

VG. SX and SX are two additional searchlines connected to N4 and N5 respectively. N4 is used in both write and search modes while N5 is only used in the write mode.

In the write mode, the content stored in each cell is

programmed by suitably controlling SL, SL , SX and SX so that appropriate voltages are applied across M1 and M2. After the write command is issued, ML is shorted to ground via an external switch (not shown in Fig. 3) and WL is set high. The voltages at the negative terminals of M1 and M2 are directly

driven by SL and SL . The voltage at the common node of M1

and M2 is labeled VG, which is controlled by SX and SX. For example, when both SX and SX are high, N4 is ON and N5 is OFF, so VG is low; vice versa. Note that in the write mode, SX and SX are always tied to the same voltage to clearly set VG. The separate control of voltage drops on M1 and M2 is beneficial because: 1) it allows the configuration of RM1 = RM2 = HRS (which is not available as a stable state from complementary resistive switch [9]) to reduce the direct current

between SL and SL ; 2) the maximum voltage needed in the

write mode is on the order of |VSET| or |VRESET| as opposed to 2|VRESET| in the case of [9]. A novel 2-step write sequence is described in Table I, where the voltages applied on each

memristor are shown. For example, to write D D = 01, the first

step resets D to 0 and maintains the state of D . The second step

sets D to 1 and maintains the state of D. The proposed write sequence configures the content of the mTCAM cell in only two clock cycles regardless of its initial value. This is especially favorable in the power-on reset of a memory where a reliable write is required when the pre-stored information is usually unknown. Assuming the voltage drops on N1 and N2

Fig. 3 Summary of data definitions in the mTCAM cell (a) and

schematics of the mTCAM cell in write (b) and search (c) modes.

Fig. 2 i-v characteristic of the memristor used in this work. Inset: transient voltage and memristance waveforms.

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are negligible, the maximum voltage applied on M1 or M2, Vwrite, should satisfy the following requirement,

Vwrite>|VSET| and |VRESET| (1)

In the search mode, ML is precharged to high and its final voltage level depends on the search result. SX is set to high to

deactivate N5. SL, SL and SX become the three effective

searchlines. When searching for 0 (or 1), SL and SL are driven

to low (high) and high (low), and SX is driven to low. The voltage VG is thus a result of a resistor divider between SL and

SL . A match will keep ML at its precharged level and a mismatch will discharged ML to ground. As a result, the

voltage difference between SL and SL , Vsearch, should

guarantee that N3 is turned OFF if match and ON if mismatch. A detailed analysis on Vsearch is presented in Table II where Vth is the threshold voltage of N3. In summary Vsearch should satisfy the following,

Vth < Vsearch < 2Vth (2)

Vsearch < |VSET| and |VRESET| (3)

where (3) indicates that the stored content should not be disturbed in the search mode. When searching for X, SX is set to high so that a match is always obtained as ML maintains its potential when VG is forced to ground by SX. Meanwhile

SL and SL are tied to ground to minimize the direct current

between searchlines.

Note that the requirements for Vsearch shown in Table II, (2), and (3) are based on an assumption that the ratio of HRS/LRS is large enough so that VG 0, Vsearch/2, or Vsearch depending on the stored content. In reality, however, since both HRS and LRS experience statistical variations, Vsearch is needed to satisfy the worst case scenario. It turns out that (2) and (3) provide good approximations even when HRS/LRS is reduced from 100 to 10. Moreover the optimal Vsearch depends on the probability of each match/mismatch case listed in Table II. For simplicity, we have chosen Vsearch = 1V in the following simulations which set the sensing margins evenly for match and mismatch cases.

B. Matchline Scheme

A NOR matchline scheme is adopted where all the bit cells of a stored word are connected in parallel to a matchline, as shown in Fig. 4. This ensures a word match retains the matchlines potential whereas one bit mismatch discharges the matchline to the ground. In the write mode (write_en = 1), N0 is used to reset ML to the ground. In the search mode, P0 is

used to charge ML to high during the precharge phase ( pre =

0) before ML is actively driven in the evaluation phase ( pre =

1). Note that the circuit in the dashed box in Fig. 4 establishes the relationship between SX and SX: in the write mode

TABLE I. SUMMARY OF TWO-STEP WRITE SCHEME

Content = X Content = 0 Content = 1

D = 0 D = 0 D = 0 D = 1 D = 1 D = 0

Step 1 VRESET 0 VRESET 0 VSET 0

Step 2 0 VRESET 0 VSET 0 VRESET

TABLE II. SUMMARY OF REQUIREMENTS ON VSEARCH

Search Content Result Requirements

0 (or 1)

X Match Vsearch/2 < Vth

0 (or 1) Match 0 < Vth

1 (or 0) Mismatch Vsearch > Vth

Fig. 4 Schematic of the matchline scheme.

Fig. 5 Architecture of an mn mTCAM array.

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(write_en = 1), SX = SX ; in the search mode (write_en = 0), SX = 1. As will be shown in the next Section, this circuit can be conveniently placed inside the write/search driver circuitry.

C. Array Architecture

A generic mn mTCAM array with peripheral circuitry is shown in Fig. 5. The array stores m words and each word has n bits. Cells are placed in an mn grid with horizontal matchlines

(ML), wordlines (WL) and vertical searchlines (SL, SL , SX,

SX). Wordlines are driven by enable drivers while searchlines are driven by write/search drivers. The outputs of all sense amplifiers (SA) are fed into an m-bit encoder that generates the desired address based on its inputs. Since the mTCAM array may contain zero, one or multiple matched entries, the encoder should include a priority logic to reflect all the possible search results.

IV. SIMULATION RESULTS

A 24 array of mTCAM array is designed and simulations are carried out in both write and search modes. Vwrite is set to 2.5V and Vsearch is set to 1V.

In the write mode, data 1, 0 and X are sequentially written into the cell. The transient waveforms are depicted in Fig. 6. The period to write a data into the cell is 20ns, which contains two steps. The switching time switch is observed as ~5ns. At the end of each write period, the desired data is successfully stored regardless of the initial content in the cell. Note that the finite transition time appears at VG is primarily dependent on the HRS value and the parasitic capacitances at the node.

In the search mode, the contents in the array is programmed as C1 = {1, X, 1, 0} and C2 = {0, X, 0, 1}. The search word is sequentially set to S1 = {1, 1, X, 0} and S2 = {0, 1, X, 1}. Before the search, both ML1 and ML2 are precharged to 1V. The transient voltage waveforms of ML1 and ML2 under two different ML parasitic capacitances (CML and CML/2) are shown in Fig. 7. It can be seen that C1 matches

S1 while C2 matches S2. In reality, the search speed depends on the data pattern, the maximum discharging current of each cell and the parasitics on the matchline.

V. CONCLUSIONS

A new mTCAM with a 5T2R cell structure has been presented. Using two memristors as the nonvolatile storage elements, the mTCAM cell is capable of low-power and high-density CAM integrations and robust write/search operations against power shut-offs. By the presented two-step write scheme which avoids the most power consuming resistance state, the mTCAM offers reliable write operations with reduced static power consumptions. In a 24 mTCAM array, overall functionality and feasibility of the mTCAM operation have been demonstrated for both write and search modes.

REFERENCES

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[8] L. Zheng, S. Shin, and S.-M. Kang, Modular Structure of Compact Model for Memristive Devices, IEEE Trans. Circuits Syst. I, Reg. Papers, 2014, accepted.

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Fig. 7 Transient waveforms in the search mode.

Fig. 6 Transient waveforms in the write mode.

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