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Ajit Prasad (4634888) Serial-Parallel Addition Multiplier 2

TABLE OF CONTENTS

INTRODUCTION 5

.1 VHDL Design Process 5

.2 Report Breakdown 5

MULTIPLIER DESIGN 6

.1 Multiplier Operation 6

.2 Full Adder 7

.3 D Flip-Flop 9

.4 Parallel Load Shift Register 10

.5 Parallel Load Parallel Output Register 11

.6 Serial-Input Parallel Output Register 11

.7 Multiplier Controller 12

.8 Integrated Multiplier 14

DESIGN ENHANCEMENTS 16

.1 32 X 32-Bit Expansion 16

.2 Pipelined Design 16

.3 Synthesized Design 16

CONCLUSION 17

5.0 REFERENCES 18

APPENDIX A: VHDL SOURCE 19

APPENDIX B: SYNTHESIS 29

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LIST OF FIGURES

Figure 1.1 VHDL Design Process.5Figure 2.1 Serial-Parallel Multiplier.. 6Figure 2.2 Multiplier Block Diagram. 7

Figure 2.3 Full Adder K-Map. 8Figure 2.4 Full Adder Schematic.. 8Figure 2.5 Full Adder Simulation.. 8Figure 2.6 Positive Edge Triggered D Flip-Flop With Asynchronous Reset. 9Figure 2.7 D Flip-Flop Simulation. 10Figure 2.8 Parallel Load Shift Register 10Figure 2.9 Parallel Load Shift Register Simulation 10Figure 2.10 Parallel Load Parallel Output Register. 11Figure 2.11 Parallel Load Parallel Output Register Simulation..11Figure 2.12 Serial-Input Parallel Output Register.11Figure 2.13 Serial-Input Parallel Output Register Simulation.12Figure 2.14 Multiplier Controller State Machine... 12

Figure 2.15 Multiplier Controller Schematic.. 13Figure 2.16 Multiplier Controller Simulation.. 14Figure 2.17 8 by 8-Bit Serial-Parallel Multiplier Simulation.14Figure 3.1 32 By 32-Bit Multiplier Simulation..16

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LIST OF TABLES

Table 2.1 Full Adder Truth Table.7Table 2.2 D Flip-Flop Characteristic Table 9Table 2.3 Multiplier Controller State Table.13

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INTRODUCTION

The objective is to design an 8 by 8-bit serial-parallel multiplier using structural VHDL. The multiplierreceives two operands A and B, and calculates the result C. The multiplier will be further expanded to32 by 32-bit multiplication, pipelined, and synthesized.

1.1 VHDL Design Process

The design procedure that will be followed is shown in figure 1.1 below. The target device is the Xilinxxc3s200 FPGA from the Spartan family of devices. This document will illustrate the design processfrom design entry to design implementation of the multiplier.

Figure 1.1 VHDL Design Process [1].

1.2 Document Breakdown

This document breaks the multiplier down into major blocks and designs each block independentlybefore finally assembling the complete multiplier. Each block is coded in purely structural VHDLtherefore it is necessary to conceive the schematic of each block in advance. To ensure that each blockworks as intended it will be simulated and important timing parameters will be extracted.

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2.0 MULTIPLIER DESIGN

The multiplier uses the serial-parallel method of addition to calculate the result of multiplying two 8-bitnumbers as shown in figure 2.1 below. The multiplier receives the two operands A and B and outputsthe result C. Operands A and B are loaded in parallel into 8-bit registers and the result C is shifted intoa 16-bit register. Multiplication begins on the assertion of a START signal and once the calculation is

complete a STOP signal is asserted.

Figure 2.1 Serial-Parallel Multiplier.

2.1 Multiplier Operation

The serial-parallel multiplier is based on the addition of bits in the corresponding column of themultiplication process as shown below. Each column is added in one clock cycle generating thecorresponding bit. The resulting bit is then shifted into output register. Therefore the entire multiplication

process for the 8 by 8-bit multiplier requires 16 clock cycles to complete the calculation.

a1a0x b1b0

------------------------------------a1b0 a0b0

a1b1 a0b1------------------------------------a1b1 (a1b0 + a0b1) a0b0

The block diagram for the multiplier is shown in figure 2.2 below. The first operand, A, is loaded in

parallel and the most significant bit is shifted out during each clock cycle. Operand B is also loaded inparallel and its value is stored in the register for the entire multiplication process. The result C isgenerated by shifting the added bits of each column one by one into the resultant register. Thereforeregister RA is a parallel load shift register, RB is a parallel load parallel output register, and RC is aserial input parallel output register.

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Figure 2.2 Multiplier Block Diagram.

In addition to the three mentioned registers, the multiplier also requires 7 one-bit registers to storeintermediate values such as the carries generated from each addition, and the bits shifted out fromregister RA.

Each component to the multiplier is designed and simulated in the following sections.

* It is important to note that all clocked circuits below use an asynchronous active low reset denoted asResetn, and a clock period of 20 ns.

* For the complete VHDL code for the multiplier and its components refer to Appendix A.

2.2 Full Adder

Part of the partial product sum ripple adder block, the full adder is a combinational circuit that calculatesthe sum of three bits. The resulting sum is output along with the carry. The truth table and K-maps forthe full adder is shown below in table 2.1 and figure 2.3.

Table 2.1 Full Adder Truth Table.

x y z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 10 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

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Figure 2.3 Full Adder K-Map [2].

Therefore the simplified expressions for the full adder are

S = xyz + xyz + xyz + xyzC = xy + xz + yz

Grouping the above expressions appropriately, the full adder can be constructed using two half addersand an OR gate

S = z (xy)C = z(xy + xy) + xy

The implementation of the full adder is therefore

Figure 2.4 Full Adder Schematic [2].

The result of simulating the circuit is shown in figure 2.5 below.

Figure 2.5 Full Adder Simulation.

Although it is not obvious from the schematic, the simulation reveals that the maximum delay of thecircuit is the time it takes for the sum output to be generated (which indicates that the XOR gate has the

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largest delay compared to the AND or OR gates). In this case the delay of the full adder circuit isapproximately 8.196 ns.

2.3 Edge Triggered D Flip-Flop

The positive edge triggered D flip-flop with asynchronous reset is used throughout as the main registertype to store various bit values for the multiplier. The characteristic table for the D flip-flop is shown intable 2.2 below. For this type of register the next output is simply the present input.

Table 2.2 D Flip-Flop Characteristic Table.

D Q(t+1)

0 0 Reset

1 1 Set

An efficient implementation of a D flip-flop uses three SR latches as shown in figure 2.6. Two latches

respond to the CLK and Data inputs. The third SR latch generates the outputs Q and its complement Q[2].

Figure 2.6 Positive Edge Triggered D Flip-Flop With Asynchronous Reset [2].

The result of simulating the circuit is shown in figure 2.7.

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Figure 2.7 D Flip-Flop Simulation.

The delay from the clock input to the output is approximately 11.678 ns.

2.4 Parallel Load Shift Register

The 8-bit parallel load shift register is composed of multiplexers and D flip-flops, refer to figure 2.8. Themultiplexers select whether to load the data or to simply pass the previous register value. If neither theload or shift enable inputs are high the registers keep their current values. If both inputs are high then

the load input takes precedence. Otherwise the circuit either loads or shifts at each clock cycle withrespect to the input that is high. If the circuit is shifting then a 0 is introduced at the leftmost bit.

Figure 2.8 Parallel Load Shift Register.


Figure 2.9 Parallel Load Shift Register Simulation.

Since in either the loading or shifting case data must travel from the input of the LSB multiplexer to theoutput shift bit the delay is equal at approximately 14.891 ns. Knowing from the previous simulation thatthe D flip-flop has a delay of 11.678 ns we can induce that the multiplexer has a delay of approximately3.213 ns.

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2.5 Parallel Load Parallel Output Register

Similar to the previous register, the parallel load parallel output register is composed of multiplexersand D flip-flops. In this case, however, the circuit either loads new data or does not change its output.Refer to figure 2.10 below for the schematic.

Figure 2.10 Parallel Load Parallel Output Register.


Figure 2.11 Parallel Load Parallel Output Register Simulation.

In this circuit a delay is introduced only if new data is loaded. As the simulation shows the delay is

equivalent to that of the previous register RA (14.891 ns) since at each clock cycle data is fed from theinput of the multiplexer to the output of the D flip-flop, which is the same critical path as the previouscircuit.

2.6 Serial-Input Parallel Output Register

The final register circuit in the multiplier is the serial-input parallel output register. This register storesthe result of each succeeding column addition and outputs the result in parallel. The circuit is verysimilar to the other two registers however it is configured to shift a data bit into the MSB and to outputthe register state when it is not shifting data as shown in its 8-bit implementation below.

Figure 2.12 Serial-Input Parallel Output Register.

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Figure 2.13 Serial-Input Parallel Output Register Simulation.

Equivalent to the other two registers RA and RB, the delay for this circuit is 14.891 ns.

2.7 Multiplier Controller

The circuit which allows for the multiplication process to actually take place is the multiplier controller.Upon assertion of the START signal the controller resets the registers, loads the operands, calculatesthe result and asserts the STOP signal. The START signal is only valid in the idle state or the donestate since it is assumed that no calculation would be interrupted for new data. The STOP signal isasserted after 16 clock cycles determined by an internal counter. A finite state machine is used todesign the circuit as shown below.

Figure 2.14 Multiplier Controller State Machine.

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The corresponding simplified state table for the FSM above is shown in table 2.3 below.

State values: Idle = 00, Load = 01, Calculate = 10, and Done = 11.

Table 2.3 Multiplier Controller State Table.

Present State Input Next State Output

X Y Start Counter Resetn* X Y Load Shift Reset_Counter* Stop

x x x x 0 0 0 0 0 0 0

0 0 1 x 1 0 1 0 0 0 0

0 1 x x 1 1 0 1 0 0 0

1 0 x < 1111 1 1 0 0 1 1 0

1 0 x 1111 1 1 1 0 1 1 0

1 1 1 x 1 0 1 0 0 1 1

1 1 0 x 1 1 1 0 0 1 1

*Active low

The resulting simplified equations are (using sum of products)

X+ = Resetn XY + Resetn X Y + Resetn StartX YY+ = Resetn Start XY + Resetn Counter1111 X Y + ResetnX YLoad = Resetn XYShift = Resetn X YStop = Resetn X Y

Reset_Counter = Resetn X Y + ResetnX Y

Which translates to the following schematic

Figure 2.15 Multiplier Controller Schematic.

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Figure 2.16 Multiplier Controller Simulation.

With a clock period of 20 ns, the delay from the first clock signal after assertion of START till theassertion of STOP is approximately 354.580 ns.

2.8 Integrated Multiplier

The complete multiplier can now be implemented by integrating the modules above into a singlefunctional circuit. The result of simulating the circuit is shown in figure 2.18 below.

Figure 2.17 8 by 8-Bit Serial-Parallel Multiplier Simulation.

As can be seen, the delay from the START signal to the assertion of STOP is the same as the multipliercontroller. The overall multiplier circuit delay is approximately 354 ns. This delay is the result of the factthat the calculation requires 16 clock cycles (320 ns) plus the delay of loading the data (14 ns) andfinally the delay to assert the STOP signal (which is one clock cycle after the last shift = 20 ns).

It can be noted that although the critical path of the circuit is

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the Xilinx software automatically optimizes the circuit upon running a timing analysis simulation.Therefore, in the optimized circuit, the serial addition of 7 full adders and one flip-flop occurs in lesstime than the clock period. If the circuit were not optimized a rough approximation for the minimumclock period would be

Tmin = DFFCLKQ + 7 * FA = 14 ns + 7 * 8 ns = 70 ns 14.29 MHz

assuming the AND gate and the setup time for the D flip-flop is negligible.

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3.0 DESIGN ENHANCEMENTS

The following section describes enhancements to the multiplier circuit which include 32 by 32-bitexpansion, pipelining, and synthesizing the design.

3.1 32 by 32-Bit Expansion

To expand the circuit to 32 by 32-bits, the registers RA and RB must each be expanded toaccommodate 32 bits and register RC must be increased to 64 bits. The multiplier controller must alsobe changed to assert STOP after 64 clock cycles. The result of simulating the 32-bit circuit is shownbelow.

Figure 3.1 32 By 32-Bit Multiplier Simulation.

The delay from the assertion of START to STOP is approximately 1310.117 ns. As can be seen, thedelay for this circuit is consistent with the 8-bit circuit such that it is approximately equal to 64 clockcycles (1280 ns) plus the delay of loading the data (14 ns) and finally the delay to assert the STOPsignal (which is one clock cycle after the last shift = 20 ns).

3.2 Pipelined Design

Due to the fact that the circuit operates in an almost entirely serial fashion and that each calculationrequires exactly 16 shifts and 15 additions from the input to the output for an 8 by 8-bit multiplier,pipelining is not possible as a way to increase throughput. After the initial multiplication, where thelatency equals 354 ns for a 20 ns clock period, it is not possible to generate a new multiplication resultat each successive clock cycle. The throughput of the current 8-bit design is

Throughput = 17 clock cycles + Tco = latency = 354 ns.

3.3 Synthesized Design

Since both the 32 by 32-bit and the 8 by 8-bit circuits have the same general repetitive structure onlyone of them, the 32 by 32-bit circuit, was synthesized. The synthesized design optimizes the circuit byreducing the delay of any critical paths, reducing the number of gate levels used in the circuit, andminimizing the number of states in the state machines used. The complete synthesized schematic isshown in Appendix B.

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4.0 CONCLUSION

An 8 by 8-bit serial-parallel multiplier was successfully designed using structural VHDL. The circuit wasbroken down into basic blocks in order to eventually combine them and generate the final multiplierschematic design. Each block and the final design was coded structurally in VHDL and simulated toverify its functionality. Using a clock period of 20 ns the delay for performing a complete multiplication

operation is approximately 354 ns from START to STOP.

The design was further enhanced to support 32 by 32-bit multiplication and it was determined that thismethod of multiplication cannot be pipelined. Finally, the 32 by 32-bit circuit was synthesized.

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5.0 REFERENCES

[1] Xilinx Inc. Xilinx Software Manuals,www.xilinx.com, (Current December 20, 2005).

[2] Mano, M. Morris. Digital Design. Prentice Hall: New Jersey, 2002.
http://www.xilinx.com/http://www.xilinx.com/http://www.xilinx.com/http://www.xilinx.com/

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---------------------------------------------------------------------------------- Module Name: Full_Adder - Full_Adder_Architecture--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity Full_Adder is

Port ( A : in std_logic;B : in std_logic;Cin : in std_logic;S : out std_logic;Cout : out std_logic);

end Full_Adder;

architecture Full_Adder_Architecture of Full_Adder is-- component declarationcomponent OR_2

port(A,B: in std_logic;C : out std_logic);

end component;

component Half_Adder

port(A,B: in std_logic;S,C: out std_logic);end component;

signal S1, C1, C2: std_logic;

-- component specificationfor U1,U2: Half_Adder use entity work.Half_Adder(Half_Adder_Architecture);for U3 : OR_2 use entity work.OR_2(OR_2_Architecture);

begin-- component instantiationU1: Half_Adder port map(A=>A, B=>B, S=>S1, C=>C2);U2: Half_Adder port map(A=>S1, B=>Cin, S=>S, C=>C1);U3: OR_2 port map(A=>C1, B=>C2, C=>Cout);

end Full_Adder_Architecture;

---------------------------------------------------------------------------------- Module Name: D_Flip_Flop - D_Flip_Flop_Architecture--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity D_Flip_Flop isPort ( D : in std_logic;

Resetn : in std_logic;CLK : in std_logic;Q : out std_logic;Qn : out std_logic);

end D_Flip_Flop;

architecture D_Flip_Flop_Architecture of D_Flip_Flop is-- component declarationcomponent NAND_2port(A : in std_logic;

B : in std_logic;C : out std_logic);

end component;

component NAND_3port(A : in std_logic;

B : in std_logic;

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C : in std_logic;D : out std_logic);

end component;

signal Qi,Qni,Ri,Si,Ti,Ui: std_logic;

-- component specification

for U1,U5: NAND_2 use entity work.NAND_2(NAND_2_Architecture);for U2,U3,U4,U6: NAND_3 use entity work.NAND_3(NAND_3_Architecture);

begin-- component instantiationU1: NAND_2 port map (Ti, Si, Ui);U2: NAND_3 port map (Ui, Resetn, CLK, Si);U3: NAND_3 port map (Si, CLK, Ti, Ri);U4: NAND_3 port map (Ri, D, Resetn, Ti);U5: NAND_2 port map (Qni, Si, Qi);U6: NAND_3 port map (Qi, Ri, Resetn, Qni);

Q

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port(A : in std_logic;B : in std_logic;C : out std_logic);

end component;

signal Di: std_logic_vector(7 downto 0);signal Qi: std_logic_vector(6 downto 0);

signal CLKi: std_logic_vector(2 downto 0);

-- component specificationfor U1,U2: Multiplexer_2_To_1 use entity

work.Multiplexer_2_To_1(Multiplexer_2_To_1_Architecture);for U3,U4: D_Flip_Flop use entity work.D_Flip_Flop(D_Flip_Flop_Architecture);for U5,U6: AND_2 use entity work.AND_2(AND_2_Architecture);for U7: OR_2 use entity work.OR_2(OR_2_Architecture);

begin-- component instantiationU1: Multiplexer_2_To_1 port map('0', Data(7), Load_Data, Di(7));U2: Multiplexer_2_To_1 port map(Qi(0), Data(0), Load_Data, Di(0));U3: D_Flip_Flop port map(Di(7), Resetn, CLKi(0), Qi(6), open);U4: D_Flip_Flop port map(Di(0), Resetn, CLKi(0), Shift_Out, open);

U5: AND_2 port map(Load_Data, CLK, CLKi(2));U6: AND_2 port map(Shift_Enable, CLK, CLKi(1));U7: OR_2 port map(CLKi(2), CLKi(1), CLKi(0));

Registers:for i in 5 downto 0 generatebegin

U1: Multiplexer_2_To_1 port map(Qi(i+1), Data(i+1), Load_Data, Di(i+1));U3: D_Flip_Flop port map(Di(i+1), Resetn, CLKi(0), Qi(i), open);

end generate;

end Parallel_Load_Shift_Register_8_Architecture;

---------------------------------------------------------------------------------- Module Name: Parallel_Load_Parallel_Output_Register_8 -

Parallel_Load_Parallel_Output_Register_8_Architecture--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity Parallel_Load_Parallel_Output_Register_8 isPort ( Load_Data : in std_logic;

Data : in std_logic_vector(7 downto 0);Resetn : in std_logic;CLK : in std_logic;Data_Out : out std_logic_vector(7 downto 0));

end Parallel_Load_Parallel_Output_Register_8;

architecture Parallel_Load_Parallel_Output_Register_8_Architecture ofParallel_Load_Parallel_Output_Register_8 is

-- component declarationcomponent Multiplexer_2_To_1port(In0 : in std_logic;In1 : in std_logic;S : in std_logic;O : out std_logic);

end component;

component D_Flip_Flopport(D : in std_logic;

Resetn : in std_logic;

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for U1: Multiplexer_2_To_1 use entitywork.Multiplexer_2_To_1(Multiplexer_2_To_1_Architecture);

for U2: D_Flip_Flop use entity work.D_Flip_Flop(D_Flip_Flop_Architecture);

begin-- component instantiationU1: Multiplexer_2_To_1 port map(Qi(15), Data_In, Shift_Enable, Di(15));

U2: D_Flip_Flop port map(Di(15), Resetn, CLK, Qi(15), open);

Registers:for i in 14 downto 0 generatebegin

U1: Multiplexer_2_To_1 port map(Qi(i), Qi(i+1), Shift_Enable, Di(i));U2: D_Flip_Flop port map(Di(i), Resetn, CLK, Qi(i), open);

end generate;

Data_Out

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port(A : in std_logic;B : in std_logic;C : in std_logic;

D : out std_logic);end component;

component OR_2

port(A : in std_logic;B : in std_logic;C : out std_logic);

end component;

component INVERTERport(A : in std_logic;B : out std_logic);

end component;

component Counter_4port(Count_Enable : in std_logic;

Resetn : in std_logic;CLK : in std_logic;Count_Out : out std_logic_vector(3 downto 0));

end component;

signal Anext, Bnext, A, B, An, Bn, Startn, ResetC, C, Shifti: std_logic;signal RAnB, RABn, RSnAB, RSAnBn, RCABn, RAB: std_logic;signal Counteri: std_logic_vector(3 downto 0);

-- component specificationfor U2,U3,U4,U5: AND_4 use entity work.AND_4(AND_4_Architecture);for U7,U8,U9: AND_3 use entity work.AND_3(AND_3_Architecture);for U10,U11: OR_3 use entity work.OR_3(OR_3_Architecture);for U12: OR_2 use entity work.OR_2(OR_2_Architecture);for U13: INVERTER use entity work.INVERTER(INVERTER_Architecture);for U14,U15: D_Flip_Flop use entity work.D_Flip_Flop(D_Flip_Flop_Architecture);for U16: Counter_4 use entity work.Counter_4(Counter_4_Architecture);

begin -- component instantiationU2: AND_4 port map(Resetn, Startn, A, B, RSnAB);U3: AND_4 port map(Resetn, Start, An, Bn, RSAnBn);U4: AND_4 port map(Counteri(3), Counteri(2), Counteri(1), Counteri(0), C);U5: AND_4 port map(Resetn, C, A, Bn, RCABn);U7: AND_3 port map(Resetn, An, B, RAnB);U8: AND_3 port map(Resetn, A, Bn, RABn);U9: AND_3 port map(Resetn, A, B, RAB);U10: OR_3 port map(RAnB, RABn, RSnAB, Anext);U11: OR_3 port map(RSAnBn, RCABn, RAB, Bnext);U12: OR_2 port map(RABn, RAB, ResetC);U13: INVERTER port map(Start, Startn);U14: D_Flip_Flop port map(Anext, Resetn, CLK, A, An);U15: D_Flip_Flop port map(Bnext, Resetn, CLK, B, Bn);

U16: Counter_4 port map(Shifti, ResetC, CLK, Counteri);

Load

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end Multiplier_Controller_8_8_Architecture;

---------------------------------------------------------------------------------- Module Name: Multiplier_8_8 - Multiplier_8_8_Architecture--------------------------------------------------------------------------------library IEEE;use IEEE.STD_LOGIC_1164.ALL;

entity Multiplier_8_8 isPort ( A : in std_logic_vector(7 downto 0);

B : in std_logic_vector(7 downto 0);Start : in std_logic;Resetn : in std_logic;CLK : in std_logic;C : out std_logic_vector(15 downto 0);Stop : out std_logic;Counter : out std_logic_vector(3 downto 0);Load : out std_logic;Shift : out std_logic;Shift_Line : out std_logic_vector(7 downto 0);Parallel_Line : out std_logic_vector(7 downto 0);State : out std_logic_vector(1 downto 0));

end Multiplier_8_8;

architecture Multiplier_8_8_Architecture of Multiplier_8_8 is-- component declarationcomponent Parallel_Load_Shift_Register_8

port(Load_Data : in std_logic;Shift_Enable : in std_logic;Data : in std_logic_vector(7 downto 0);Resetn : in std_logic;CLK : in std_logic;Shift_Out : out std_logic);

end component;

component Parallel_Load_Parallel_Output_Register_8port(Load_Data : in std_logic;

Data : in std_logic_vector(7 downto 0);Resetn : in std_logic;CLK : in std_logic;Data_Out : out std_logic_vector(7 downto 0));

end component;

component Serial_Input_Parallel_Output_Shift_Register_16port(Data_in : in std_logic;

Shift_Enable : in std_logic;Resetn : in std_logic;CLK : in std_logic;Data_Out : out std_logic_vector(15 downto 0));

end component;

component Multiplier_Controller_8_8

port(Start : in std_logic;CLK : in std_logic;Resetn : in std_logic;Load : out std_logic;Shift : out std_logic;Stop : out std_logic;Counter : out std_logic_vector(3 downto 0);State : out std_logic_vector(1 downto 0));

end component;

component Full_Adder

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port(A : in std_logic;B : in std_logic;Cin : in std_logic;S : out std_logic;Cout : out std_logic);

end component;

component D_Flip_Flopport(D : in std_logic;Resetn : in std_logic;CLK : in std_logic;Q : out std_logic;Qn : out std_logic);

end component;

component AND_2port(A : in std_logic;

B : in std_logic;C : out std_logic);

end component;

component INVERTER

port(A : in std_logic;B : out std_logic);end component;

signal A8,B8,C8: std_logic_vector(7 downto 0);signal A7,B7,C7: std_logic_vector(6 downto 0);signal A14,B14: std_logic_vector(13 downto 0);--signal Statei: std_logic_vector(1 downto 0);--signal Counteri: std_logic_vector(3 downto 0);signal Loadi,Shifti: std_logic;

-- component specificationfor U1: Parallel_Load_Shift_Register_8 use entity

work.Parallel_Load_Shift_Register_8(Parallel_Load_Shift_Register_8_Architecture);for U2: Parallel_Load_Parallel_Output_Register_8 use entity

work.Parallel_Load_Parallel_Output_Register_8(Parallel_Load_Parallel_Output_Register_8_Architecture);for U3: Serial_Input_Parallel_Output_Shift_Register_16 use entity

work.Serial_Input_Parallel_Output_Shift_Register_16(Serial_Input_Parallel_Output_Shift_Register_16_Architecture);

for U4: Multiplier_Controller_8_8 use entitywork.Multiplier_Controller_8_8(Multiplier_Controller_8_8_Architecture);

for U5: Full_Adder use entity work.Full_Adder(Full_Adder_Architecture);for U6: D_Flip_Flop use entity work.D_Flip_Flop(D_Flip_Flop_Architecture);for U7,U8: AND_2 use entity work.AND_2(AND_2_Architecture);for U9: INVERTER use entity work.INVERTER(INVERTER_Architecture);

begin-- component instantiationU1: Parallel_Load_Shift_Register_8 port map(Load_Data => Loadi, Shift_Enable => Shifti,

Data => A, Resetn => Resetn, CLK => CLK, Shift_Out => B8(7));U2: Parallel_Load_Parallel_Output_Register_8 port map(Load_Data => Loadi, Data => B,Resetn => Resetn, CLK => CLK, Data_Out => A8);

U3: Serial_Input_Parallel_Output_Shift_Register_16 port map(Data_in => C8(0),Shift_Enable => Shifti, Resetn => Resetn, CLK => CLK, Data_Out => C);

U4: Multiplier_Controller_8_8 port map(Start => Start, CLK => CLK, Resetn => Resetn,Load => Loadi, Shift => Shifti, Stop => Stop, Counter => Counter, State => State);

U5: Full_Adder port map(A => C8(7), B => A7(6), Cin => C7(6), S => C8(6), Cout =>B7(6));

U6: D_Flip_Flop port map(D => B8(7), Resetn => A14(13), CLK => CLK, Q => B8(6), Qn =>open);

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U7: AND_2 port map(A => A8(7), B => B8(7), C => C8(7));U8: AND_2 port map(A => Resetn, B => B14(13), C => A14(13));U9: INVERTER port map(A => Loadi, B => B14(13));

Sum_Carry_Chain:for i in 5 downto 0 generate

U5: Full_Adder port map(A => C8(i+1), B => A7(i), Cin => C7(i), S => C8(i), Cout

=> B7(i)); U6: D_Flip_Flop port map(D => B8(i+1), Resetn => A14(i+7), CLK => CLK, Q =>B8(i), Qn => open);

end generate;

Serial_Parallel_Chain:for i in 6 downto 0 generate

U6: D_Flip_Flop port map(D => B7(i), Resetn => A14(i), CLK => CLK, Q => C7(i), Qn=> open);

U7: AND_2 port map(A => A8(i), B => B8(i), C => A7(i));end generate;

Reset_OR_Initialize:for i in 12 downto 0 generate

U8: AND_2 port map(A => Resetn, B => B14(i), C => A14(i));

U9: INVERTER port map(A => Loadi, B => B14(i));end generate;

Load

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APPENDIX B: 32 BY 32-BIT MULTIPLIER SYNTHESIS RESULTS

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Coen 6501 a Prasad