Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

NITTTR, Chandigarh EDIT -2015 96

Codec Scheme for Power Optimization inVLSI Interconnects

1Dhriti Duggal,2Rajnish Sharma1,2Chitkara University, Himachal Pradesh, India

1dhriti.duggal@chitkarauniversity.edu.in, 2rajnish.sharma@chitkarauniversity.edu.in

Abstract— This paper presents a codec scheme for optimizingpower in VLSI Interconnects. It is based on the traditionalbus encoding method which is considered to be one of themost effective ways of power and delay reduction. The workdone aims at optimizing power by designing the scheme usingFull-Custom design approach. The model has been designedand implemented using Cadence Virtuoso Analog DesignSuite in 0.18µm CMOS technology. Power has been computedfor different possible combinations of input data. Delay hasbeen reckoned for the maximum power consuming inputcombination. Layout editor has been used to generate thephysical description of the circuit. The 4 bit input datacombination consuming maximum dynamic power of 6.44µWand propagation delay of 722.7ps is “1000” with previouslytransmitted 4 bit data being “0111”. A significant powerreduction of 38.89% has been observed by designing thescheme using Full-Custom approach as compared to theconventional Semi-Custom approach of design.

Keywords— Interconnects, Couplings, Power Dissipation,Layout Implementation.

I. INTRODUCTIONFor System on Chip (SOC) and Network on Chip (NOC)designs in Deep Submicron era, interconnects play animportant role in the overall performance of the chip. Theyare used to distribute clock and other signals and to providepower/ground to and among the various circuits/systemsfunctions on the chip [1, 2]. Interconnects consume around44% of the total chip area and hence it becomes veryimportant to estimate and minimize the power consumedby them. Coupling Capacitance located between the wireand its adjacent wires is important to analyze because itslows down the signal. It can become the major componentof delay if the switching and coupling activities betweenthe group wires are not minimized. Further it may also leadto Crosstalk and Signal Integrity related issues, which inthe worst of the cases may lead to the complete circuitmalfunction if not modeled properly [3-6]. There arevarious methods to reduce the crosstalk, powerconsumption and propagation delay but bus encodingmethod is one of the most efficient methods [3]. It reducespower consumption and crosstalk by bringing reduction inthe switching activity that is by reducing the number ofpower consuming voltage transitions experienced by theoutput capacitance/clock cycle.Power consumption sources in digital CMOS circuits arebroadly classified into three main categories: static, short-circuit and dynamic power dissipation [7]. Dynamic powerdissipation is one of the most dominant sources of powerdissipation in CMOS circuits which cannot be ignored.Thus, to optimize power in any design successfully,dynamic power has to be estimated and minimizedseparately. The dissipated power is expressed as:

Pdiss = α* VDD2* fCLK* CL (1)

Where, CL is the load capacitance, VDD is supply voltage,fCLK is the clock frequency and α is the average activityfactor or the switching factor whose value lies between 0and 1. This paper focuses on bus encoding method forreducing power dissipation of VLSI Interconnects byreducing the switching activity.The rest of the paper is organized as follows: Section IIdiscusses the types of couplings in interconnects. SectionIII describes the implemented codec scheme. Results havebeen discussed in Section IV and Section V concludes thepaper.

II. COUPLINGS IN INTERCONNECTSThe coupling between groups of three wires is classifiedinto five types depending upon the nature of transitions ofsignals in the wires that are Type-0, Type-1, Type-2, Type-3 and Type-4 as shown in Table 1 [3-6].

Table I. 3 bit bus couplingsTYPE-0 TYPE-1 TYPE-2 TYPE-3 TYPE-4

˗ ˗ ˗ ˗ ˗↑ ˗ ↑ ˗ ˗ ↑↓ ↑↓↑↑↑↑ ˗↑↑ ↑↑ ˗ ˗ ↓↑ ↓↑↓↓↓↓ ↑˗ ˗ ↑ ˗ ↓ ↑↓ ˗

↑↑˗ ↑↑↓ ↓↑ ˗˗ ˗↓ ↑↓↓˗↓↓ ˗ ↓ ˗˗ ˗↓ ↓ ˗ ↓↓↓ ˗ ↓ ˗ ↑

↓↓↑↓↑↑

↑: transition from 0 to 1; ↓: transition from 1 to 0; ˗: no transitionType-0 coupling occurs when all the 3 bit wires undergothe same transition [1-2].Type-1 coupling occurs whenthere is transition in one or maximum two wires (includingthe centre one) while the third wire remains quite [1-2].Type-2 coupling occurs when the centre wire is in theopposite state transition with one of its adjacent wireswhile the other wire undergoes the same state transition asthe centre wire [1-2]. Type-3 coupling occurs when thecentre wire undergoes the opposite state transition with oneof the two wires while the other wires are quite[1-2].Type-4 coupling occurs when all the three wire transitions in theopposite state with respect to each other[1-2].

III. IMPLEMENTED CODEC SCHEMEFig 1 shows the block diagram of the implemented codecscheme. Transition Detector compares the present 4 bitinput data with the previously transmitted 4 bit data.Output of the transition detector acts as an input to thecoupling detectors which help in detecting crosstalkcouplings. XOR Stacks are used at both the encoder anddecoder side to transmit and receive data.

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

97 NITTTR, Chandigarh EDIT-2015

Fig. 1 Block Diagram of the implemented codec scheme

Layout of different blocks of the implemented codecscheme are shown in the figures below:Fig 2 shows the layout of the transition detector which actsas a comparator and is used to compare the 4 bit presentinput data with previously transmitted 4 bit data on thesame data lines. The combination of first four NOT andAND gates are used to detect ‘low’ to ‘high’ transitions onthe data bus whereas the combination of last four NOT andAND gates are used to detect ‘high’ to ‘low’ transitions onthe data bus.

Fig. 2 Layout of Transition Detector

8 bit output of the transition detector acts as an input to thecoupling detectors where type-0, type-1, type-2, type-3 andtype-4 coupling detector individually are used to detect theoccurrence of any of the types of type-0, type-1,type-2,type-3 and type-4 crosstalk couplings. Further itgenerates a 1 bit output signal. If any of the output signal is‘high’ it indicates the occurrence of that particularcrosstalk coupling else not. Fig 3 shows the layout of type-2 coupling detector which covers the maximum number ofcoupling cases as explained in table I. Similar ways,layouts of all other coupling detectors have been designed.

Fig. 3 Layout of Type-2 Coupling Detector

1 bit output of the individual coupling detectors acts as aninput to the 5 input OR gate which is used to generate thedesired 1 bit control signal as shown in fig 4. If its outputis ‘high’ then the inverted data is sent to the output sideusing XOR stack 1 and if its output is ‘low’ then theoriginal data is sent to the output side using XOR stack 1.

Fig. 4 Layout of 5 Input OR gate

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

NITTTR, Chandigarh EDIT -2015 98

Fig 5 shows XOR Stack 1 which is used to transmit thedata to the decoder end according to the implemented logicand the status of the control signal. A similar type of XORstack is used at the output end to decode the receivedinformation depending upon the implemented logic and thestatus of the control signal

Fig. 5 Layout of XOR Stack 1

IV. RESULTS AND DISCUSSIONThe design has been implemented using Cadence VirtuosoAnalog Design Suite in 0.18µm technology. Virtuosolayout editor has been used to generate the physicaldescription of the circuit. Table II highlights the total preand post layout power consumption of the implementedcodec scheme individually for all 16 possible combinationsof present and previous data. Power and delay results forthe maximum power consuming present and previous dataare shown in table III.

Table II. Total power resultsPresentdata

PreviousData

Pre-layouttotal power

consumption(mW)

Post-layout totalpower consumption

(mW)

0000 1111 2.705 3.1900001 0000 1.521 1.5900010 0001 1.851 2.0720011 0010 1.521 1.5900100 0011 2.542 2.9290101 0100 1.521 1.5900110 0101 1.849 2.0820111 0110 1.519 1.5921000 0111 2.937 3.5081001 1000 1.521 1.5921010 1001 1.849 2.0821011 1010 1.521 1.592

1100 1011 2.540 2.9171101 1100 1.521 1.5821110 1101 1.848 2.0741111 1110 1.521 1.586

Table III. Power and delay results for the worst combinationwhen present and previous data is “1000” and “0111”

Pre layout Post layoutTotal power (mW) 2.937 3.508

Dynamic power (µW) 5.40 6.44Total delay (ps) 402.4 722.7

Table IV shows the comparison of present work withpreviously done work in terms of power consumption andpropagation delay.

TABLE IV. Comparison of present work with previous work

Parameter [1] Present WorkPower (µW) 10.54 6.44Propagation Delay(ps)

296 722.7

There is a significant improvement of 38.89% in powerconsumption in the work done as compared to the previouswork. A codec scheme has been presented which focusesmainly on reducing the switching and coupling activity soas to reduce the power consumption. Modeling thecomplete scheme using Full-Custom design approach hasbeen the focus point instead of using the traditional Semi-Custom approach of design. Full-Custom designmethodology gives the liberty to the designer to specify thelayout of each and every transistor and the interconnectionsbetween them. Whereas, in case of Semi-Custom designingpre defined and pre characterized libraries are used, notgiving the privilege of complete customization to thedesigner. Though there has been improvement in powerbut increase in delay has been observed in the present workas previous work focused the research on couplingsassociated with either RC or RLC modeled interconnects.In the present work, stress has been laid upon both of themequally. The scheme has been designed for all types ofcrosstalk couplings rather than focusing on only inductiveor resistive couplings in particular leading to a trade-offbetween power and delay.

V. CONCLUSIONCodec Scheme implementation for optimizing power inVLSI Interconnects has been presented. The pre and postlayout results have been compared. Also the comparison ofthe present design has been done with the previously donework in terms of power and propagation delay and asignificant improvement in dynamic power consumptionhas been observed.

REFERENCES[1]Deepika Agarwal, G. Nagendra Babu, B.K. Kaushik, S.K. Manhas,

“Reduction of Crosstalk in RC Modeled Interconnects with LowPower Encoder” Emerging Trends in Networks and ComputerCommunications (ETNCC),IEEE International Conference, pp. 115-120, 2011.

[2]G. Nagendra Babu, Deepika Agarwal, B.K. Kaushik, S.K. Manhas,Brijesh Kumar “Crosstalk avoidance in RLC modelled interconnectsusing low encoder,” Recent advances in Intelligent ComputationalSystems (RAICS),pp 921-924, 2011.

Int. Journal of Electrical & Electronics Engg. Vol. 2, Spl. Issue 1 (2015) e-ISSN: 1694-2310 | p-ISSN: 1694-2426

99 NITTTR, Chandigarh EDIT-2015

[3]Chih-Peng Fan and Chia-Hao Fang, “Efficient RC Low-power busencoding methods for Crosstalk reduction,” Integration VLSI Journal,Elsevier, vol. 44, no. 1, pp. 75-86, Jan. 2011.

[4]M.R Stan, and W.P. Burleson, “Bus-Invert Coding for Low-powerI/O,” IEEE Trans. On Very Large Scale Integration System, vol.3, no.1, pp. 49-58, March 1995.

[5]S.K. Verma and B.K. Kaushik, “A Bus Encoding Method for Crosstalkand Power Reduction in RC Coupled VLSI Interconnects”International Journal of VLSI design & Communication Systems(VLSICS) Vol.3, No.2, April 2012, pp.29-39.

[6]S.K. Verma and B.K. Kaushik ,“Crosstalk and Power Reduction UsingBus Encoding in RC Coupled VLSI Interconnects” Third InternationalConference on Emerging Trends in Engineering and Technology(ICETET), IEEE computer society, November 2010, pp.735-740.

[7]Jan M. Rabaey, Anantha Chandrakasan, and Borivoje Nikolic,“Digital Integrated Circuits,” 2nd Edition, PrenticeHall Publication,2003.