CMOS periphery

Ivan Peric, Monolithic Detectors for Strip Region 1

CMOS periphery


CMOS periphery: detector types

• Embedded pixel sensor• With readout cells on the periphery• With readout cells in the active region• With continuous readout• With trigger readout• Segmented strip detector with hit-buffer based multiplexing• With/without digital z encoding• Segmented strip detector with lossy constant-delay-multiplexing (readout latency only 80ns)• With/without digital z encoding


HVCMOS sensor types

N-Well

N-Well

CMOS CMOS

N-Well N-Well

Variant 1PMOS not isolated

Variant 2PMOS isolated with a deep P-well

Type A – smart diode Type B – HVMAPS

CMOS N-Well

N-Well

CMOS

PMOS must be isolated with a deep P-well


Readout types: in-pixel hit processing (embedded pixel sensor)

RAM/ROMHit flag Priority scan logic

Time stamp Data bus

Read

RowAddr + TS

One RO cell/pixel

Shift register

in-pixel hit processingMatrix size M x NOutput data width ln(N)=n+TSPeriphery ~ 1% - 1.5%

Readout cell function – time stamp is stored when hit arrivesHit data are stored until the readoutPriority logic controls the readout orderRO cell size in 0.18um ~ 7um x 40um(with comparator and thr-tune DAC)Without comparator: 7um x 20umExample: Pixel size 80um x 320umChip size: ~ 2cm x 2cmNumber of pixels: 256 x 64Size of periphery with comparators: 2cm x 224um (1.12%)Size of periphery without comparators: 2cm x 112um (0.6%)

Comparatorand Thr tune DAC

Pixel contains a charge sensitive amplifier and optionally a discriminator with a threshold tune DAC

CSAComparator

Concept: Every pixel has its own readout cell, placed on the chip periphery


Readout types: in-pixel hit processing with trigger (embedded s.)

RAM/ROMHit flag

Priority scan logic

Time stampData bus

Read

RowAddr + TS

One RO cell/pixel

Shift register

In-Pixel hit processingMatrix size M x NOutput width n+TSPeriphery ~ 1.5%

Delayed TS and trigger

Readout cell function – time stamp is stored when hit arrivesThe stored time stamp is compared with the current time stampIf trigger arrives with the correct latency, the triggered hit flag is set Priority logic controls the readout orderEstimated cell size in 0.18um without comparator ~ 7um x 40umExample: Pixel size 80um x 320umChip size: ~ 2cm x 2cmNumber of pixels: 256 x 64Size of periphery without comparator: 2cm x 224um (1.12%)

Triggered hit flag

Pixel contains a charge sensitive amplifier and a discriminator with threshold tune DAC

CSAComparator

Concept: Every pixel has its own readout cell, placed on the chip periphery


In-pixel hit processing with the RO placed in active area

RAM/ROMHit flag

Priority scan logic

Time stampData bus

ReadDelayed TS and trigger

The implementation of the whole readout in active region requires deep P-WellNo digital periphery required

Triggered hit flag

N-Well

CSA Comparator

Concept: Every pixel has its own readout cell, placed in the pixel itself (active area)

Smart diode implementation


In-pixel hit processing with the RO placed in active area

N-Well

N-Well

N-Well

HVMAPS implementation


Segmented strip detector with hit-buffer based multiplexing













1

Segmented strip Output width 1 + TSSmall periphery (<1%)Pad-area dominates

Shift register

CSAComparator

HitPixel

synch25ns clock

FIFO

Shift reg.

TS

Hit TS

ffsr

Ck

hit

hit

RAMFull flag

Write prio. logic

DataInHit

EoC buffer

Read prio. logic



n

Segmented strip with digital row encodingOutput width n+ TSSmall periphery (<1%)Pad-area dominatesScrambled address when more than a hit/column

A few cells/column

Shift register

CSAComparator

Address ROM

Address Hit

synch25ns clock

FIFO

Shift reg.

TS

Address Hit TS

ffsr

Ck

Address

Sync Address, hit

hit RAM

RAMFull flag

Write prio. logic

DataIn

Data bus

EoC buffer

HitRead prio. logic

Pixel

EoC buffer

Read


Scheme that copes with hit multiplicity

Segmented strip with digital row encodingOutput width n+ TSSmall periphery (<1%)Pad-area dominatesScrambled address when more than two hits/column

Shift register

CSAComparator

AddressDown HitPixel

AddressUp

n n n n


Column mapping

Multiple hits/column unlikely Multiple hits/column possible due to charge sharing


Segmented strip detector with lossy constant-delay-multiplexing

A C DB

Output 1

Output 2



A C DB

Output 1

Output 2



A C DB

Output 1

Output 2

0 1 2



A C DB

Output 1

Output 2

0 1 2

A

B



A C DB

Output 1

Output 2



A C DB

Output 1

Output 2



A C DB

Output 1

Output 2

0 10



A C DB

Output 1

Output 2

0 10

C



A C DB

Output 1

Output 2



A C DB

Output 1

Output 2



A C DB

Output 1

Output 2

0 1 2



A C DB

Output 1

Output 2

0 1 2

A

D



A C DB

Output 1

Output 2



1

Segmented strip Output width 8x8Constant delaySmall periphery (<1%)Pad-area dominatesHit loss when more than 8 hits/BC

8x8

Pipelinestructure

f a

f a

f

a

f

f

a

a f

f f

ff m1

FF

inc

Addr3-bit adder

en

chan

in8

8 8

8333

3

3

3

m

Addr

enin8

inc

1

Demux with en

Chan0-14

Chan15

Chan16-30

ROMFFs:2304



n

Segmented strip with binary row encodingOutput width 8x(8+n)Constant delaySmall periphery (<1%)Pad-area dominatesHit loss when more than 8 hits/BC

8x8

Pipelinestructure

f a

f a

f

a

f

f

a

a f

f f

ff1inc

en

chan 8 8

8333

3

3

3

eninc

1

Chan0-14

Chan15

Chan16-30

fn f f

addr

n nn

nin

in

fn f fn nn

in

FFs:6912


Segmented strip detector with analog row encodingCSA

Comparator

Analog address-encoding

Segmented strip with analog row encodingAnalog z-encodingOutput width mNo periphery

Documents

CMOS periphery