Ch1. VLSI System Design Methodology

7/28/2019 Ch1. VLSI System Design Methodology

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VLSI System Design

Methodology


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Contents

Structure Design Strategy

System on chip design

Sea of gate & Gate array design

Standard cell design

Full-custom mask design


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Structure Design Strategy


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System on chip design


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System on Chip Design options:

Programmable logic and structures,

Programmable interconnect, Programmable

gate arrays

Sea of gate and gate array design

Standard cell design


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Programmable Logic

In CMOS, the spectrum of programmable

devices into 3 areas:

Chips with programmable logic structures

Chips with programmable interconnect

Chips with reprogrammable gate arrays


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The cmos system designer should be familiarwith these options for two reasons:

First, it allows the designer to competently assess aparticular system requirement for an IC andrecommend a solution, given the system

complexity, the speed of operation, cost goals,time-to-market goals, and any other top-levelconcerns.

Second, it familiarizes the IC system designer withmethods of making any chip designreprogrammable and hence more useful and ofwider-spread use.


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Programmable Logic Structures


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The programming of PALs is done in three

main ways:

Fusible links

UV-erasable EPROM

EEPROM


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Fusible links

Fusible links use metals such as

Platinum silicide

Titanium tungsten to form the links

These links are blown when current exceeds in the

fuse.

This is accomplished by using higher voltage than

normal.Programming is a one time.


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UV-erasable EPROM

UV-erasable memories typically use a Floating Gate.

The floating gate is interposed between the regular MOStransistor and the channel.

To program the cell, voltage around 13-14volts is applied tothe control gate. While drain of the transistor to beprogrammed is held at around 12volts.

Programming may be completed numerous times.

The chips are usually housed in glass-lidded packages to allowillumination by UV light.


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EEPROM

EEPROM technology allows the electrical

programming and erasure of CMOS ROM cells.

Two transistors are typically used in a ROM

cell.

Access transistor

Programmed transistor


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A two-poly sandwich is again used in theprogrammed transistor with the control gateon the top.

Series access transistor allows programming ofcells.

EEPROM has a testability advantage overfused technologies.


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Programmable interconnect.

In PAL, the device is programmed by changing the

characteristics of switching element.

An alternative would be to program the routing.

Commercially, programmable routing approaches are

represented by products from Actel

QuickLogic


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Antifuse

Based on an elementcalled a PLICE orantifuse.

Normally high resistance

(> 100 M)

on application ofappropriate voltage,

the antifuse is changedpermanently to a lowresistance structure

(200-500)


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Antifuse-based Actel FPGAs

I/O Buffers

Program/Test/Diagnostics

I/O Buffers

I/O

Buffers

I/O

Buffers

Vertical routes

Rows of logic modules

Routing channels

Standard-cell likefloorplan


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Interconnection Fabric

Logic Modul

Horizontal

Track

Vertical

Track

Anti-fuse

Actel Interconnect


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Pass transistors are used to connect wiresegments for the purpose of programming.

These may be bypassed by antifuses if thelinks are required permanently.

N1,N2,N3,N4,N9,N10,N11 are column access

transistors. N5,N6,N7,N8 are row access transistors.

To program antifuse all transistors in series are

turned on at end is connected toprogramming voltage and ground supply.

When the programming sequence is applied,the antifuse so selected is blown.


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Basic Block in Actel FPGA


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It consists 3 2-input muxes, nor gate.

Implements 2 and 3 input logic functions and

also 4 input functions.

A latch also implemented using one logic

element.


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General Architecture of Xilinx FPGAs


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RAM-based FPGAs

CLB CLB

CLBCLB

switching matrix

Horizontalroutingchannel

Vertical routing channel

Interconnect point

[Adapted from http://infopad.eecs.berkeley.edu/~icdesign/. Copyright 1996 UCB]


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Basic Block (CLB) in RAM-based FPGAs

R

Q1D

CE

R

Q2D

CE

F

G

F

G

F

G

R

Din

Clock

CE

F

G

A

B/Q1/Q2

C/Q1/Q2D

A

B/Q1/Q2

C/Q1/Q2

D

E

Combinational logic Storage elements

Any function of up to

4 variables

Any function of up to

4 variables

Courtesy of Xilinx



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Programmable Logic: FPGA


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Xilinx 4000 Interconnect


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Switch Matrix


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Sea of Gates Uninterrupted lines of Pand N diffusions

Metal interconnects over non used transistors Lines are interrupted connecting PMOS to Vdd and NMOS to Vss

2-5 masks till three levels of metals, vias, interconnects


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Gate Array - Sea-of-gates

rows of

cells

routing

channel

uncommitted

VDD

GND

polysilicon

metal

possible

contact

In1 In2 In3 In4

Out

Uncommited

Cell

CommittedCell

(4-input NOR)


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Sea-of-gate Primitive Cells

NMOS

PMOS

Oxide-isolation

PMOS

NMOS

NMOS

Using oxide-isolation Using gate-isolation


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Standard Cell Design

SSI(nand,nor,xor,aoi,oai,inverters,buffers,regs)

MSI(decoders,encoders,adders,comparators)

Datapath(alus,adders,shifters)

Memories(RAM,ROM,CAM)

System-level bloks (processors, serial interfaces, etc.)


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Standard Cell Libraries

Typically contain a few hundred cells inverters, NAND gates, NOR gates, complex AOI, OAI gates, D-latches,

and flip-flops

Each gate type can have multiple implementations to provide adequate drivingcapability for different fanouts

e.g the inverter gate can have standard size transistors, double sizetransistors, and quadruple size transistors

the chip designer can choose the proper size to achieve high circuitspeed and layout density

Cells characterized for various metrics, such as

delay time vs. load capacitance Circuit, timing, and fault simulation models

cell data for place-and-route

mask data

Cells designed such that they can be abutted to form rows


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Standard Cell Based Design

FunctionalModule(RAM,multiplier,)

RowsofCells

Logic Cell

RoutingChannel

Feedthrough Cell

Routing channel

requirements are

reduced by presence

of more interconnect

layers



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Documents

Ch1. VLSI System Design Methodology