Ch1 Introd July2014

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    EE141

    Digital Integrated Circuits2nd Introduction1

    Trends in VLSI

    July2014

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    EE141

    Digital Integrated Circuits2nd Introduction2

    Digital Integrated Circuits

    Introduction: Issues in digital design The CMOS inverter Combinational logic structures

    Sequential logic gates Design methodologies Interconnect: R, L and C TimingArithmetic building blocks Memories and array structures

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    EE141

    Digital Integrated Circuits2nd Introduction3

    Introduction

    Why is designingdigital ICs different

    today than it wasbefore?

    Will it change infuture?

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    Digital Integrated Circuits2nd Introduction4

    ENIAC - The first electronic computer (1946)

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    Digital Integrated Circuits2nd Introduction5

    The Transistor Revolution

    First transistor

    Bell Labs, 1948

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    Digital Integrated Circuits2nd Introduction6

    The First Integrated Circuits

    Bipolar logic

    1960s

    ECL 3-input Gate

    Motorola 1966

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    Intel 4004 Micro-Processor

    19711000 transistors1 MHz operation

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    Intel Pentium (IV) microprocessor

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    Moores Law

    In 1965, Gordon Moore noted that thenumber of transistors on a chip doubled

    every 18 to 24 months.He made a prediction thatsemiconductor technology will double its

    effectiveness every 18 months

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    Evolution in Complexity

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    Transistor Counts

    1,000,000

    100,000

    10,000

    1,000

    10

    100

    1

    1975 1980 1985 1990 1995 2000 2005 2010

    8086

    80286i386

    i486Pentium

    PentiumPro

    K1 Billion

    Transistors

    Source: Intel

    Projected

    Pentium IIPentium III

    Courtesy, Intel

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    Moores law in Microprocessors

    40048008

    80808085 8086

    286386

    486Pentium proc

    P6

    0.001

    0.01

    0.1

    1

    10

    100

    1000

    1970 1980 1990 2000 2010

    Year

    Transistors(MT)

    2X growth in 1.96 years!

    Transistors on Lead Microprocessors double every 2 years

    Courtesy, Intel

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    Die Size Growth

    40048008

    80808085

    8086286386

    486Pentium procP6

    1

    10

    100

    1970 1980 1990 2000 2010

    Year

    Dies

    ize(mm)

    ~7% growth per year

    ~2X growth in 10 years

    Die size grows by 14% to satisfy Moores Law

    Courtesy, Intel

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    Frequency

    P6

    Pentium proc486

    38628680868085

    8080

    80084004

    0.1

    1

    10

    100

    1000

    10000

    1970 1980 1990 2000 2010Year

    Freque

    ncy(Mhz)

    Lead Microprocessors frequency doubles every 2 years

    Doubles every2 years

    Courtesy, Intel

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    Power will be a major problem

    5KW18KW

    1.5KW

    500W

    40048008

    80808085

    8086286386486

    Pentium proc

    0.1

    1

    10

    100

    1000

    10000

    100000

    1971 1974 1978 1985 1992 2000 2004 2008Year

    Pow

    er(Watts)

    Power delivery and dissipation will be prohibitive

    Courtesy, Intel

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    Power density

    40048008

    80808085

    8086

    286386

    486Pentium proc

    P6

    1

    10

    100

    1000

    10000

    1970 1980 1990 2000 2010Year

    PowerDe

    nsity(W/cm2)

    Hot Plate

    Nuclear

    Reactor

    RocketNozzle

    Power density too high to keep junctions at low temp

    Courtesy, Intel

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    Not Only Microprocessors

    Digital Cellular Market

    (Phones Shipped)

    1996 1997 1998 1999 2000

    Units 48M 86M 162M 260M 435M

    Analog

    Baseband

    Digital Baseband

    (DSP + MCU)

    Power

    Management

    Small

    Signal RFPower

    RF

    (data from Texas Instruments)

    CellPhone

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    System design cycle

    20

    Arithmetic

    operation

    Numbersystem

    Algorithm

    Architecture

    Floor-plan

    Logic gates

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    Transistor modeling Characterized by figure of merit depends on:

    a) Performance

    b) Level of integration

    c) Cost

    Influenced by:

    Minimum feature size No. of Gates

    Power dissipation

    Gate delay

    Die size Testing

    Reliability

    Production cost21

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    Moores First Law

    22

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    Speed/Power Performance

    23

    Th I t t d Ci it (IC) E

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    The Integrated Circuits(IC) Era

    Microelectronics Evolution

    24

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    Productivity Trends

    1

    10

    100

    1,000

    10,000

    100,000

    1,000,000

    10,000,000

    2003

    1981

    1983

    1985

    1987

    1989

    1991

    1993

    1995

    1997

    1999

    2001

    2005

    2007

    2009

    10

    100

    1,000

    10,000

    100,000

    1,000,000

    10,000,000

    100,000,000Logic Tr./Chip

    Tr./Staff Month.

    xxx

    xxx

    x

    21%/Yr. compoundProductivity growth rate

    x

    58%/Yr. compoundedComplexity growth rate

    10,000

    1,000

    100

    10

    1

    0.1

    0.01

    0.001

    Log

    icTr

    ans

    istorper

    Chip(M

    )

    0.01

    0.1

    1

    10

    100

    1,000

    10,000

    100,000

    Pro

    duc

    tiv

    ity

    (K)Trans./

    Staff-

    Mo.

    Source: Sematech

    Complexity outpaces design productivity

    C

    omp

    lex

    ity

    Courtesy, ITRS Roadmap

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    Why Scaling?

    Technology shrinks by 0.7/generation With every generation can integrate 2x more

    functions per chip; chip cost does not increasesignificantly

    Cost of a function decreases by 2x But

    How to design chips with more and more functions?

    Design engineering population does not double everytwo years

    Hence, a need for more efficient design methods Exploit different levels of abstraction

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    Design Abstraction Levels

    n+n+

    S

    GD

    +

    DEVICE

    CIRCUIT

    GATE

    MODULE

    SYSTEM

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    Design Metrics

    How to evaluate performance of adigital circuit (gate, block, )? Cost

    Reliability Scalability

    Speed (delay, operating frequency)

    Power dissipation

    Energy to perform a function

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    Cost of Integrated Circuits

    NRE (non-recurrent engineering) costs

    design time and effort, mask generation

    one-time cost factor

    Recurrent costs

    silicon processing, packaging, test

    proportional to volume

    proportional to chip area

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    Die Cost

    Single die

    Wafer

    From http://www.amd.com

    Going up to 12 (30cm)

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    Cost per Transistor

    0.0000001

    0.000001

    0.00001

    0.0001

    0.001

    0.01

    0.1

    1

    1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

    cost:-per-transistor

    Fabrication capital cost per transistor (Moores law)

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    Yield

    %100

    per waferchipsofnumberTotal

    per waferchipsgoodofNo.Y

    yieldDieper waferDies

    costWafercostDie

    areadie2

    diameterwafer

    areadie

    diameter/2wafer

    per waferDies

    2

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    Defects

    areadieareaunitperdefects1yielddie

    is approximately 3

    4area)(diecostdie f

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    Some Examples (1994)

    Chip Metallayers

    Linewidth

    Wafercost

    Def./cm2

    Areamm2

    Dies/wafer

    Yield Diecost

    386DX 2 0.90 $900 1.0 43 360 71% $4

    486 DX2 3 0.80 $1200 1.0 81 181 54% $12

    Power PC601

    4 0.80 $1700 1.3 121 115 28% $53

    HP PA 7100 3 0.80 $1300 1.0 196 66 27% $73

    DEC Alpha 3 0.70 $1500 1.2 234 53 19% $149

    Super Sparc 3 0.70 $1700 1.6 256 48 13% $272

    Pentium 3 0.80 $1500 1.5 296 40 9% $417

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    Di it l I t t d Ci it 2 d I t d ti39

    Summary

    Digital integrated circuits have come a longway and still have quite some potential left forthe coming decades

    Some interesting challenges ahead

    Getting a clear perspective on the challenges andpotential solutions is the purpose of this book

    Understanding the design metrics that governdigital design is crucial

    Cost, reliability, speed, power and energydissipation