CASES 2002 Intl Conference on Compilers, Architectures and Synthesis for Embedded Systems Embedded Architectures: Configurable, Re-configurable, or what?

CASES 2002Int’l Conference on Compilers,

Architectures and Synthesisfor Embedded Systems

Embedded Architectures: Configurable,

Re-configurable, or what?

(position statements)

Reiner Hartenstein

University ofKaiserslautern

viewgraph downloading, for a link see:

http://hartenstein.de

Grenoble, FranceOctober 8 - 11 2002

Pierre Paulin, STMicro (moderator); Henk Corporaal, IMEC; Reiner Hartenstein, University of Kaiserslautern; Oz Levia,

Improv Systems; Marco Pavesi, Italtel; Chris Rowen, Tensilica.

Thursday, Oct 10, session 5, 4.00 - 5.00 p.m.

Re-configurable !

© 2002, [email protected] http://hartenstein.de2

University of Kaiserslautern

Xputer Lab„Re-configurable Hardware“ ??

„Re-configurable Hardware“ ??

this „Hardware“ is not hard !

We need a concise terminology: a consensus is on the way

it‘s Morphware

Terminology has been highly confusing



Xputer LabTerminology: DPU versus CPU ...

• DPU: data path unit• DPA: DPU array• GA: gate array• rDPU: reconfigurable DPU• rDPA: reconfigurable DPA• rGA: reconfigurable GA

• DPU is no CPU: there is nothing central - like in a DPA

DPUDPU

DPUinstructionsequencer

CPU

DPA(r)

(r)



Xputer LabDigital System Platforms

clearly distinguished

platformprogram source

running on itmachine paradigm

hardware (not programmable)

nonemorphwar

e

fine grain

rGA (FPGA)configware

coarse grain

rDPU, rDPAreconfigurable data stream processor

flowware & configware anti

machinedata stream processor (hardwired) flowware

instruction stream processor softwarevon Neumann machine



Xputer Labflowware defines ....

time

port #

time

DPA

xxx

xxx

xxx

|

||

x x

x

x

x

x

x x

x

- -

-

input data streams

xx

x

x

x

x

xx

x

--

-

-

-

-

-

-

-

-

-

-

xxx

xxx

xxx

|

|

|

|

|

|

|

|

|

|

|

|

|

|output data streams

time

port #time

port #

... which data item at which time at which port

flowware manipulates the data counter(s) ...

... software manipulates the program counter



Xputer LabConfigware / Flowware Compilation

r. DataPath

Array

rDPA intermediate

high level source program

wrapper

address generato

r

configware

mapper

flowware

scheduler

M M M M

M M M M

MM

MM

MM

MM

data streams

data sequencer



Xputer Labmost important contributor to nano

SoC

we need rDPAs for:• cellular wireless• multimedia • other applications

relative merits: • performance• flexibility• time to market• product

longevity

key functionalities:to cope with • compute requirements• unstable standards• multiple standards



Xputer Lab

1960 1970 1980 1990 2000 2010

100 000 000

10 000 000

1000 000

100 000

10 000

1000

100

10

1

Processor Performance

microprocessor / DSP

No

rmal

ized

pro

cess

or

spee

d

Memory(Moore’sLaw)

Tra

nsi

sto

rs/c

hip

2G

3G

4G

1G

wirelessAlgorithmic Complexity

(Shannon’s Law)

No

rmal

ized

pro

cess

or

spee

d



Xputer LabPerformance vs. Flexibility

flexibility

throughput1000

100

10

1

0.1

0.01

0.0012 1 0.5 0.25 0.13 0.1 0,07

MOPS / mW

µ feature size

DeMan [T. Claasen et al.: ISSCC 1999]

hard-wired

hardwired

vonNeumann

instruction set processors

standard microprocessor

DSP FPGA

Reconfigurable logic

rDPAs go far beyond bridging the gap

rDPA

*) R. Hartenstein: ISIS 1997

rDPAs (reconfigurable computing)*



Xputer LabcSoC for wireless communication et

al.

ASIC

Program

ROM

LeonµC

RAMGlobal

SoC-RAM

Reconfigurable Hardware

Local XPP-RAM

Amba-Bus

FIFO-Bridge

ASIC

Program

ROM

LeonµC

RAMGlobal

SoC-RAM

Reconfigurable Hardware

Local XPP-RAM

Amba-Bus

FIFO-Bridge

BREG-ObjectFREG-Object ALU-Object

Left-Switch Right-Switch

CM-Interface

BREG-ObjectBREG-ObjectFREG-ObjectFREG-Object ALU-ObjectALU-Object

Left-SwitchLeft-Switch Right-SwitchRight-Switch

CM-InterfaceCM-Interface

Layout for UMC 0.13 mm CMOS

Xtreme processing unit (XPU) from PACT

incremental dynamic

reconfiguration

http://pactcorp.com

rDPA



Xputer LabTime to Market

• A Fundamental Paradigm Shift in Silicon Application

Revenue/ month

Time / months

1 10 20

ASIC Product

30

Update 1

Product

Update 2

reconfigurable Product with download

[Tom Kean]



Xputer Lab

© 2001, [email protected] http://KressArray.de


Xputer Lab>>> END

END



Xputer Lab

© 2001, [email protected] http://KressArray.de


Xputer Lab>>> Appendix

Appendixfor discussion



Xputer Lab

stolen from Bob Colwell

Why a dichotomy of machine paradigms?

CPU

caches, ...

vN bottleneck

data stream machine:

• bad message: caches do not help

• good message: no vN bottleneck

• caches not needed

vN: unbalanced

© 2002, [email protected] http://hartenstein.de


Xputer Lab

15

Soap Chip* Platform Template

microProg peripherals

RISC,VLIW

Config.MCU

ASIP

S/W

RISC,VLIW

Gen. Purp. RISC, VLIW

S/W

Scalable SoC interconnect

ASIC

Mem

ProcessorStandard

I/O blocks ROM, Flash

eSRAM eDRAM

Config.DSP Config.DSP

S/WS/W

Configware

SoftwareS/W

C/W

RC

rDPA

FPGAeFPGA

eFPGA

Standard H/W IP

C/W

C/W

C/W

© 2002, [email protected] http://hartenstein.de

important: coarse grain morphware

*) System on a programmable Chip



Xputer Lab

resources variable

algorithms variable

configware

streamware

morphwareAnti machinedata stream machine

flowware

Programming sources

von Neumanninstruction stream machineresources fixed

algorithms variable

hardware

software

reconfigurable or hardwired

hardwired only



Xputer LabMachine paradigms

M

I /O

instructionsequencer

datapath(ALU)

CPU

instructionstream

Software

von Neumann

M

d a t ap a th

DPU orrDPU

u n it

data addressgenerator(data sequencer)

memory

datastreamI/O asM*

data-stream machine

I/OMM MM M

(r)DPA

memory

I/OMM MM M

(r)DPU

embedded memory architecture*

Configware

Flowware

instruction stream machine



Xputer LabCost

new business model needed

desi

gn c

ost

year

product life cycle

the key enabler: morphware



Xputer Lab

Glossary

DPU data path unitrDPU reconfigurable DPUDPA data path array (DPU array)rDPA reconfigurable DPAISP instruction set processorAM anti machineAMP data stream processor*rAMP reconfigurable AMP

*) no “dataflow machine”

platform category

source „running“ on platform

machine paradigm

hardware (not programmable) noneISP** software von Neumann• morphwar

econfigware FPGA: none

data stream processor (AMP*) flowware

anti machinereconfigurable AMP (rAMP)

flowware & configware

digital system platforms:

morphware use granularity (path width) (re)configurable blocksreconfigurable logic • fine grain (FPGA) (~1 bit) CLBs

reconfigurable computingcoarse grain (e.g. 32 bits) rDPUs (e.g. ALU-like)multi granular: by slice bundling rDPU slices (e.g. 4 bits)

categories of morphware:

approaching consensus

**) instruction set processor *) data stream processor

Documents

CASES 2002 Intl Conference on Compilers, Architectures and Synthesis for Embedded Systems Embedded Architectures: Configurable, Re-configurable, or what?