BLECS-Combiner Presentation

Context

Functionalities BP and alarms table

Memory contents

State

Some questions Next steps *

BLECS-Combiner ContextICBLECFBLECSCIBUS Unmascable Beam PermitBLETC N1BLETC N16ICBLECFCreate 1BLECSBLETC N1BLETC N16Create 2Last BLECSBLETC N1BLETC N16Create n CIBUS Mascable Beam PermitHV1 + HV2ICBLECFICBLECFICBLECFICBLECFIC Ionization chamberBLECF BLM data acquisition card Current to FrequencyBLETCBLM data processing and Threshold ComparatorBLECSBLM Combiner and SurveyCIBUSControls Interlocks Beam User SingleHVHigh Voltage power supply1 to 4 crate connected in series with the BLECSSame connection between BLECS and between BLECS and CIBUSLast BLECS control the HV but all can read the HV voltage

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BLECS-Combiner FunctionalitiesBEAM PERMIT TRANSMISSION Beam Permit lines transmission from the Threshold comparators (TC) to the CIBU (Interlock network), tagging. BEAM ENERGY CONVERSION & DISTRIBUTION Receive the energy from the CTRV, converse it in 5 bits value and distribute it to the whole create. ANALOG GENERATION AND ACQUISITION Control and Monitoring of the high voltage (HV) for the ionization chambers TESTS Related to the Beam Interlock Related to the Beam Energy Related to the HV VOLTAGES SURVEY HV and low voltage with level comparators*

BEAM PERMIT LINE CONTROL BLECS-Combiner FunctionalitiesQQOFFONLines from BLECS (Up)Lines from FPGA (frequency > 1MHz)Transient voltage suppressors @ BLECS output ?*

BLECS-Combiner FunctionalitiesBEAM PERMIT LINE CONTROL BLECS Beam permit output spec Uout(ON) = 5V Uout(OFF) = -5V Iomax = 25 mA*

RatingUnitUout(ON)5VUout(OFF)-5VIomax25mA

Beam permit related partsBeam Permit from TC (M)Beam Permit decision unitPost-mortemandLoginBeam Energy FailureBeam Permit from TC (U)Beam Permit from BLECS (UA)Beam Permit from BLECS (UB)Beam Permit from BLECS (MA)Beam Permit from BLECS (MB)Beam Permit to CIBU (UA)Beam Permit to CIBU (UB)Beam Permit to CIBU (MA)Beam Permit to CIBU (MB)Test FailureFPGAClock from BOBRTime Stamps (orbit counter)BLECS-Combiner FunctionalitiesDump table*

Beam permit related partsBeam Dump (M & UM)Beam permitPower Supplies ComparatorsLogicP0 ConnectorBLECSBLETCP2 ConnectorBLECSor CIBUSCISVBeam Energy (Serial)Beam Energy (Serial)Beam permitHV1HV2ComparatorsVME PS 4xP0 PS 3x12 linesFPGATestsPost-mortemBeam infoBLECS-Combiner FunctionalitiesBeam permit decision unit*

Beam Energy related partsBLECS-Combiner FunctionalitiesSerial reception (redundant A and B) Counters: Frame, CRC error, Lost of Frame Toggle bit

Translation 16 bits to 5bits, hard coded conversion table Substitution of the original value by any value (in test mode only) Additional information (tests commands for the TC) on the reminded free bits (see tests functionalities section further) Serial transmission to up to 16 TC receivers in parallelDump table*

ScenarioCRC errorLost FrameCommentAction1NoNoNormal operationNormal2A or B-Threshold Error>? per secondwarning3-A or BThreshold Error>? per secondwarning4NoA & BNo Beam Energy receptionHighest Energy is send & error bit 1

Beam EnergyBLECS-Combiner FunctionalitiesDump table*

CTRVBeam Energy test setup on BA5BLECS-Combiner Functionalities2P2 CTG CPU BLETC BLETC BLETC BLECS1P2P0P0P0P0CTRP34562021*

ANALOG GENERATIONThe high voltage power supplies for the ionization chambers are controlled by analog signals 0-10V.There is an analog sum done between the 2 outputs of the DAC, the modulation signal is attenuated with a potentiometer digitally controlled. To HV supplyBLECS-Combiner FunctionalitiesBLECS-Combiner-Schematics-Rev1*

BLECS outputHV outputVoltage step0.153 mV45.8 mVVoltage range6.8 V2040 VModulation range peak-peak78mV to 100mV23mV to 30V

ANALOG ACQUISITIONThe high voltage power supplies have analog output monitors to view the voltage and current levels, there is 1 channel for the current and 2 channels of digitalization for the voltage (offset and low frequency modulation)ADCLPFilterInstrumentationamplifierDigital pot.Digital pot.GAINOffset compensationFrom the HV voltage monitoringLPFilterBufferFrom the HVcurrent monitor

FPGAFPGABufferBLECS-Combiner FunctionalitiesBLECS-Combiner-Schematics-Rev1Dump table*

BLECS input@ the HV [V]@ the HV [I]Adc resolution (DC) 13 bits1.22 mV366 mV2.44mAAdc resolution (AC) G = 1508.1 mV2.44 mVMeasured noise (2*StdDev)1.61 mV481.6 mV @ 1502V4.8mA @ 11.7mA

System testConsistency testManual actionsInternal Timer requestUser request Expert requestTESTS Related to the Beam Interlock Related to the Beam Energy Related to the HV(CPU): cpu based test, the decision passed/failed is given by the CPU to the BLECS which will release the beam permit to true (beam allowed)BLECS-Combiner Functionalities: TestsDump tableHV ModulationBeam Permit LinesConsistency test (CPU)BPBIS test:Beam Permit to Beam interlock (CPU)HV Step Tests Individual testsThe tests are triggered by the CPU (Sequencer?) and are activated by the BLECS only if the Beam info indicate that there is no beam permit. For some tests, the result can only be computed by the CPU. The result will be written on the combiner in order that it gives the beam permit again.Energy test*

CONSISTENCY It controls the threshold table by changing the energy and reading the logging. CPU based testHVLF Low frequency modulation of the HV Modulation of the HV power supplies an analysis of the Running Max including HVAT step of the HVBPTC - Beam Permit Lines from TC Test of the lines between BLETC and last BLECS (before CIBU)SYSTEM TEST (by Timer, User & Expert) It include all the standard test to be done within 12 to 24hours: Consistency, BPTC, HVLF.CONSISTENCY (by User & Expert) It controls the threshold table by changing the energy and reading the login. CPU based testBPBIS (by BIS User, Expert?) Test of the lines between BLECS and LHC Beam Interlock System. CPU based testEnergy Test (by User ?). The master of CTRV send a sequence of energy. The BLECS check for this sequence.Beam Energy CRC Continuous check of the correct reception of the Energy valuesHV monitoring Continuous check of the U & I for the 2 power supplies with ADC & comparators.VME Supplies monitoring Continuous check of the 5V, 3.3V and 12V with comparators.P0 Floating Supplies Continuous check of the 5V and 15V with comparators.CONTINUOUS CHECKSYSTEM TEST detailsBLECS-Combiner Functionalities: TestsDump table*

Continuous checks on the frame (arrives every ms): CRC errors on the data reception. Lost Frame. Time out in case of no reception on time. Lost Energy value. Time out in case of no new energy (every second)Energy test (by User, Expert?) Test of the Energy values changes. The CTRV master initiate a known sequence of different energy values. The BLECS check for it when it was asked for. Related to Beam EnergyBLECS-Combiner Functionalities: TestsDump table*

CONSISTENCY (by User & Expert) It verify the threshold table by changing the energy in the BLECS and reading the login on the BLETC. Needs a result of the comparison from outside to be written inside the BLECS BPTC - Beam Permit Lines from TC Test of the lines between BLETC and last BLECS. (see further slides)Use of the Beam Status from the BIS (CIBUS interface) to know when to accept change on threshold tableCTRV transmission specification 1. 10010000 header (8 bits)2. Energy value (16 bits)3. Toggle bit + 000 (4 bits)4. CRC (4 bits)Energy value (16 bits)CRC check, errors countersTime out check, errors countersConversionBLECS transmission specification 1. 10010000 header (8 bits)2. Composite data (16 bits)3. Toggle bit + 000 (4 bits)4. CRC (4 bits)To maximum 16 TC in parallelBLECS-Combiner Functionalities: TestsRelated to Beam Energy** Applied when transmission is broken.

Beam Energy (0 to 31) [5 bits]Error bit [1 bit]SofResetTC [1bit]System under TestUnmaskable Beam Info [1 bits]Maskable Beam Info [1 bits]BPL Unmaskable test activation [1 bit]BPL Maskable test activation [1 bit]Beam Permit Line test TC Card Number [4 bits]Bit position[15..11][10][9][8][7][6][5][4][3..0]Broken link state*31 (highest)10011000

BPLBIS (by BIS User, Expert?) Test of the lines between last BLECS before the CIBU and LHC Beam Interlock System. CPU based testBPTC - Beam Permit Lines from TC Test of the lines between BLETC and last BLECS (before CIBU)

Access by the CPU of the Beam Permit outputs lines: Only when no beam Only one line can be modified, all the others should be Beam permit away (false) Because of the Daisy chain structure between the BLECS, all the 3 (for one IP) have to be tested at the same time.

Related to Beam InterlockBLECS-Combiner Functionalities: TestsDump table*

Access by the CPU of the Beam Permit outputs lines: Only when no beam Only one line can be modified, all the others should be Beam permit away (false)Procedure for the BPL to BIS testBLECS-Combiner Functionalities: TestsDump tableRequest the BPL to BIS test: Activate UBPBISTR (User Beam Permit to BIS Test Request) The system waits for the Beam Info to go False in order to enter in the testOnes inside the test, all the beam permit lines goes falseThen it is possible to put only one beam permit line (A or B) to true for maskable and unmaskable linesThe test ends when the result of this test is given to the board by writing in the correct register bit 1 for passed and 0 for failed.*

BLECS 1Task :Identify the last crate in the chain (the one which touch the CIBU)Related to Beam InterlockLast crate identification BLECS-Combiner Functionalities: TestsHV crate

BLECS 2VCC100kGND5kFPGAIf the FPGA input = 1 there is no BLECS under. Means there is the CIBU and this is the last BLECS before CIBU.BLECS 2BLECS 3BLECS 4Top to VCCIt see top positionIt see bottom positionP2.A30P2.A29

BLECS 1VCC100kGND5kFPGAP2.A30P2.A29If the FPGA input = 0 there is another BLECS under. Means this is not the last BLECS before CIBU.*

BLECSTask :Notify the other BLECS that the system is under test.Last crate received beam permit away (Beam Dump)Related to Beam InterlockCommune lines between crate BLECSOpen drain linesBLECS-Combiner Functionalities: TestsBLECSBLECS*

Commune lines between crate Open drain lines with dedicated IC: OD1 & OD2BLECS-Combiner Functionalities: Tests*Line direct FPGA to FPGA (200 Ohm between IO) simulation of OD with pull-up OD3BLECSBLECSBLECSBLECSOD1OD2OD3Signalization needed:The system is under test (the last crate keep the beam permit lines low)The last crate has received the beam permit low (See BPTC test)Request 100pA test levelRequest Modulation level of the HV+ Modulation of the HV

NameOD1OD2OD3DescriptionNormal operation111Beam permit indication from the la combiner before the CIBUSxx0OD3 can change to indicate BP is false by the last crate before CIBUS (See BPTC test)System under test (all test except Modulation)01xThe HV level goes at 100pA when any test startsSystem under test Request Modulation level and Modulation.00x

BLECSPrinciple BPTC (Beam permit from BLETC to last BLECS) BLECS-Combiner Functionalities: TestsBLECSBLECSLast BLECSFrom any BLETC to the last BLECS before the CIBUOne crate after each otherThe tested crate send an info crate under testThe last BLECS should know it position and send a feedback saying I received the beam dumpThe CPU initiate the test on one of the crateThe BLECS check the Beam info to see if the test is allowed, otherwise waitsThe BLECS notify the other crate by changing the state of the OD1 lineThe last BLECS put the beam permit away and wait for Beam DumpThe tested BLECS test the first TC by sending the command thought the energy serial connection.The beam dump should start from the TC and pass thought all BLECS needed to arrive to the last BLECS.The Last BLECS receive the Beam Dump and notify the tested crate by pulling the OD2 line.The tested BLECS receive the Beam Dump notification and start to test the next TC and so on till the last TC.OD1OD2*

HVLF overviewBLECS-Combiner Functionalities: Tests*

BLECS-Combiner Functionalities: Flash param*Parameter 2: Set voltage modul. (peak-peak)Parameter 1: Set HV voltage value Parameter 3: Set frequency modul.MTFResult 1: PhaseResult 1: GainLSAModulation 1: VoltagePeriod Modulation 2: VoltagePeriodHV normal operationHV HVCFCHV HVRDACHV HVRGOHHV peak HVCFCHV peak HVRDACHV peak HVRGOHPresent TC board tablePresent CFC board tableStatus table TestCFCStatus table RSTDACStatus table RSTGOHPresent channel tableHV Diff HV1 & HV2LSAFlashRegistersCPUExpert GUITrimROMPer crateFrom Crate through CPURsum tableSWITCH Enable write registerModulation 1:Gain min & maxPhase min & maxModulation 2:Gain min & maxPhase min & maxMonitorPer IP

HVLF related parts1 TCRAM256x32bitsPhase & Gain trackingDecision UnitThresholdsTCMax.16RAM256x32bitsPhase & Gain trackingDecision UnitThresholdsRAM256x32bitsPhase & Gain trackingDecision UnitThresholdsReal Excitation SignalNV MemoryFirst glance: Excitation Signal frequency 30mHz or 100mHzSample per period 256 for the reference and 1s/Exitation signal for the RunMax (Use the Login) Number of period min. 3Number of channel in parallel 16 (1 TC)Total time for one create 3*1/0.3Hz*16TC = 160sBLECS-Combiner Functionalities: TestsRAM256x16bitsCH1CH2CH16VMERAM256 Channelsx32bits update every Login*

HVLF first resultsBLECS-Combiner Functionalities: TestsResult modulation 30mHzResult modulation 100mHzGain StdDev Phase StdDevIn this test, there were two methods working in parallel: Simple and double cross-correlation Further investigations needed to ameliorate, select one of the two and fine pitch the method.There are only 4 channels connected with a chamber for this test. There can be easily identified them on the result of the measurements below.*

Test command & Test Result for Beam Permit to BIS

Status Test ResultsAlarms

Crate setup infoRunnMaxStart TestsResults Tests:1) Consistency2) Threshold to BPL

Energy ValueBeam info stateTest commands Combiner SN?BLECS-Combiner Functionalities: Data transfersBLECSBLETC N1 to 16CPUVMEP0 SerialCIBUSBICEthernet*

BLECS-Combiner FunctionalitiesTest Decision unitSystem testTest requests Decision unitConsistency test*HVLF modulation testTest results

There is a second method of HV survey which use comparators with fixed level connected to the FPGA for analysis. BLECS-Combiner Functionalities: HV surveyComparators threshold:V monitor higher: 2100=> limit of IC capacitorV monitor lower: 500I monitor higher: 18mAV monitor lower: 0.5mAThe two HV (voltage and current) are monitored by one ADC at a rate of 6.94 kHz, some logic can be implemented to survey any changes:Threshold comparison with a value determined by the location (for I, depend on the number of ionization chamber connected)PT8 first test: around 0.6 to 0.7mABLECS-Combiner-Schematics-Rev1QuestionsDump table*

Low Voltage power supplies Survey VME: 5V, 3.3V, 12V Analog: 5V, 15V BLECS-Combiner Functionalities: LV surveyUse comparators to detect any failure and :Count the number of failure / per LOGIN reading (1s) if ripples => ~100 per secondMeasure length of the failure ? (resolution 25ns)BLECS-Combiner-Schematics-Rev1QuestionsDump table*

BLECS-Combiner FPAnalog outputSelect analog outputCLK inputsInputs A & BOutputs A & BVME access ledBeam permit inputBeam permit outputDump lines / Beam infoQuestions*

System OperationalSystem in testTest RequestedPost MortemHighVoltage failedBeamEnergy failedObitClock failedDUMP

UA inUB inMA inMB inUDLMDLUBIMBIUA outUB outMA outMB out

Vref1Vdc1Vmon1Imon1Vref2Vdc2Vmon2Imon2

BLECS-Combiner BP and alarms tableBLECS-MemoryMapping*

SourceAlarm LowAlarm MediumAlarm highDumpPM recordCommentLinkBeam permit INxx4 lines: UA, UB, MA, MB from another BLECSSlide 6P0 Beam Permit xx2 lines: U, M from the BLETCHV current comparatorIf low or highLow limit = 0.5mA, High limit = 18mASlide 10Slide 18HV current ADCIf low or highlimits are depending on loadHV voltage Comparator1 or 2 failedIf 1&2 down for 1sIf 1&2 down for x sec.HV voltage ADCIf Instable1 or 2 failedTime limited instabilityLow voltageIf rippleIf downCharacterization of the PS, Ripple level determination.Slide 19System testIf test failedSlide 12Consistency testIf test failedSlide 11BPLBISIf test failedBeam permit to the Beam Interlock SystemSlide 13

BLECS-Combiner Memory contentsPM SRAM Post mortemBD SRAM Beam Dump, content to be definedXtra SRAM Extra, content to be definedFlash ROM Flash memory for saving parametersLOGIN Logged status and principal results (Read only) TEST RESULTS Result of the last tests. To be saved after every testsControl / Status Registers Status of the Create: (nbr. TC, nbr. Channels, RunMax for modulation, ...)DAB64x Control / Status RegistersBLECS-MemoryMapping*

BLECS-Combiner Memory contentsLOGIN Logged status and principal results (Read only)BLECS-MemoryMapping*

BLECS-Combiner Memory contentsPM SRAMThis is the first attempt of the post mortemdefinition. To be reviewedBLECS-MemoryMapping*

BLECS-Combiner StateEstimation of the work completion:*

Function descriptionHardwareFPGA codeTestBeam permit from TCCompletedpartialNot startedBeam permit to CIBUCompletedPartialPartialBeam EnergyCompletedPartialPartialAnalog generationCompletedCompletedPartialAnalog acquisitionPartialPartialPartialTest Beam InterlockPartialPartialNot startedTest Beam EnergyCompletedCompletedNot startedTest HVPartialPartialNot startedVMEPartialPartialPartial

BLECS-Combiner Some questionsHardware: missing function, improvements? Front panel:Is there all the needed information / devices ? HV survey:What could be the levels of current to define threshold What are the levels (Vlower and Vhigher) Low Voltage survey:Method of process the comparators output. Counter? Time measurements?

BLECS-Combiner-Schematics-Rev1viewviewview*

BLECS-Combiner next stepsFPGA code correction and functions addition, use of the second iteration (available). Hardware completion for a third revision. Test bench development for the test of the production boards. Validation of the third prototype. Production of the boards (45) Completion of the test bench (Hardware, software) *

Combiner functionalitiesANALOG GENERATIONSCHEMATIC*

Combiner functionalitiesANALOG ACQUISITION*

Combiner functionalitiesBEAM PERMIT CONTROL PCB ImplementationBeam Dump lines from the TCBeam permit lines from previous combiner to next combiner or BIS*

Combiner functionalitiesANALOG DIGITAL CONVERSIONSPCB ImplementationAnalog generation for the 2 HV PSRC filter close to the connector to cut the eventual high frequencies induced by the digital componentsDigitalization of the information coming from the 2 HV power supplies*

Combiner functionalitiesVOLTAGES SURVEY 1) HV SUPPLIES2) VME & P0 floating PS

Survey VME PSSurvey HV PSSurvey P0 floating PS*