SENSgRS ACTWORS

A E LS E V I E R Sensors and Actuators A 62 (1997) 636-645 PHYSICAL

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Bipolar-compatible epitaxial poly for smart sensors: stress minimization and applications

P.T.J. Gennissen a,., M. Bartek a, p.j. French a, P.M. San'o b Laboratory for Electronic hTstr,tmentation, Facul~. of Electrical Engineering, DIMES, Delft University of Technology, PO Box 5031, NL-2600 GA De!ft,

Netherlands b Laboratory for Electronic Devices, Materials and Components, Faculty of Electrical Engineering, DIMES, Delft University of Technology, PO Box 5031,

NL-2600 GA Delft, Netherlands

Abstract

This paper presents the optimization of the fabrication process for bipolar-compatible epipoly for micromachining applications. The use of an epitaxial reactor to grow polysilicon enables the growth of monocrystalline silicon (for bipolar electronics) and polysilicon on top of oxkle (for MEMS) in a single deposition step. However, after bipolar processing the early structures showed compressive strain in the epipoly layer, which then required careful MEMS design, The cause of this compressive strain is shown to be the oxidation steps in the bipolar process, The occurrence of this strain can be explained by the presence of oxygen in the epipoly. An alternative processing technique, where the epipoly is doped using implantation and shielded from oxidation by a nitride layer during further bipolar processing, yields epipoly layers without compressive strain. The full thermal budget of the bipolar process is used to diffuse and activate the implanted epipoly dopant, Functional thermal and electrostatic sensor and actuator structures have been fabricated to demonstrate the feasibility of this process, © 1997 Elsevier Science S.A.

Keywords: Bipolar-compatible epitaxiat polysilicon; Micromachining; Smart sensors

1. Introduction

The two major techniques for the fabrication of microelec- tromechanical structures (MEMS) are surface and bulk micromachining. In bulk micromachining a masking layer is patterned at the back side of the wafer and the unmasked areas are etched in anisotropic wet etchants such as KOH. The final structures can be made of the remaining silicon substrate or from KOH-resistant materials, and the resulting front side of the wafer is usually flat, This technique can be used to fabricate a range of devices, including pressure sen- sors, accelerometers, microvalves and nozzles. Bulk micro- machining does, however, have several disadvantages. Since KOH stops on ~ 111 ) planes it is not possible to etch vertically through the wafer when standard (100) type waters are used. The side-walls resulting from the etch stop on ( 111 ) planes have a slope of 54.7 ° with respect to the wafer surface. When a standard 500 ~m thick substrate is used, the minimum width of the etch hole at the back side of the wafer needed to etch through the full wafer is about 700 Ixm, resulting in large

* Corresponding author. Tel.: +31 15 278 33 42. Fax: +31 15 278 57 55. E-maih P.Gennissen @et.tudelft.nl

0924-4247/97/$17.00 © 1997 Elsevier Science S.A. All rights reserved P11S0924-4247 ( 9 7 ) 0 1 4 9 8 - 2

structures and therefore low die count per wafer. This prob- lem can be solved by the use of (110) wafers, which allows wet etching of vertical trenches [ 1 ]. The inability of KOH to etch convex comers limits flexibility in device shape and the required comer-compensation structures consume consider- able chip area. Finally, bulk micromachining often requires double-sided alignment, which adds to the process complexity.

In surface micromachining, on the other hand, structures are fabricated in layers which are deposited on top of the substrate. The fabrication starts with the deposition and pat- teming of a sacrificial layer, often phosphosilicate glass (PSG). Then constructional layers such as polysilicon or silicon nitride are deposited and patterned. In the last step the sacrificial layer is removed, leaving free-standing structures. Usually LPCVD is used to deposit both the sacrificial and constructional layers. Since the growth rate of LPCVD layers is usually low, the thickness of the layers used is often limited to a maximum of about 2 ~m. Special care must be taken to control the mechanical stress in the deposited layer. For most structures a low tensile stress is required for device fabrica- tion. The size of surface-micromachined structures is very small in comparison to bulk-micromachined ones. No dou-

P.T.J. Gem,issen et al. / Sensors amt Actuators A 62 (1997) 636-645 637

ble-sided alignment is needed to fabricate the devices and the die count can be rather high due to the small size of the structures. A disadvantage of the small size of the structures is that the signal levels are often too low to allow off-chip signal conditioning. Therefore, surface micromachining is often carried out as a number of post-processing steps after completion of a bipolar oi" CMOS process in which the signal- conditioning electronics have been fabricated. Devices realized in the surface-micromachining technique are micromotors, accelerometers, pressure sensors and comb drives.

Many of the disadvantages of surface micromachining are caused by the limited thickness of the constructional layer. In particular, a surface-micromachined lateral accelerometer with capacitive readout would greatly benefit from a thicker constructional layer. The thick layer would lead to a relatively large value of both proof mass and readout capacitance. A thick layer ol'polysilicon can be grown in an epitaxial reactor that has a deposition rate which is approximately 100 tirnes larger than that of a standard LPCVD poly system [2]. If the deposition of this layer is combined with the growth of the epitaxial layer for the signal-conditioning electronics, a smart sensor can be made without influencing the thermal budget of the electronics process [3,4]. Special care must be taken to avoid compressive mechanical stress. The epipoly tech- nique has the following advantages over conventional surface mieromachining: • Due to the high deposition rate (up to 1 p,m rain - ~) the

thickness of the polysilicon layer can be much larger than the thickness of conventionally grown LPCVD poly ( <7 nm min- t ) , leading to more rugged microstructures, higher masses for acceleration sensors and higher output signals if lateral capacitances are used [5].

• The thermal budget of the bipolar fabrication process is unaffected by the poly deposition.

• In contrast to conventional surface micromachining, where structures are fabricated on the wafer surface, these epipoly microelectromechanical devices are countersunk in the epitaxial layer, yielding a highly planar structure.

• Due to their large thickness, devices fabricated in epipoly are rather stiff in the vertical direction. This lowers the probability of stiction of these devices to the underlying substrate. A disadvantage of this merged fabrication process is that

the sensor fabrication is no longer a pre- or post-processing module. This makes the fabrication more difficult when third- party chip foundries are used for sensor production.

In this paper the fabrication of an epipoly layer which is compatible with a standard bipolar electronics process is investigated. Several experiments were performed to opti- mize the mechanical and electrical characteristics of the layer.

2. Layer material optimization

Several experiments were performed to characterize the epipoly growth process and to optimize the epipoly layer.

The goal of the experiments was to fabricate a layer with optimum properties after the full bipolar process in order to open up possibilities for smart-sensor fabrication. All exper- iments were carried out in a single-wafer epitaxial reactor (ASM Epsilon One) using an HCl/dichlorosilane (DCS) gas system. Unless mentioned otherwise, the processing con- ditions were as follows:

Temperature 1050°C Pressure 60 torr DCS 360 slm HCI 0 slm Prebake 1000°C, 2 min in hydrogen Deposition time 4 min

Since the mechanical properties of the epipoly layer are the dominant factor for MEMS applications, these properties were optimized first and the electrical properties were only measured for the layers which passed the mechanical test.

The following influences were addressed: • poly seed-layer structure • oxidation • nitride protection during oxidation steps • epipoly growth temperature and doping • sacrificial oxide area and thickness • gas composition during epipoly growth • in situ prebake

2.1. Poly seed structure

2.1.1. Experimental On three oxidized wafers a low-stress LPCVD polysilicon

seed was deposited (deposited as a semi-amorphous structure and in situ annealed at 600°C [6] ) and on two oxidized wafers a standard LPCVD polysilicon seed (deposited directly as polysilicon) was grown. One wafer from each group was annealed at 1100°C as this is the highest temper- ature step during the bipolar process. On all the wafers the epipoly layer was grown at standard conditions. Then one quarter of each wafer was doped using the deep p-type insu- lation diffusion step using a solid boron source and one quar- ter was doped using the POC13 collector contact diffusion of the bipolar process. The remaining half received only the 1 × 10 ~6 cm-3 in situ arsenic doping of the epi growth. Then the epipoly was patterned and etched by RIE followed by sacrificial etch and freeze drying. In order to measure the strain, pointer structures as shown in Fig. 1 were used. These structures can be used to measure both compressive and tensile strain [7,8]. One control wafer received low-stress LPCVD poly and epipoly, but was not taken through the bipolar process.

2.1.2. Results All the wafers that were taken through the bipolar process

showed very high compressive strain levels irrespective of poly seed layer or doping type and level, The wafer which did not see any of the bipolar steps, on the other hand, had a

638 P.T.J. Gennissen et at. /Sensors and Actuators A 62 (1997) 636-645

[ ] Anchor

[ ] Free

[ ] PIE etched

Fig. 1. Strain-measurement structures: (a) Delft type [7]; (b) Berkeley type [8].

much lower stress level. The conclusion of this experiment is that the high compressive strain level in the epipoly layer after bipolar processing is caused by either the high-temper- ature treatment only, or by the oxidation.

2.2. Oxidation

2.2.1. Experimental For this experiment two oxidized wafers received a low-

stress LPCVD poly seed layer, followed by epipoly growth. Then one was annealed for I0 rain at 1100°C in oxygen and the other one was annealed for the same time and temperature in argon. Then the wafers were etched by RIE, followed by sacrificial etching and stress measurement.

2.2.2. Results The wafer which was annealed in argon did not have any

noticeable difference in stress level compared with the as- deposited layer from the previous experiment. The oxidized wafer, on the other hand, showed a strong increase in com- pressive strain level even after this very short oxidation step. Oxygen penetration during oxidizing steps was the likely cause of the compressive strain in the epipoly after bipolar processing. This means that a standard diffusion process can- not be used to dope the epipoly layer.

2.3. Nitride protection

2.3.1. Experimental On one wafer with sacrificial oxide and a poly seed layer,

epipoly was grown using the same recipe as in the previous experiment. Then one half of the wafer was covered with nitride followed by a 4 h 40 min oxidation step at 1100°C. This is the normal total thermal budget of the bipolar fabri- cation process. Then the nitride was stripped and the epipoly was patterned, followed by sacrificial etching and strain measurement.

2.3.2. Results The half of the wafer which was not shielded from oxygen

during the oxidation step showed a high compressive strain level. The protected half, however, did not show any meas - urable mechanical strain. The compressive strain can eas i ly be observed by an array of double clumped beams, such as shown in Fig. 2. The strain was calculated from the strain- measurement device given in Fig. 3. From this structure the compressive stain in the oxidized layer was calculated to b e 800 We. The strain in the protected layer was below the accu- racy of the measurements.

Fig. 2. An ,array of double-clamped epipoIy beams with lengths of 100,200- 1000 Ixm and a width of 2, 4 and 6 t.zm: (a) epipoly layer passivated wi th nitride during oxidation; ('b) epipoly not passivated during oxidation. Note the clear difference in strain level.

P.T.J. Gennissen et al. / Sensors" and Actuators A 62 (1997) 636-645 639

Fig. 3. Strain-measurement structures. The device which was covered with nitride during the oxidation process shows no measurable strain (a), while the unprotected device indicates compressive stain (b).

2.4. Growth temperature

2.4.1. Experimental In this experiment three oxidized wafers with a low-stress

LPCVD poly seed layer were used to analyse the influence of the epipoly growth temperature on the mechanical and electrical properties of the epipoly layers. Epipoly was grown at 950, 1050 and 1150°C at 60 torr pressure. For each depo- sition temperature the growth time was adjusted to grow a 4 ~m thick monocrystalline epilayer, since this is the epilayer thickness of the bipolar process. Then one quarter of the wafer was implanted with boron at 100 keV and a dose of 5 × l0 ~5 cm -2. Two other quarters were implanted with phosphorus and arsenic, respectively, at the same energy and dose, while the remaining quarter received only the in situ arsenic dope of the epipoly growth process. Then a 200 nm thick low- stress LPCVD nitride layer was grown to shield the epipoly wafer f rom oxygen penetration during further bipolar proc- essing steps. The same method is used in LOCOS processes. After this the wafers were put in a furnace at 1100°C for 4 h 40 min in oxygen in order to simulate the full bipolar process without performing all the different steps. Then the nitride layer was stripped in boiling phosphoric acid and trenches were etched through the epipoly layer, followed by sacrificial etching.

2.4.2. Results On all the wafers the mechanical stress levels were very

low. Due to the limited size of the strain-measurement struc- tures it was not possible to obtain a reliable quantitative strain

estimation, but all the strain-measurement structures indi- cated no strain, or very low tensile levels. In order to get more insight into the mechanical difference of the grown layers, beams were pulled-in electrostaticalty. Fig. 4 shows the measurement set-up. A voltage is applied between the free- standing etched beam and a counter electrode. The voltage between beam and electrode is increased while observing the beam through a microscope. The voltage at which the beam collapses to the counter electrode is the pull-in voltage. After collapsing the beams irreversibly stick to the counter elec- trode. They did, however, return to their straight position if the activation voltage was left below the pull-in voltage. The width of the beams used was 4 ~m, the gap between beam and counter electrode was 2 ~m and the thickness was 4 ~m.

Free-standing beam " ~

t9

Fig, 4, Pull-in voltage measurement set-up.

Voltage Source

640 P.T.J. Gennissen et al. / Sensors and Actuators A 62 (1997) 636~545

160

140

120

100

go

60

4O

20

x

o 1 I50'C, Bc~ron

I- 1050"C, Phosphorus

950"C, Phosphorus

X 950°C, Arsenic

A950"C, Boron

×

beam length (gm)

a x

9;0 000

Fig. 5. Relation between pull-in voltage and beam length for several growth temperatures and doping types.

65 . . . . . .

60 ........ -

50 Arsenic

I

0 0 . 45 ,.

k

35 P h o s p h o r u s ' ~ ~ " ,

3 0

2~ 950 I' fJ00 1050 I l'O0 1150 growth temperature ('C)

Fig. 6. Relation between epipoly growth temperature and sheet resistance.

The resul ts o1' these measurements are plotted in Fig. 5. The pull- in voltage is determined by a combinat ion of Y o u n g ' s modulus and intr insic strain of the layer. From the measure- ments it can be concluded that the various layers have very s imilar mechanica l characteristics.

F r o m the different layers the resistance of a 500 txm long 4 ~ m wide freestanding double-clamped beam was measured to invest igate the influence of growth temperature on the resist ivity of the epipoly layer. The results are plotted in Fig. 6. A higher epipoly growth temperature leads to a lower sheet resistance of the layer. Since the sheet resistance of the layer is acceptable for MEMS fabrication at all growth tem- peratures used, 1050°C was chosen as the standard deposit ion temperature, since this is the staudard epi growth temperature of the bipolar process. The designer also has the freedom to choose any of the dopants used in this experiment.

2.5. Sacr i f i c ia l o,vide

2.5.1, E x p e r i m e n t a l

In this exper iment the influence of the sacrificial oxide thickness on the epipoly planarity was investigated. Two wafers were thermal ly oxidized to grow 700 and 100 nm

sacrificial oxides. One control wafer was not oxidized. Then

a standard LP C VD low-stress polysi l icon seed layer w a s grown. The poly seed layer and under ly ing oxide w e r e removed from the wafer in a chessboard pattern. The s ize o f the squares was 1 cm × 1 cm. Then ep i / ep ipo ly was g r o w n at standard condi t ions for all wafers and the surface o f the wafers was scanned us ing an alphastep surface scanner. P S G and low-temperature oxide ( L T O ) were also inves t iga ted as a fast etching al ternat ive for the sacrificial thermal oxide.

2.5.2. Resu l t s

The surface scans of tim three wafers are shown in F ig . 7. The wafer with the thickest sacrificial layer is s h o w n in Fig. 7 ( a ) . From this scan it is clear that the surface o f the wafer is not planar. There is a step at the ep i / ep ipo ly in te r face , and the epi and epipoly layers are concave and c o n v e x , respectively. This non-planar i ty is be l ieved to be caused b y a temperature gradient over the epi and epipoly areas d u r i n g growth. In the epireactor the wafers are heated by h a l o g e n lamps. The epipoly areas become warmer than the epi a r e a s

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(e) Fig, 7. Surface scans of the epi/epipoly interface for (a) a wafer with 700 nm sacrificial oxide, (b) a wafer with 100 nm sacrificial oxide and (e) a wafer without sacrificial oxide. Note the difference in Y-axis scale for wafer (a).

P.T.,L Gennissen et al. / Sensors' aml Actuators A 62 (1997) 636-645 641

Fig. 8. Polysilicon bubble caused by outgassing of the underlying PSG layer at high polysiltcon growth temperatures.

because of the thermal insulation properties of the underlying oxide. Since the average temperature of the wafer is set to 1050°C, the centres of the epipoly squares are above this temperature and the temperature in the centres of the epi areas is below 1050°C. The plots of the wafer with thinner sacrifi- cial oxide (Fig. 7(b) ) and no oxide at all (Fig. 7(c) ) con- firm this hypothesis. The resulting surface is much more planar. The step at the interface still exists, as this step is not caused by a temperature gradient, but by a preference of the DCS to decompose at the monocrystalline silicon rather than at the poly seed. In order to get a surface as planar as possible, the temperature gradient over the wafer during epi/epipoly growth should be minimized. This is accomplished by mini- mizing the areas with buried oxide and choosing the oxide thickness not larger than necessary.

The use of PSG and LTO is not possible in the epipoly process, since these layers are not stable at the high growth temperatures of the epipoly. The LTO delaminated from the wafer surface during cooling down, causing particles in the epi reactor. With PSG polysilicon bubbles were formed dur- ing epi growth, caused by the outgassing of the PSG layer [9]. An example of such a bubble is shown in Fig. 8.

2.6. Gas composition

1,2

0.6

"5

"~ 0'4 I 1),2

0L 0 1 2 3

IfCt to DCS ratio

J

Fig, 9. (a) SEM photograph of a combination of epi and poly growth on the same chip. (b) Step height at the epi/epi-poly iaterfaee vs. HCI to DCS ratio.

2.6.2. Results Fig. 9 shows an SEM photograph of an area with combined

epi and epipoly. The step height at the epi/epipoly interface is a function of the HCI/DCS ratio. The dependence of the step height on gas composition is also given in Fig. 9. T h e more HC1, the higher the step height and the higher the rel- ative growth-rate difference. This was expected, since HCI is added to DCS to prevent polysilicon nucleation and growth in selective epitaxial growth recipes, where monoc12¢stalline silicon is grown on bare silicon and poly nucleation is pre- vented on oxide areas.

2.6.1. Experimental In this experiment five oxidized wafers with a low-stress

LPCVD poly seed layer were used to analyse the influence of the gas composition during epi growth on the relative growth rate between monocrystalline silicon and epipoly. As in the previous experiment the poly seed layer and underlying oxide were removed from the wafer in a chessboard pattern. Epipoly was grown at a temperature of 1050°C, a pressure of 60 torr, a DCS flow of 100 slrn and a HC1 flow of 0, 100, 200, 300 and 400 slm, respectively. The deposition time was adjusted to grow a 4 ~m thick monocrystalline epilayer for all wafers. After epigrowth the surface of the wafer was scanned using an alphastep surface scanner.

2.Z Prebake

2.Z t. Experimental In previous work on selective epitaxial growth (SEG) and

epitaxial lateral overgrowth (ELO), the influence of the pre- bake temperature on the epi/oxide interface was studied [ 10]. The prebake in hydrogen is needed to remove any native oxide from the rnonosilicon and poly seed substrate to ensure good quality of the grown layers. During the prebake silicon reacts with silicon dioxide and evaporates as silicon monoxide. One wafer received the standard bipolar epi pre- bake of 1150°C for 2 rain and two other ones received a 2 rain prebake at 950 and 1000°C.

642 P. 7"..1. Gennissen et al. /Sensors and A ctuatorsA 62 (1997) 636-645

Fig. 10. Undercut at the Si/oxide interface when the prebake temperature is too high.

2.7.2. R e s u l t s

Fig. 10 shows an SEM photograph of a cross section of an epi/oxide interface after selective epitaxial growth when the prebake was carried out at 1150°C. During the 2 min prebake a 2 ~m void was formed. This void was not observed for the wafers which received the 950 and 1000°C prebake. A pre- bake of 1000°C was chosen for the epipoly process, since this was the highest temperature for which a void was not observed.

transistors should be unaffected by the epipoly growth, the thickness and in situ doping level of the epipoly are dictated by the bipolar process. The basic fabrication process starts with (100)-type wafers in which buried n + regions are implanted. The oxide originating from the buried layer drive- in step is used as sacrificial layer for the MEMS structures. On the oxide a thin layer of LPCVD polysilicon is grown, which acts as a seed layer for the epipoly growth step. Then the LPCVD poly and underlying oxide are removed from areas on the substrate where no MEMS are to be fabricated. During epitaxial growth monocrystalline silicon grows on monocrystalline silicon and polysilicon grows on the poly- silicon seed. The growth rate of the polysilicon is about 70% of the growth rate of the epi. A planar surface can be obtained if the combined thickness of the sacrificial oxide and poly seed layer is tuned to compensate for the difference in growth rate. Then the epipoly is doped by implantation and covered with nitride. Transistors are fabricated according to a standard bipolar flow chart. Before metallization nitride is deposited on the transistors for electrical insulation, followed by trench etching through the epipoly layer until the buried sacrificial layer is reached. In the last step the sacrificial layer is removed followed by freeze drying [ 11 ]. The fabrication procedure is illustrated in Fig. 11.

3. Basic fabrication process

In the proposed fabrication process the growth of polysil- icon for MEMS structures is combined with the epi growth step of the bipolar process. Since the properties of the bipolar

4. Practical issues when working with epipoly

4.1. L i t h o g r a p h y

Since the epipoly layer is very thick and the epipoly surface is very rough, special care must be taken when lithographic

(a) Buried n formation, patterning of poly seed on sacrificial oxide.

(b) Result after epi/poly growth, poly ' imptant and nitride protection.

C E B

(c) Bipolar process flow completed.

(d) Metallization and trench etching.

(e) Sacrificial etch, freeze dry,

epi/zubsttate ~ n+-silicon i l l p+-sificon []~ poly [ ~ oxide ~ nitride

Fig. 11. Fabrication scheme for micromechanical structures using epi-poly.

P. T.J, Gennissen et al. /Sensors and Actuators A 62 (1997) 636--645 643

steps are to be performed after epipoly growth. It is mandatory to remove the poly seed layer and underlying oxide from the alignment marks before epipoly is grown, especially when an automatic wafer stepper is used. Due to the rough surface, scattering of the exposure light will occur at the epipoly surface. This limits the minimum feature size for patterns on the epipoly. In our process we have defined 2 Ixm wide epi- poly beams with a horizontal spacing of 1 >m when HiPR6517HC photoresist was used. This photoresist absorbs the scattered light. For patterns on the monocrystalline part of the substrate no special care is needed, apart from the alignment marks, Since MEMS structures are usually large compared to readout electronics, no lithographic problems are expected.

4.2. D e s i g n

The surface at the epi/epipoly interface will always show a step due to the preference of DCS to decompose at the monocrystalline silicon, rather than at the poly. In order to have the design fabricated in a layer of uniform thickness, the area close to the interface should not be used as the device area. When epipoly growth is combined with monocrystalline silicon the epipoly areas themselves should not be larger than needed, since the growth temperature in the centre of the epipoly areas will always be higher than at the rest of the wafer due to the thermal insulation properties of the sacrificial oxide.

5. Applications

Several epipoly sensor and actuator structures have been fabricated. One of them is a thermally actuated indicator. The

Fig. 13. SEM photograph of an epipoly accelemmeter structure.

device consists of a cross which is normally used as a strain- measurement device as in Fig. 1 (a) . The vertical beam of this cross is suspended by two horizontal beams. One of the horizontal beams is connected above the centre of the vertical beam, the other below. A current through the horizontal beams induces their thermal expansion, causing the vertical beam to rotate around its centre. The simplicity of the device makes it ideal for monitoring process problems such as stick- ing and stress. A device with a beam length of 200 t~m, beam width of 4 ~m and beam offset of 8 ~m is shown in Fig. 12. The tip defection is 6 ~m for a supply voltage of 15 V. The close-up of the tip in Fig. 12(d) shows no, or a very low, stress gradient.

A second device which was fabricated to show the feasi- bility of the epipoly process was an accelerometer structure shown in Fig. 13. This device has been electrostatically actuated.

6. Conclusions

. . . . . . . , . . . . . . . . . . . . . , , , ,

Fig. 12. Thermally actuated indicator beam: (a) device photograph; (b) tip deflection at 0 V supply; (c) tip deflection at 15 V supply, (d) close-up of the tip showing no, or a very low, stress gradient.

A range of experiments has been performed to develop a low-stress polysilicon film deposited in an epitaxial reactor. This layer had to be compatible with the already existing bipolar fabrication process to allow monolithically integrated smart-sensor fabrication in the future. The influence of poly seed layers, growth temperature, gas composition, sacrificial layer thickness, doping and post-deposition treatment was investigated. It has been found that the properties of the poly seed layers, the growth temperature and doping type do not influence the mechanical properties of the layer dramatically, although the resistivity decreases for a higher growth tem- perature. During epi and epipoly growth no HC1 should be added to the gas mixture since HC1 leads to a higher growth- rate reduction of the epipoly than that of the monocrystalline silicon due to the larger surface area of the poly. The standard epi growth conditions for the bipolar process lead to good mechanical and electrical properties of the epipoly. The opti- mum growth conditions from a compatibility point of view are: temperature 1050°C, pressure 60 tort, DCS 360 slm, no

644 P.T..I. Gennissen et aL / Sensors' and Actuators A 62 ( 1997) 636-645

HC1, 2 min in situ prebake at 1000°C in hydrogen, dope with 1 × 10 ~6 cm -3 arsenic.

Special care must be taken to prevent the occurrence of compressive mechanical stress when the layer is taken through the rest of the fabrication process. It was found that during oxidation steps oxygen can penetrate into the layer, thereby causing compressive stress. Oxygen penetration is prevented by shielding the layer with a nitride film. This method is similar to a standard LOCOS process. A further advantage of this method is that the epitaxial layer becomes thinner during the oxidizing steps in the rest o f the fabrication process, while the thickness of the epipoly layer remains the same. This can be used to compensate for the difference in growth rate between the epi and the epipoly layer. Doping of the layers is achieved by implantation before nitride capping.

When the epipoly layer is grown on large areas of thick sacrificial oxide, the surface becomes convex because the temperature in the centre o f the epipoly area is higher than at the edge. For practical MEMS structures this is not expected to be a problem since these are limited in size. A small area directly at the epi/epipoly interface cannot be used for device fabrication because of local thickness non-uniformity at this interface. Alignment marks for lithography are preferably fabricated after the epipoly steps, but this is only possible when no buried layers are used. Since the epipoly surface is very rough, the use of a photoresist which absorbs scattered light is recommended.

PSG and LTO are not suitable as a sacrificial layer in this epipoly process, since these layers are not stable at the high deposition temperatures used for epipoly, The LTO suffers from delamination, and outgassing of PSG causes polysilicon bubbles. TEOS oxide is an alternative to thermal oxide and this will be the subject of further investigations.

Acknowledgements

The authors wish to thank the staff and processing crew of DIMES Technology Centre for assistance in fabricating the devices. This work is supported, in part, by the Dutch Tech- nology Foundation (STW), project DEL 44.3578.

[4] P. Lange, M Kirsten, W. Riethmtiller, B. Wenk, G. Zwicker, J.R. Morrante, F. Ericson and J.A. Sehweitz, Thick polycrystalline silicon for surface micromechanical applications: deposition, structuring and mechanical characterization, Tech. Digest, 8th Int. Con, If Solid-State Sensors and Actuators (Transducers '95/Eurosensors IX), Stockholm, Sweden, 25-29 June, 1995, Vol. 1, pp. 202-205.

[5] B. Wenk, J. Ramos-Martos, M. Fehrenbach, P. Lange, M. Offenberg and W. RiethmUller, Surface micromachined accelerometer with increased working capacitance and force feedback operation, in H.C. de Graaff and H. van Kranenburg (eds.), Proc. ESSDERC '95. The Hague, The Netherlands, 1995, Editions Frontieres, pp. 243-346.

[6] P.J. French, B.P. van Drie~nhuizen, D. Poenar, J.F.L. Goossen, R. Mallre, P.M. Sarro and R.F. Wolffenbuttel, The development of a low- stress polysilicon process compatible with standard device processing, 1EEE Z Microelectromeeh. Syst., 5, (1996) 187-196.

[7] B.P. van DrieSnhuizen, J,F,L. Goossen, P.J. French and R.F. Wolffenbuttel, Comparison of techniques to measure both compressive and tensile stress in thin fihns, Sensotw andActuators'A, 37-38 ( 1993 ) 756-765.

[8] L. Lin, R.T. Howe and A.P. Pisano, A passive, in situ micro strain gauge, Proc. IEEE MEMS Workshop (MEMS '93), Fort Lauder~kde, FL, USA, 1993, pp. 201-206.

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Biographies

P a u l G e n n & s e n received his M.Sc. degree in electrical engineering from Delft University o f Technology, Delft, The Netherlands, in 1993. In the same year he worked for six months for E G & G ICsensors Inc., Milpitas, CA, USA. In 1994 he did a postgraduate study on silicon microstructures. Since 1995 he has been at the Laboratory for Electronic Instrumentation, Delft University o f Technology, working towards a Ph.D. degree in the field of micromachining tech- nology for smart sensor applications.

References

[1 ] K. Ohwada, Y. Negoro, Y. Konaka and T. Oguchi, Groove depth uniformization in (110) Si anisotropic etching by ultrasonic wave and application to accelerometer fabrication, Prec. IEEE MEMS Workshop (lvIEMS '95), Amsterdam, The Netherlands, 1995, pp. 100-105.

[2] M. Kirsten, B. Wenk, F. Ericson, J.A. Schweitz, W. Riethmiiller and P. Lange, Deposition of thick doped polysilicon fihns with low stress in an epitaxial reactor for surface rnicromaehining applications, Thin Solid Films, 259 (1995) 181-187.

[3] M. Offenberg, F. L~irmer, B. Eisner, H. Mtinzel and W. Riethmtiller, Novel process for a monolithic integrated accelerometer, Tech. Digest, 8th hff. Golf Solid-State Sensors and Actuators (Transducers '95/ Eurosensors IX), Stockhohn, Sweden, 25-29 June, I995, Vol. 1, pp. 589-592.

M. B a r t e k was born in Trnava, Slovakia, in 1965. He received his M.Sc. degree (cure laude) in electrical engi- neering from the Electrical Engineering Department o f the Slovak Technical University, Bratislava, Slovakia, in 1988, and his Ph.D. degree from the Delft University of Technol- ogy, The Netherlands, in 1995, where he was engaged in the subject of selective epitaxial growth for smart silicon sensor applications. Currently, he is a research assistant at the Lab- oratory for Electronic Instrumentation, Delft University of Technology, The Netherlands, and his work deals with tech- nological aspects of integrated silicon sensor systems.

P a d d y F r e n c h received his B.Sc. in mathematics and M.Sc. in electronics from Southampton University, UK, in 1981

P, T.J. Gennissen et al. / Sensors and Actuators A 62 (1997) 636-645 645

and 1982, respectively. In 1986 he obtained his Ph.D., also from Southampton University, which was a study of the pie- zoresistive effect in polysilicon. After 18 months as a post- doctoral fellow at Delft University, The Netherlands, he moved to Japan in 1988. For three years he worked on sensors for automotive applications at the Central Engineering Lab- oratories of Nissan Motor Company. He returned to Delft University in May 1991 and is now a staff member of the Laboratory for Electronic Instrumentation with interests in micromachining and process optimization related to sensors.

Pasqualina M. Sarro received the Laurea degree in solid- state physics from the University of Naples, Italy, in 1980. From 1981 to 1983, she was a post-doctoral fellow in the Photovoltaic Research Group of the Division of Engineering, Brown University, RI, USA. In 1987, she received the Ph.D. degree in electrical engineering at the Delft University of Technology, The Netherlands. Since then, she has been with the Delft Institute of Microelectronics and Submicron Tech- nology (DIMES) at Delft University, where she is respon- sible for research on integrated silicon sensors and microsystems technology.