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EDK BFM SimulationTutorial

UG254 (v1.0) July 18, 2006

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Xilinx is disclosing this Document and Intellectual Property (hereinafter the Design) to you for use in the development of designs to operate on, or interface with Xilinx FPGAs. Except as stated herein, none of the Design may be copied, reproduced, distributed, republished, downloaded, displayed, posted, or transmitted in any form or by any means including, but not limited to, electronic, mechanical, photocopying, recording, or otherwise, without the prior written consent of Xilinx. Any unauthorized use of the Design may violate copyright laws, trademark laws, the laws of privacy and publicity, and communications regulations and statutes. Xilinx does not assume any liability arising out of the application or use of the Design; nor does Xilinx convey any license under its patents, copyrights, or any rights of others. You are responsible for obtaining any rights you may require for your use or implementation of the Design. Xilinx reserves the right to make changes, at any time, to the Design as deemed desirable in the sole discretion of Xilinx. Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made. Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design. THE DESIGN IS PROVIDED AS IS WITH ALL FAULTS, AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU. YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE, WHETHER GIVEN BY XILINX, OR ITS AGENTS OR EMPLOYEES. XILINX MAKES NO OTHER WARRANTIES, WHETHER EXPRESS, IMPLIED, OR STATUTORY, REGARDING THE DESIGN, INCLUDING ANY WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND NONINFRINGEMENT OF THIRD-PARTY RIGHTS. IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL, INDIRECT, EXEMPLARY, SPECIAL, OR INCIDENTAL DAMAGES, INCLUDING ANY LOST DATA AND LOST PROFITS, ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN, EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN, WHETHER IN CONTRACT OR TORT OR OTHERWISE, WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN. YOU ACKNOWLEDGE THAT THE FEES, IF ANY, REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY. The Design is not designed or intended for use in the development of on-line control equipment in hazardous environments requiring failsafe controls, such as in the operation of nuclear facilities, aircraft navigation or communications systems, air trafc control, life support, or weapons systems (High-Risk Applications). Xilinx specically disclaims any express or implied warranties of tness for such High-Risk Applications. You represent that use of the Design in such High-Risk Applications is fully at your risk. 2006 Xilinx, Inc. All rights reserved. XILINX, the Xilinx logo, and other designated brands included herein are trademarks of Xilinx, Inc. PowerPC is a trademark of IBM, Inc. All other trademarks are the property of their respective owners.

Revision HistoryThe following table shows the revision history for this document.Date 07/18/06 Version 1.0 Initial Xilinx release. Revision

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UG254 (v1.0) July 18, 2006

Table of ContentsPreface: About This GuideAdditional Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Typographical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Online Document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

EDK BFM Simulation TutorialEDK BFM Install . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Getting Started with BFM Simulation of Processor IP . . . . . . . . . . . . . . . . . . . . . . . . . 9 Using GNU m4 to Generate BFM Stimuli . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 BFM Simulation of OPB PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

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Preface

About This GuideThis tutorial is an introduction to using EDK Bus Functional Model (BFM) simulation to verify existing processor IP cores. The tutorial contains four sections: EDK BFM Install covers installation of the les needed for EDK BFM simulation. Getting Started with BFM Simulation of Processor IP is an introduction to EDK BFM simulation. The BFM simulation uses the OPB GPIO core. Using GNU m4 to Generate BFM Stimuli is a tutorial on the use of m4 to generate BFL, for those readers who would like to generate their own BFL stimuli. BFM Simulation of OPB PCI illustrates a BFM simulation of OPB PCI conguration, reinforcing BFM simulation concepts.

The online tutorial les are located at: http://www.xilinx.com/bvdocs/desles/ug254.zip

Additional ResourcesTo nd additional documentation, see the Xilinx website at: http://www.xilinx.com/literature. To search the Answer Database of silicon, software, and IP questions and answers, or to create a technical support WebCase, see the Xilinx website at: http://www.xilinx.com/support.

ConventionsThis document uses the following conventions. An example illustrates each convention.

TypographicalThe following typographical conventions are used in this document:Convention Courier font Meaning or Use Messages, prompts, and program les that the system displays Literal commands that you enter in a syntactical statement Example speed grade: - 100

Courier bold

ngdbuild design_name

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Convention

Meaning or Use Commands that you select from a menu Keyboard shortcuts Variables in a syntax statement for which you must supply values

Example File Open Ctrl+C ngdbuild design_name See the Development System Reference Guide for more information. If a wire is drawn so that it overlaps the pin of a symbol, the two nets are not connected. ngdbuild [option_name] design_name

Helvetica bold

Italic font

References to other manuals

Emphasis in text An optional entry or parameter. However, in bus specications, such as bus[7:0], they are required. A list of items from which you must choose one or more | Separates items in a list of choices

Square brackets

[ ]

Braces

{ }

lowpwr ={on|off} lowpwr ={on|off} IOB #1: Name = QOUT IOB #2: Name = CLKIN . . . allow block block_name loc1 loc2 ... locn;

Vertical bar

Vertical ellipsis . . . Horizontal ellipsis . . .

Repetitive material that has been omitted

Repetitive material that has been omitted

Online DocumentThe following conventions are used in this document:Convention Meaning or Use Cross-reference link to a location in the current document Cross-reference link to a location in another document Hyperlink to a website (URL) Example See the section Additional Resources for details. Refer to Title Formats in Chapter 1 for details. See Figure 2-5 in the Virtex-II Platform FPGA User Guide. Go to http://www.xilinx.com for the latest speed les.

Blue text

Red text Blue, underlined text

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EDK BFM Simulation TutorialEDK BFM InstallThe les needed to run Bus Functional Model Simulation in EDK are installed and tested in this section using the following outline. Install the les needed to run a BFM simulation Identify the directory structure of BFM les within EDK Run BFM simulations on an existing PIP core

EDK BFM simulation of PIP Cores is supported using ModelSim and NcSim simulators, and runs on Linux and Windows operating systems. The instructions in this application note are most often given using Windows and ModelSim environment. If assistance is needed adapting the instructions for use with Linux/NcSim, please contact Xilinx. Unless specied otherwise, the commands in this application note are executed at the command/Linux prompt. EDK BFM simulation allows simulation of bus transactions on either the Processor Local Bus (PLB) or On-Chip Processor Bus (OPB), IBM CoreConnect buses. A license is available from http://www.xilinx.com/ipcenter/processor_central/register_coreconnect.htm

/gnu/m4/bin/nt/ - gen_b_do, gen_b_do /gnu/m4/ - proc_defs_opb.m4, proc_defs_plb.m4

/hw/XilinxBFMInterface/pcores - BFM simulation models

Figure 1-1:

BFM Installation directories

The UG254.zip le contains install_les, m4_exercises, and design directories. Figure 1-1 provides the BFM installation directories within EDK. Run the following steps. All les are provided in ug254.zip. 1. 2. Run bfm_8.1.exe, a self-extracting ZIP le, from the command prompt. Verify that the $XILINX_EDK/hw/XilinxBFMinterface/pcores directory contains the BFM models. Verify that $XILINX_EDK/bin/nt/xilbfc.exe exists.

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3. 4.

Copy edk_bfm.zip to the $XILINX_EDK (%XILINX_EDK%) directory. UnZIP edk_bfm.zip. Verify that $XILINX_EDK/gnu/m4 contains the proc_defs_opb.m4 and proc_defs_plb.m4 les, and that $XILINX_EDK/gnu/m4/bin/nt contains m4.exe. m4 is generally available in Linux distributions, so it does not need to be installed. Verify that the $XILINX_EDK/hw/XilinxBFMinterface/pcores/xil_bfm_v1_00_a/hdl/vhd l directory contains the xil_bfm_pkg.vhd le. Add $XILINX_EDK/gnu/m4/bin/nt to $PATH. Invoke XPS and (re)compile the Unisim, Simprim, XilinxCorelib, and Smartmodel libraries. This is needed so that the BFM models are compiled into the BFM libraries. Select Simulation Compile Simulation Libraries. Select the simulator and HDL. When prompted by the GUI, enter the path to the libraries as shown in Figure 2 and click Compile.

5.

6. 7.

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Figure 2: 8.

Compiling Simulation Libraries

Verify that the modelsim.ini just created in the EDK_Lib directory contains the opb_bfm and plb_bfm libraries. The content of this modelsim.ini needs to be included in the active modelsim.ini le. If there are no special libraries in the currently active modelsim.ini, this is done by copying EDK_Lib/modelsim.ini to $MODEL_TECH/win32. Note: If this modelsim.ini does not have the following libraries, add them:std = $MODEL_TECH/../std ieee = $MODEL_TECH/../ieee verilog = $MODEL_TECH/../verilog vital2000 = $MODEL_TECH/../vital2000 std_developerskit = $MODEL_TECH/../std_developerskit

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EDK BFM Install

synopsys = $MODEL_TECH/../synopsys modelsim_lib = $MODEL_TECH/../modelsim_lib

To use the PPC405 Smartmodel, uncomment/comment lines in modelsim.ini as below.libsm = $MODEL_TECH/libsm.sl libswift = $LMC_HOME/lib/pcnt.lib/libswift.sl ; Veriuser = veriuser.sl

9.

Create the edk_bfmsim_tutorial/m4_exercises directory,

10. enter m4 at the command prompt. 11. Enter Hi Mom. m4 echoes Hi Mom. 12. Enter m4exit. 13. Change to the edk_bfmsim_tutorial/opb_gpio/bfmsim directory. Briey read the contents of the following les used in BFM simulation:pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio_tb.vhd scripts/run.do scripts/m4/opb_gpio_defs.m4 (opb_gpio.m4)

14. Since ISE libraries (Unisim, Simprim, Coregen) were compiled in step 7, the opb_gpio/simgen.opt le does not need the -X option. Verify that the -E argument in simgen.opt points to EDK_Lib. From the opb_gpio/bfmsim directory, run: simgen -f simgen.opt This creates the simulation models for OPB GPIO. 15. Change to the opb_gpio/bfmsim/simulation/behavioral directory. Optionally remove all EDK libraries in the bfm_system.do le already mapped in the modelsim.ini le. To do this, remove lines containing duplicated EDK maps (usually 731) in bfm_system.do. Add the following lines to the beginning of the bfm_system.do le:vlib xil_bfm_v1_00_a vmap xil_bfm_v1_00_a xil_bfm_v1_00_a vcom -93 -work xil_bfm_v1_00_a $XILINX_EDK/hw/XilinxBFMinterface /pcores/xil_bfm_v1_00_a/hdl/vhdl/xil_bfm_pkg.vhd

Use the hard-coded path for $XILINX_EDK (e.g., C:/EDK8.1). 16. From the opb_gpio/bfmsim/simulation/behavioral directory, comment or remove the C_AR0_BASEADDR/C_AR0_HIGHADDR generics from my_core_wrapper.vhd le. To do this, add comments to lines 54, 55, 97, 98, and remove the semicolons on lines 53, 96. 17. From the opb_gpio/bfmsim/scripts/m4 directory, run from the command prompt: gen_bfl_do opb_gpio This creates the opb_gpio.bfl and opb_gpio.do les, and moves them up one directory to the scripts directory. 18. Invoke ModelSim. From the opb_gpio/bfmsim/simulation/behavioral directory, run: do ../../scripts/run.do

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This errors out since the wave.do isnt complete. Add signals of interest to the waveform viewer, save the wave.do, and re-run. 19. Verify that the simulation results are displayed in the waveform viewer. 20. Make a change to the value of a generic, and rerun the simulation. From opb_gpio/bfmsim/scripts/m4, change the C_IS_DUAL generic in opb_gpio_defs.m4. 21. Run: gen_bfl_do opb_gpio In the VHDL testbench, change the C_IS_DUAL generic in opb_gpio/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio_tb.vhd on line 107. 22. In ModelSim, from opb_gpio/bfmsim/simulation/behavioral, rerun: do ../../scripts/run.do

Getting Started with BFM Simulation of Processor IPThe OPB GPIO Processor IP core is simulated in this section using the following outline: A. Identify when stimuli are provided and checked from the OPB side B. Identify when stimuli are provided and checked from the I/O side C. Describe the synchronization used to transfer control between the BFL and the VHDL in BFM simulation Figure 3 is a functional diagram of BFM simulation of a Processor IP core. The BFM is modeling the microprocessor either PPC405 or MicroBlaze which is communicating to the Processor IP using either the PLB or OPB. The VHDL testbench interfaces to the Processor IP core ports, which connect to external pins on the FPGA, GPIO_IO_I, and GPIO_IO_O. The C_IS_DUAL generic denes whether a single or dual GPIO is included in the core. When congured as a single GPIO, the two registers in the OPB GPIO are DATA and TRI, located at C_BASEADDR + 0x0 and C_BASEADDR + 0x4, respectively.

BFM

Processor IP

VHDL Testbench

ug254_02_051706

Figure 3:

BFM Simulation

Run a BFM simulation of the OPB GPIO using the steps below. 1. Briey read the following les:opb_gpio/bfmsim/pcores/opb_gpio_v3_01_b/hdl/vhdl/opb_gpio_tb.vhd opb_gpio/bfmsim/scripts/m4/opb_gpio_defs.m4 opb_gpio/bfmsim/scripts/m4/opb_gpio.m4

The VHDL testbench, opb_gpio_tb.vhd, provides stimuli to and checks results from the I/O side. The two m4 les, opb_gpio_defs.m4 and opb_gpio.m4, provide stimuli to and check results from the microprocessor side. The opb_gpio_defs.m4 le provides the symbolic names and addresses for the registers in the OPB GPIO core.

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In the next steps, use the waveform viewer to verify the content of the DATA and TRI registers. 2. From the edk_bfmsim_tutorial/opb_gpio/bfmsim/simulation/behavioral directory, run: do ../../scripts/run.do 3. As illustrated in Figure 4, verify the reset operation. Reset is done from the OPB side. Verify that from 450 ns to 650 ns, the BFM lines read 0x00000000 and 0xFFFFFFFF in the DATA and TRI registers. Control is transferred to the VHDL testbench, which writes the status message to the simulator transcript window indicating that the reset operation is performed.

ug254_03_051706

Figure 4: OPB GPIO Reset

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4.

As illustrated in Figure 5, verify the read operation. From 350 ns to 650 ns, opb_gpio.m4 prompts the VHDL testbench to generate input stimuli into GPIO_IO_I. The synchronization pulses occur at 350, 450, 550, and 650 ns. The 0xFFFFFFFF, 0x00000000, 0xFFFFFFFF, and 0x00000000 input stimuli are generated by the testbench at 360, 460, 560, and 660 ns. Control is transferred to the BFL, and the BFM veries that the data register contains the data received from the GPIO_IO_I inputs at 410, 510, 610, and 710 ns. Control is transferred between the BFM and VHDL by the pulses on synch_in/synch_out at the top of the waveform viewer.

ug254_04_051706

Figure 5: 5.

OPB GPIO Read Operation

As illustrated in Figure 6, verify the write operation. From 750 ns to 1000 ns, the simulation veries that the GPIO writes data correctly to the GPIO_IO_O outputs. The opb_gpio.m4 writes 0x00000000, 0xFFFFFFFF, and 0x00000000, at 770, 860, and 940 ns. The opb_gpio_tb.vhd veries this data at the GPIO_IO_O output pins.

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Figure 6:

OPB GPIO Write Operation

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6.

As illustrated in Figure 7, verify the interrupts in the OPB GPIO. From 1660 ns to 2000 ns, the simulation veries that the interrupts function correctly. In the GPIO, an interrupt is generated when there is a change in input value on the GPIO_IO_I pin. The Interrupt Service Register (ISER) is reset at 1580 ns. The BFM receives an interrupt at 1840 ns. The BFM reads the ISR at 1940 ns.

ug254_06_051706

Figure 7: OPB GPIO Interrupts 7. (Optional) Add code to opb_gpio.m4 and opb_gpio_tb.vhd to write 0xF0F0F0F0 from the OPB, check results at the GPIO_IO_0, and display a message indicating the test done. (Optional) Add code to opb_gpio.m4 and opb_gpio_tb.vhd to generate 0xFFFF00000 at GPIO_IO_I, check the results, and display a message indicating the test done.

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Using GNU m4 to Generate BFM StimuliThe rst step in understanding BFM stimuli is to read the core_defs.m4 and core.m4 les for several cores. Much of the m4/BFL stimuli is based on the following two commands: read_word(register_symbolic_name, expected_value) write_word(register_symbolic_name, write_value) This section provides exercises to understand the details of m4. Arecommended prerequisite is reading completed m4 les of existing Processor IP cores. The GNU m4 macro processor generates Bus Functional Language (BFL) stimuli for simulation using Bus Functional Models (BFMs). The tasks in this section are given below. Run GNU m4 interactively and in batch mode Read m4 constructs used in generation of BFM stimuli Read m4 constructs used to verify stimuli generated by HDL Generate BFM stimuli using m4

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core_defs.m4

.m4

m4

BFC

core.do

Simulator

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Figure 8: Generating BFM Stimuli Figure 8 shows the ow for generating BFM stimuli. Stimuli in m4 is easier to read and write than stimuli in BFL or do les. One obstacle in learning m4 is getting accustomed to reading and writing the forward and backwards ticks, and interpreting their use. The m4 interactive mode is a good method for learning m4. Change to the edk_bfmsim_tutorial/m4_exercises directory, enter m4, and run the following commands in interactive mode. 1. 2. 3. 4. 5. 6. 7. Generate the concatenation of 00000000 and FFFFFFFF.00000000`FFFFFFFF

Find the length of the string Xilinx.len(`Xilinx)

Find the index number of the rst occurrence of the string li in the string Xilinx.index(`Xilinx,`li)

Write the string yo in Toyota using the substr macro.substr(`Toyota,2,2)

Replace the X character in Xilinx with Z.translit(`Xilinx,`X,`Z)

Run incr(4). Find the results of the following arithmetic macros.eval(-3*5) eval(eval(2+4)*2) eval(5+5,16) eval(5+5,16,8) eval(5+5,2)

8.

Run the following macros by rst including the proc_defs_opb.m4 le. The proc_defs_opb.m4 le is used in exercises 7-15.include(`proc_defs_opb.m4) make_num

9.

Run the following macros.strip_hex(0xFFFFFFFF) strip_hex(make_num) strip_hex(make_num)`strip_hex(make_num) make_num`make_num

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10. Run the following macros.define(`C_BASEADDR, `0x30000000) add_offset(C_BASEADDR, 0x10C)

11. Run the following macros.calc_be(0x00000004,word) calc_be(0x00000004,halfword) calc_be(0x00000004,byte)

12. Run the following codes.def_reg(`CAP,` 0x3000010C) CAP

13. Run the following macros.read_word(0x0000000C, 0x12345678) read_word(0x0000000A,0x12345678, `req_size=4, req_delay=5) read_half(0x0000000A, 0x12345678) read_byte(0x00000005, 0x12345678) write_word(0x0000000C,0x12345678) write_word(0x000000A, 0x12345678,`req_size=4,req_delay=5) write_half(0x0000000A, 0x12345678) write_byte(0x00000005,0x12345678)

14. Run the following macros.forloop(i,0,2,`eval(i) ) forloop(i,0,2,`eval(i) ) foreach(i,(1,5,17,4), `eval(i)

15. Run the following macros.assert_in assert start set_dev set_device(device1) set_device(monitor)

16. Run the following code.ALL_ONES_WORD ALL_ONES_BYTE_0 ALL_ZEROES

17. Create the following new macros. (The proc_defs_opb.m4 is not used in these exercises.)define(`go, `hello world) go

18. Create a multiply macro.define (`multiply,`eval(2*4)) multiply define(`multiply,`eval($1*$2)) multiply(2,2)

19. Create a macro called concatenate.define(`concatenate,$1`$2) concatenate(cup,cake)

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20. Run the following m4 batch commands from the m4_exercises directory.m4 m4 m4 m4 my_makenum.m4 ifelse.m4 forloop.m4 interrupt.m4

21. Run the following m4 commands.m4 opb_gpio_defs.m4 m4 opb_gpio.m4 > opb_gpio.bfl Read the file opb_gpio.bfl

22. Run the following m4 command and note the functionality of the divert commands.m4 test_divert.m4

23. Run the following m4 command and note the reset functionality.m4 opb_gpio_reset.m4

24. Change the C_IS_DUAL generic to 1, rerun the command above, and observe the output. 25. Run the following m4 command and describe how stimuli is generated from the IO (not the OPB) side.m4 stimulate_gpio_ins.m4

Note: This illustrates that the BFL must request that the VHDL generate this stimuli. Thesynchronization signals required for this operation are shown.

26. Run the following m4 command and describe how stimuli are generated from the OPB side.m4 stimulate_gpio_outs.m4

27. Change the C_IS_DUAL generic and rerun the command. 28. Run the following command and describe how interrupts are tested in the OPB GPIO.m4 test_gpio_interrupts.m4

BFM Simulation of OPB PCIIn this section, run a BFM simulation of OPB PCI conguration. Analyze the results in the waveform viewer in terms of the VHDL stimuli and BFL stimuli. 1. Optionally read the following three les to determine when stimuli are applied and results are checked.opb_pci/bfmsim/pcores/opb_pci_v1_02_a/hdl/vhdl/opb_pci_tb.vhd opb_pci/bfmsim/scripts/m4/opb_pci.m4 opb_pci/bfmsim/scripts/m4/opb_pci_defs.m4

Table 5, OPB PCI Bus Interface Registers in the OPB PCI Full Bridge Product Specication (DS437) provides register abbreviations and locations. 2. From opb_pci/bfmsim/scripts/m4 directory, rungen_bfl_do opb_pci cd opb_pci/bfmsim/simulation/behavioral do ../../scripts/run.do

3.

In ModelSim, run View Structure View Signals

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4. 5. 6. 7.c_include_pci_config 1 c_bridge_idsel_addr_bit 16 c_num_idsel 1 c_include_devnum_reg 0 opb_clk opb_abus opb_dbus opb_rnw opb_be opb_select pci_xferack pci_toutsup ad FFFFFFFF cbe F idsel idsel_int idsel frame_n trdy_n irdy_n stop_n devsel_n0000 00000000

Add the generics, and OPB and PCI Bus signals to the waveform viewer. Add V3 signals to the waveform viewer. Run the simulation and determine the simulation time at which the PCI bus is reset. Determine the simulation time at which the CSR is written.

3000010C 04000080

3000010C 00000000

30000110 00000000

00000000 00000000

30000110

00000000

FFFFFFFF

1111

0000

1111

0000

1111

0000

1111

FFFFFFFF

00010004

FFFFFFFF

FFFFFFFF

02000000

FFFFFFFF F

F

A

0

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Figure 9:

Conguring the OPB PCI

Figure 9 shows the waveform viewer output from a simulation of the conguration of the OPB PCI. The simulation time shown is 2000 ns 3000 ns. This illustrates the bus transaction that writes the Command Status register in the OPB PCI core.

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