Basic digital logic J. Christiansen, CERN - EP/MIC [email protected]

Basic digital logic

J. Christiansen,

CERN - EP/MIC

[email protected]

December 2003 J.Christiansen/CERN 2

General digital functions

Any digital function can be made from this structure• Logic: Logical operations

– And, Or, Additions, Multiplications, Divisions, etc.

• Memory: Storage of variables and state– Latch, Flip-Flops, registers, register files, SRAM, DRAM, ROM, etc.

Mixed signal design: Both digital and analog functions on same IC / board

Logic MemoryADC DACAnalog Analog


Logic

Logic built from basic building blocks: GatesName Function Truth table Symbol

And

Others: Nand, Nor, Exclusive or, Multiplexer, Tristate, Full adder, Buffers, etc.

a x b

ab

0

1

0 1

0

0 1

0

Or a + b

ab

0

1

0 1

0

1 1

1

Inversion a

a

0

1

1

0

a

b

a

b

a


Memory elements

Storage of a logic value for a give time period

D

L

Q

Latch

1

1

Q

0

1

D L

0

1

X 0 Q

Flip-Flop

Q

0

1

D C

0

1

X QLevel sensitive Edge sensitive

Clock

D Q DL

Q DL

Q

Master – slavelatch

Memoryarray

DecodingAddress

Rd/wr

Data

MemoriesRAM: Random Access MemorySRAM: Static RAMDRAM: Dynamic RAMFLASH: “Permanent” RAM (no power needed)ROM: Read Only MemoryPROM: Programmable ROMEPROM: Erasable PROM (with UV light)EEPROM: Electrical Erasable PROMDPM: Dual Port MemoryFIFO: First In - First OutAddress decoding normally

divided in row and collumn decoding


Logic optimization

• Reduction of logical expressions: (~ = inversion)– a x (b x c) = (a x b) x c = abc; a + (b + c) = (a + b) + c = a+b+c– a + ~a = 1; a x ~a = 0– a x (b + c) = ab + ac; a + (b x c) = a + bc (no reduction)– ~(a + b) = ~a x ~b; ~(a x b) = ~a + ~bEg. ~a~b~c~d + ~ab~c~d = ~a~c~d x ( ~b + b ) = ~a~c~d x ( 1 ) = ~a~c~d

Heavy and tedious

• Reduction using graphical Karnough maps– Basic product terms:

~a~b~c~d + ~ab~c~d + ~ab~cd + ~abc~d + abcd + abc~d + a~bcd + a~bc~d

– Reduced expression: ~a~c~d + ~ab~c + ac + bc~d = ~a~c x (~d + b) + c x (a + b~d)

Quick and elegant, but for more than four variables it gets complicated

• Today: Logic synthesisOnly one bit changing

c,d

10

01

00

11

10

110100a,b

1

1

0

0

0

1

0

0

0

0

1

1

0

1

1

1

Alternative:bc~d or ~ab~d


Which gates are really needed ?

• How many different types of gates are needed to implement any given logical function ? :

Inv

And

Or

So why is this not used in practice ?Too slow or too large areaDifferent drive capabilities also needed (buffers)

Memory elements can also be made from this


Implementing logic with memories ?

• RAM or ROM can be used to implement logic operations: Look Up Table (LUT)

Logic

Map any given combination into required output

Inputs Output

--0000 0--0001 0--0010 1--0011 1--0100 0-------- ---1111 0

Address(input)

Data(output) Address decoding logic + memory array

used to implement required function

For most applications Look up tables not efficient (size and speed)

Special applications:Special encoders/decodersProgrammable logic in FPGA’s


Timing of digital circuits

Load

Delay Gate delay depends on:Type of gateNumber of inputsWhich inputTransition ( 0 -> 1 or 1 -> 0 )Output loadInput slew rateTemperatureSupply voltageProcess parametersTechnology

Gates

Sequential circuits

Clock

D Q

Setup: Input data must have stabilized certain time before clock

Hold: Data must not change within certain time after clock

Clock

DataTimingrequirements


Timing examples

• Data arriving too late (too long logic delay)

• Data arriving too early (clock skew problem)

• Asynchronous input signal (meta-stability problem)

D Q D QLogic

Clk

Q

D

Logic delay

D Q D Q

Clk1

DFlip-flop delay

delay Clk2

D Q

Clk

Clk

Clk

Data from asynchronous system

Delay

Sample point

Sample point

Output finally resolves to 0 or 1


Wires also have delays

• Capacitive loading of gate (affects gate delay but can not be considered a wire delay)

• Propagation delay because of distributed L-C– Wire has delay.– Wire has characteristic impedance which may cause reflections.– Normally not important inside chips but must be taken into account for

signal exchange between chips.– If wire resistance also signal attenuation

• R-C delays– Thin wires have resistance and capacitance– Gives wire delay

Reduces signal slew rateComplicated delay calculation for wire networks

Z


Logic values

• Digital logic only works with Logic 0 and Logic 1• Logic values represented by voltages

"1"

VOH

VOL

"0"

VIH

VIL

Undefinedregion

Noise MarginHigh

Noise MarginLow

+V +V

0 0

Output Input

NoiseCrosstalkVoltage drops


State machines• Used to go through sequence of events

based on inputs. State evaluation/change every clock cycle.

• Best represented by state transition diagrams.

• Implemented with state memory (flip-flops) and state transition logic.

• Different encodings:– Binary ( 000, 001, 010, 011, 100, )– Gray code

Only one bit changes in any state transition

– One hot ( 001, 010, 100)One and only one bit actively set (fast)

– Counters are a type of state machine with simple algorithmic state transitions.

A

B

C D

E

01

2

345

6

7

Counter

Stateregister

State Transition

logic

Inputs

Clock

Reset


Pipelining

• A Pipeline is used to increase operating speed of a digital circuit:– Increases operation frequency– Increases Latency (slightly)

LogicS

torage

Clock

LogicD

Storage

LogicCS

torageLogic

B

Storage

LogicA

Storage

A B C D

tlogictstor

F1 = 1 / ( tlogic + tstor )

Latency1 = tlogic + tstor

F2 = 4 x F1

Latency2 = Latency1 + 3x tstor

Clock

Wave pipelining: Use delays as short term data storage


Data processing

• In data processing applications a separation is normally made between the real data processing and the control of the processing.– Data path:

Data exchange (data busses, data multiplexers, etc.), Data storage (memory, pipeline, register file, etc.), Data processing ( additions, multiplications, shifts, etc.)

– Control: State machines that determines the control of the of the data path

Control

Unit 1

Unit 2

Unit 3Unit 4

CommandStatus

Data path

Registerfile

Address generation path


Data path control

• State machines (used in hardwired RISC processors)

• Micro code (used in CISC processors)

A

B

C D

E

AB

C D

E

B

B

B

Micro code memoryCommand

Data path status Data path control

Address Data

Clock

Command

(Strongly simplified)


Digital implementation

Type Year Comment

Transistors 50

Descreete logic 60 - 80 TTL, FAST, ECL, NMOS, CMOS

PAL 70 - 80 Programmable, Simple functionality

PLD 80 - 90 Programmable, Limited functionality

CPLD 90 - ? Programmable, Complex logic

FPGA 90 - ? (Re)-Programmable, Very complex logic, Cheap development, Limited large scale production cost

ASIC 80 - ? Very high performance, Very large complexity, Expensive development, Cheap large scale production

DSP/processor 80 - ?

PAL: Programmable Array LogicPLD: Programmable Logic DeviceCPLD: Complex Programmable Logic DeviceFPGA: Field Programmable Gate ArrayDSP: Digital Signal ProcessorASIC: Application Specific Integrated Circuit

Large flexibility, Data processing, Low–high performance

(still used for RF and power)


IC Technologies

• Bipolar:– High speed, Good analog performance, Limited integration

• NMOS:– First MOS ( Metal Oxide Semiconductor ) technology– Limited performance, High static power, Limited integration

• CMOS– Complementary MOS with zero static power– Very high integration– Very high performance in modern CMOS– Frequent introduction of improved technologies (every 2-3 years)– Other improvements:

• BiCMOS: Both Bipolar and CMOS on same chip• SOI (Silicon on Insulator): Isolated devices and lower parasitic capacitances• SiGe (Silicon Germanium): Improved transistor speed by incorporating Ge.

• Exotic: GaAs, HEMT, – Very high speed ( RF, High speed telecommunication, etc.)– Low integration, Low yield


All this is just “simple” binary thinking

There are only 10 types of people in this world:

Those who understand binary

And those who don’t

Documents

Basic digital logic J. Christiansen, CERN - EP/MIC [email protected]