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T his is the digital age. From flashy cell phones,games, PCs, and PDAs to the behind-the-scenesautomotive, medical, and Internet components,progress in digital computing owes much to thesoftware that helps designers create and connect

millions of transistors. But with the trend toward mixed-signalchips in a communications-centric world, everyone is finding theneed for a little bit of analog. As many electronic products getsmaller yet do more, designers face special challenges asthey add analog circuitry to an otherwise digital chip.

Only recently have analog/mixed-signal designers hadany help from electronic design automation (EDA) soft-ware. Now the established EDA vendors and a group of start-upsare competing for a share of the growing analog/mixed-signalchip design business. The result is a steady stream of new tools.

Hottest on the list of new EDA offerings are the so-called ana-log synthesis programs, which offer an automated way to turnspecifications into a working component. Unfortunately, theyare not as well known as their digital counterparts.

Synthesis, which ushered in the modern age of digital design,lets designers describe circuit functions in terms of software code,rather than with symbols and schematics. This code is then com-piled into a list of standard cells, the physical implementation ofa logic function. Then, thanks to automated layout, a stable of engi-neers is no longer needed to place and connect the cells by hand;the computer does the job. With synthesis and automated place-ment and routing, chip designers can cut design cycle time dras-tically—digital chip designers, that is.

For analog designers, it’s a different story. While digitaldesigners are automating the time-consuming grunt work and

focusing on creating more and better electronics, analog design-ers have been doing things the old-fashioned way—manually.But that situation may be changing.

In fact, growing interest in analog/mixed-signal design wasvery much apparent at the International Solid-State CircuitsConference in San Francisco last February. Even digital design-ers packed into sessions on analog and radio frequency circuits,hoping to glean some insights into the integration of high-per-formance analog and digital components on the same chip.

The Semiconductor Industry Association, San Jose, Calif., pre-dicts that nearly 70 percent of all ICs will have analog componentswithin five years, compared with about 25 percent today. For exam-

ple, the much-anticipated short-link wireless technologies,like Bluetooth and IEEE 802.11, need an analog interface atthe sending and receiving end of every device.

Considering that only 2000–2500 analog designers areworking in North America, according to Gary Smith, an EDA ana-lyst with Dataquest Inc., digital designers might be called upon tolearn analog and mixed-signal design skills—attractive commodi-ties in the communications, multimedia, and data storage markets.

Black magic to the rescue

The differences between analog and digital circuits are vast. Dig-ital circuits work by flipping transistors on and off to the statescalled 1 and 0. They can be described in high-level, hardwaredescription languages (HDLs) and then synthesized into stan-dard cells, which can contain multiplexers/demultiplexers, flip-flops, buffers, and logic gates. Digital circuits have a greater immu-nity to noise than analog ones because a range of signal values areassociated with logical 1 and 0 [see figure, p.72]. This noise mar-gin helps to lower performance sensitivity to standard cell place-ment and routing, making automation of those steps possible.

In contrast, analog circuits work by biasing the transistor some-where between what the digital world would call fully on and fully

CHIP DESIGN

Automation ComestoAnalog

BY BETH MARTINContributing Editor

Long overshadowed by the digital world, the black-magic realm of analog design is gaining

the spotlight and acquiring software tools of its own

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off. These circuits don’t come in standardized packages; theymust be sized and tweaked to work properly. Unlike digital cir-cuits, they cannot yet be described in HDL. Instead analog cir-cuits are characterized more along the lines of “give me anamplifier with a gain of 1000, and make it not burn out.” Designautomation tools are not yet smart enough to turn that kind ofdescription into a circuit layout. Analog designers manuallydraw the schematics and connect them so that the transistors stayin the delicate active region. It’s no wonder that building greatanalog circuits is said to involve some amount of black magic.

Because analog designs require skilled craftsmen, who arein short supply, and few parts of the typical analog flow areautomated, the average analog circuit takes longer to imple-ment than its usually much larger digital counterpart. Problemsmultiply if the analog design is destined to be a block on amixed-signal or system chip. But progress is being made,enough to spark a revolution in EDA for analog/ mixed-signal(AMS) designers, who arenow dealing with transistorsin the range of millions.

The analog revolution

Granted, it’s a slow revolu-tion that relies heavily ondesigners adopting newdesign methods. But ahandful of companies aremoving forward in newareas like analog synthesisand physical layout, andothers are improving tradi-tional simulation tools.

“We’re on the cusp of amajor change in the waypeople will do AMS design,”said Rob Rutenbar, aCarnegie Mellon professorof computer engineeringand cofounder of a start-upanalog EDA company, Neo-linear Inc., also in Pitts-burgh. “It’s a very cool timeto be working on hard-coreanalog tools. In the 1980s,we were considered lunaticsin the wilderness. Fifteenyears later, it’s paying off.”

Simulation and layout stages

Simulation is one area where analog designers have been ableto rely on EDA tools, most often those based on Spice, the sim-ulation program developed in the early 1970s at the Universityof California at Berkeley. But these tools are very slow becausethey simulate at the transistor level. With millions of transis-tors involved, they are not practical. The reason is that eventhough most of the transistors in a mixed-signal design areused for the digital component, the entire circuit has to be sim-

ulated to make sure that the analog and digital parts worktogether—an arduous and expensive process.

Mixed-signal chips require mixed-signal simulators to ver-ify the behavior of both digital and analog blocks, as well as theinterfaces between them. Several analog and mixed-signalsimulators are currently on the market, which is dominated byCadence Design Systems Inc., in San Jose [see pie chart, nextpage]. So far, though, none of the simulators meets thedemands of most analog/mixed-signal designers.

Most likely, mixed-signal simulation will increase the use ofmixed-signal HDLs such as Verilog-AMS or VHDL-AMS. Insteadof describing each transistor, these languages would describefunctions or behaviors that include several transistors. They wouldgive the industry a standard format for simulating the behaviorsof groups of transistors rather than of each transistor individually.In the digital world, HDLs were originally used for verifying thebehavior of a design through simulation, but they later became the

standard input to logic syn-thesis tools as well.

After a high-level simula-tion, analog circuits are phys-ically designed with the helpof graphics editors. To theuser, these editors resemble adrawing program, having theequivalent of shapes and clipart that help the layoutdesigner place and connectthe analog transistors. Afterlayout, the analog block issimulated with much moredetailed, transistor-level inputto the simulation software.Complete analog blocks alsoneed to be simulated withinthe context of their largerenvironment, the chip,which presumably includeslots of digital circuitry.

Many users would liketoday’s transistor-level sim-ulators to be faster and han-dle bigger designs. “Theyare comfortable using thetools that they once used todevelop 50 000-transistordesigns,” said Gary Pratt, a

technical marketing manager at Mentor Graphics, inWilsonville, Ore., “and would simply like that extended to theirnew multi-million transistor designs. Unfortunately, many arefinding that this does not exist, despite vendor claims of high-capacity simulators for mixed-signal designs.” The real capac-ity of a simulator varies with the design, speed of the machinesit runs on, degree of accuracy, and simulation time.

This is why mixed-level simulators are so useful. Thedesigner can trade off the accuracy of simulation at the tran-sistor level against the speed of simulation at the behavioral

Threading the Needle Analog design tools must factor in the effect on a device’s output

voltage of small changes in its input voltage, as shown by the IV

curve of an operational amplifier. The steeper the curve, the greater

the sensitivity.

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level by choosing the simulation method appropriate to eachblock. Simulating the whole chip with selected blocks at dif-ferent levels of abstraction—a mix of behavioral, cell-level,and transistor-level models—allows the process to run in a rea-sonable time while verifying the blocks in context of the chip.

But breaking up the system into such levels is no easytask, said Ken Kundert, a specialist in AMS at Cadence DesignSystems. In a session at the Electronic Design Processes Work-shop held in Monterey, Calif., in April, Kundert argued that achip architect must settle on a plan that dictates when and howthe full chip and its blocks are to be simulated.

EDA vendors say that simulation is one area in which tools arenot sufficient if the designers lack a smart simulation strategy.Spokespeople from Mentor, Avant!, and Synopsys agree thatmixed-signal and system-on-chip (SoC) designers must developa top-down design flow to be successful. In a top-down flow, sys-tems are defined at a high level, possibly before any blocks aremade. The specifications for the sys-tem blocks, developed by chip archi-tects, are handed down to the blockdesigners. In the traditional bottom-upflow, each block is created independ-ently, then stitched together on a chip.

Not all analog designers are facedwith AMS. In high-performance ana-log designs, like those coming fromHuibert Verhoeven’s op-amp group atNational Semiconductor in SantaClara, Calif., simulation tools need nothandle mixed-signal or mixed-levelconsiderations, but they do need toaccount for parasitic resistance andcapacitance. Verhoeven’s group isdoing better with traditional bottom-up analog design flows than with top-down flows and automation becausetheir designs have few transistors andmust operate at higher speeds thanautomation tools can deliver. But Ver-hoeven said more tools are becomingavailable for analog components of system-on-chip designs,including automated placement and routing.

Automated placement and routing

Physical layout is the process of turning the symbolicschematic design into a real geometry of transistors, thenplacing the transistors and routing the wiring between them.While mixed-signal simulation and layout editing tools areestablished but young technologies, new tools for automatingother parts of the analog design process are just emerging—like automatic placement and routing. Rather than manuallypushing transistors around on a computer screen, placementand routing would be a pushbutton operation. Given some per-formance constraints, the tool would find the best solution forarranging and connecting the circuits.

But such technology, long standard for digital design, isunproven for analog. For example, a placement and routing

tool from Neolinear is now being evaluated by Philips Semi-conductor, Texas Instruments, Raytheon, Sharp, and ST-Microelectronics. Dubbed NeoCell, the tool offers the onlyautomated analog placement and routing software available.

Anthony Gadient, Neolinear’s vice president of engineer-ing, told IEEE Spectrum that NeoCell automatically places androutes analog cells at least three times as fast—and with equalor greater performance—than manual placement and routing[see figure, p. 74].

But Verhoeven’s op-amp group still relies on a layout editorto manually place and route circuits. He said he would not hes-itate to use an automatic placement and routing tool if it per-formed as well as his designers did.

Sharing the synthesis spotlight

In addition to place and route capability, Neolinear also offers a cir-cuit synthesis tool that automatically sizes analog transistors, a crit-

ical step in getting a working analogcomponent. The size of an analogtransistor determines how it will func-tion with different input voltages. Ifthe transistor is too small, even milli-volts of fluctuations can push it out ofthe active region.

Besides Neolinear, three othercompanies—Barcelona Design, Ana-log Design Automation, and AntrimDesign—have recently come outwith tools billed as analog synthesis.But the companies all seem to have aslightly different interpretation ofwhat, exactly, is meant by that term.None of the offerings resemble thedigital approach of hardware-descrip-tion-language in, netlist out. As longas people are not too picky about themeaning of synthesis, however, ana-log synthesis is definitely here andworking, offering some method ofturning high-level specifications for,

say, operating voltage and speed into a working component. Still skeptical of the whole lot is EDA analyst Gary Smith of

Dataquest (now part of Gartner Inc., Stamford, Conn.). He haslittle confidence in these tools because the design methods to sup-port them are not yet in place. Even so, Smith believes that theywill be useful for retargeting existing chip designs to new man-ufacturing processes, which happens every 12–18 months.

Barcelona Design’s tool, launched in February 2000, isavailable only through the Sunnyvale, Calif.–based company’sWeb site. At the site, the designer is led through the selectionof the manufacturing process and circuit topology to the addi-tion of specifications and performance criteria. The tool thencreates simulation set-up, netlist, schematic, and placementfiles that are intended for use with Cadence Design Systems’analog simulation and custom design tools [see figure, p. 75].

Taking a different tack is Analog Design Automation Inc., inOttawa, which is targeting analog companies with its analog syn-

Cadence Design70%

Mentor Graphics20%

Avant!8%

Other2%

Source:Dataquest

Market Shares in Mixed-Signal SimulationAnalog and mixed-signal simulators are

available from 18 vendors of electronic design

automation tools, but the market is dominated

by Cadence Design Systems.

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thesis technology based on fuzzy logic algorithms. Amit Gupta,president and CEO, said the company’s technology offers a20–25-fold productivity increase over manual methods andresults in higher-quality circuits. It is “Holy Grail technology,”said Gupta, because it addresses the bottlenecks in analogdesign by enabling less-experienced engineers to produce high-quality analog designs.

Analog synthesis definitely can decrease the time betweentopology and schematic 10-fold, compared with the traditionalmanual method, agrees Felicia James, a mixed-signal productdevelopment manager at Texas Instruments in Dallas. It canalso result in a better-quality circuit. Having all that tediousroutine work automated, she said, lets the designers exploretradeoffs and fine-tune the circuit.

At Antrim Design Systems Inc., in Scotts Valley, Calif.,the company’s tool set captures specifications and topologiesand generates detailed analysis, verification plans, and testsuites. Antrim’s strong point is its highly regarded mixed-signal simulator, which is coupled to the synthesis process.Matsushita Electric Industrial Co., Kodoma City, Japan, usedAntrim tools to build single-chip DVD players and cell-phone components.

But along with its benefits, automation software for ana-log requires tradeoffs, not only in circuit performance, butalso in the time needed to learn to use the software and fit itinto the design flow. Designers will need to use the well-worn approach of considering which parts of the design needto be the “best of the best” and do those by hand. “The rest ofthe blocks only need to be very good,” Carnegie Mellon’sRutenbar said, “and tools can do that. You don’t need fullcustom for everything—you need to get it done in sixmonths,” not in two years.

From tools to methodologies

Tool vendors are pushing more than just tools. Everyone agreesthat design methodologies must evolve as well. “Bottom-upanalog design is a bottleneck to completing complex mixed-sig-nal [system-on-chip] designs on schedule,” said Michael Jackson,who heads the West Coast R&D group at Avant! Corp., Fremont,Calif. “The most promising area is the transition from bottom-up analog design to top-down design.”

Texas Instruments’ James said she’s already seeing thatshift occur. More information for the physical design of ana-log blocks comes from the chip-level description. “You used tohave pure circuit designers,” she said, “and the layout personwas pretty separate from the design process.” But now theAMS teams increasingly use the top-down methodologies,which means new job responsibilities for analog engineers.

For EDA to address the needs of AMS designers, EDA ven-dors must work closely with designers to understand the typesof designs in progress, and to help create a coherent method-ology that links the piecemeal tools, emphasized Henry Chang,an architect focusing on AMS issues at Cadence Design Sys-tems. New tools will take a while to catch on, said Chang, andwill be used only incrementally until designers trust and under-stand the limitations of the tool for their design types. There isno one-size-fits-all when it comes to EDA tools, so new designpractices must fill the gaps.

More help on the way

Tools are still behind the curve in noise analysis and other prob-lems—like harmonic distortion—that come with system-on-chip design. “Crosstalk and noise are critical in high-speeddesigns,” said National Semiconductor’s Verhoeven. Analogdesigners must consider noise, drift, temperature coefficients,

jitter, nonlinear responses, and transmission lineissues. Naturally, such disturbances affect thebehavior of the analog circuits. Several compa-nies specialize in developing tools for these aspectsof analog design. For instance, Snaketech Inc., inVoiron, France, which was acquired last year bySimplex Solutions Inc., Sunnyvale, Calif., special-izes in substrate noise.

Another up-and-coming technology thataddresses the demands of analog circuitry is afield-programmable analog array (FPAA) fromAnadigm Ltd., Crewe, United Kingdom. Thetechnology is similar to the field-programmablegate array that is a staple of digital systems. Theengineer uses software to select circuit elementsfrom among 20 analog function blocks and con-nects them so as to perform the desired function.The selections are converted into a data streamand downloaded to the FPAA.

Functions that can be implemented usingFPAA include offset removal, rectifiers, gain stages,comparators, and first-order filters. The designerscan also construct high-order filters, oscillators,pulse-width modulators, and equalizers.

While this technology is very young, and still

Tools like Neolinear’s NeoCell automate the placement and routing of

analog circuits. As with many digital designs, the engineers still do some

routing manually, but automation shortens design time considerably.

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expensive, it could someday be useful for creating communi-cations products that would work on any standard. Forinstance, a cell phone with a reprogrammable analog-to-digi-tal converter would search the entire communications band fora signal, then grab the necessary program from memory tomake itself into a code-division multiple access (CDMA), time-division multiple access (TDMA), or global system for mobilecommunications (GSM) phone. Such a phone could be usedin Japan, Europe, or the United States without modification.

Testing, testing…

The requirements of testing mixed-signal designs open “awhole new frontier,” according to David Yee, vice chair of thecomputer-aided design group of Semiconductor ResearchCorp., Durham, N.C., an organization that helps coordinate col-laborative research among universities andindustry. In fact, the cost per transistor of man-ufacturing test will soon exceed the cost of mak-ing the transistor—for some larger designs, italready has. In analog test, every transistor onthe chip needs to be tested for behavior andperformance, unlike digital testing, which onlyneeds to check that the transistors switch. Butcurrently, there are no good solutions to theAMS test problem.

For designs like phase-locked loops (PLLs),which keep certain input signals in sync withone another, current built-in self-test (BIST)structures will work fine. In other circuits,though, such measurements of performanceas speed, dynamic range, and resolution can-not be made using BIST.

One issue is that there are sometimes noaccess pins to the analog block on a system-on-chip design. Yet some connection must linkthe analog block to the outside world. How tosolve this problem is what drives GordonRoberts, an associate professor in the depart-ment of electrical and computer engineering atMcGill University in Montreal.

The way Roberts sees it, testing these tiny chips with hugemachines just is not the best way. The trend has been to movethe testers ever closer to the circuits on the chip. Even with cen-timeters between the circuits and the test equipment, degra-dation occurs in the measurement because of signal noisepicked up by the electrical leads that connect the tester to thechip under test. To reach the embedded analog blocks, saidRoberts, people are modifying the designs to bring signalsfrom the circuits under test to the boundary of the chip. Somedesigners use drivers, buffers, and test buses on the chip toconnect cores, embedded blocks of circuitry on system chips,to the outside world. But for Roberts, that’s not enough.

“The way I see the world,” said Roberts, “test instrumentsshould have the same functionality as the benchtop equip-ment, but be located on the chip. Miniaturize the measure-ment instruments and add them as plug-in test cores.”

For that kind of setup, the test cores would need to be

small and scale to new process technologies. They should alsobe synthesizable from a hardware design language, which iswhere EDA can play a role. Once analog synthesis is mature,said Roberts, test-core blocks will be possible. Essentially, thetest core would convert the analog signal to digital, and sendthat signal to a test pin on the boundary of the chip. With someimprovements in the technology used to probe the pins whilethe chips are fresh from fabrication and still on the wafer, testcould be made quite manageable.

Carnegie Mellon’s Rutenbar agrees. With analog synthesisin place, designers will also be able to generate test vectorsmore easily. But right now, inserting BIST or other test struc-tures is something analog designers avoid. “In analog, it’s sohard just to get the signal path done,” said Rutenbar, “theydon’t want to worry about putting test structures in.”

Seeing eye to eye

The relationship between semiconductor makers and theEDA vendors is sometimes a thorny one. Some designerssee the tools as immature, requiring them to create time-consuming work-arounds. Others, like National Semi-conductor’s Verhoeven, appreciate that EDA vendors allowusers to add functionality to their programs with extra scripts.Fortunately, the pure analog chips are coming along just fine with the relatively mature simulation and layoutediting tools.

Two things designers and EDA vendors do agree on is thatthere is always more room for automation and that tools needto be integrated into a more formal top-down design flow. But, said Cadence Design’s Chang, “The analog productivitygap isn’t a show-stopper. The industry adapts pretty well. Peo-ple work it out.” •

–Elizabeth A. Bretz & Linda Geppert, Editors

Software for editing a custom layout [above] is part of a larger

analog/mixed-signal design package from Cadence Design Systems.

While software can make the job easier, a layout engineer must still

“push polygons” to manually place the circuits and draw the electrical

connections between them.