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Contents:
Asynchronous/Ripple Counter
MOD Number
Counters < 2^N MOD Number
Decade Counter and BCD Counter
MOD 60 counter
Asynchronous Down Counter
Asynchronous Counter
Prepared By
Mohammed Abdul kader
Assistant Professor, EEE, IIUC
Propagation Delay in Ripple Counter
Synchronous/Parallel Counter
Presettable Counters
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 2
Asynchronous Counter/Ripple Counter 101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101
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In asynchronous counter each FF output drives the clock input of next FF. The types of
arrangement is called an asynchronous counter because the FFs don’t change state in exact
synchronism with the applied clock pulses. Only 1st FF responds to the input clock pulses,
other FF gets clock from the output of previous FF.
This type of counter is also often referred to as a ripple counter due to the way the FFs
respond one after another in a kind of rippling effect.
The term asynchronous counter and ripple counter used interchangeably.
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 3
4-bit asynchronous counter 101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101
010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010
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010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 4
MOD Number 101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101
010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010
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MOD number of a counter as defined as the number of states that the counter goes through
in each complete cycle before it recycles back to its starting state. The MOD number can
be increased simply by adding more FFs to the counter.
Where N is the number of flip-flop.
Frequency Division
In the basic counter each FF provides an output waveform that is exactly half the frequency of the
waveform at its CLK input.
In any counter, the signal at the output of the last FF (i.e. the MSB) will have a frequency equal to
the input clock frequency divided by MOD number of the counter.
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 5
Counters with MOD Number<𝟐𝑵 101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101
010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010
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Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 6
Decade Counters and BCD Counters 101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101
010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010
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The MOD-10 counter is also referred to as a decade counter. In fact, a decade counter is any that has
10 distinct states, no matter what the sequence. A decade counter as shown in fig, which counts in
sequence from 0000 (decimal 0) through 1001 (decimal 9), is also commonly called a BCD counter,
because it uses only the 10 BCD code groups 0000, 0001, ……, 1000 and 1001. To reiterate, any
MOD-10 counter is a decade counter and any decade counter that counts in binary from 0000 to
1001 is a BCD counter.
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 7
MOD-60 Counter 101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101
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Example: A MOD-60 counter was needed to divide the 60 Hz line frequency down to 1 Hz.
Construct an appropriate MOD-60 counter.
26 = 64, So we need six FFs to design a MOD-60 counter.
The counter is to be cleared when it reaches the count of 60 (111100). Thus, the output of
FFs Q5, Q4, Q3 and Q2 must be connected to the NAND fate. The output of flip-flop Q5
will have a frequency of 1Hz.
Solution:
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 8
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All of the counters we have looked at thus far have counted upward from zero, that is,
they were up counters.
It is relatively simple matter to construct asynchronous (ripple) down counters, which
will count downward from a maximum count to zero.
The sequence of a 3-bit down counter is given below.
Asynchronous Down Counter
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 9
Asynchronous Down Counter 101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101
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Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 10
Propagation Delay in ripple counter 101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101
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In a ripple counter, because of the inherent propagation delay (𝑡𝑝𝑑) of each FF, the second FF will not
respond until a time 𝑡𝑝𝑑 after the first FF receives an active clock transition. The third FF will not
respond until a time equal to 2 X 𝑡𝑝𝑑 after the clock transition and so on.
In general, we can say that Nth FF cannot change states until a time equal to N X 𝑡𝑝𝑑 after the clock
transition occurs.
Assuming, 𝑡𝑝𝑑=50 ns, input clock period
T=1000ns
Output of Flip-flop “A” toggles after 50
ns of the falling edge of clock, Similarly,
output of flip-flop “B” toggles after 100
ns and output of flip-flop “C” toggles
after 150 ns.
In this situation the counter does operate
properly in the sense that the FFs do
eventually get to their correct states
However situation worsens if the input
pulses are applied at a much higher
frequency.
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 11
Propagation Delay in ripple counter 101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101
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The waveform in fig show what happens if
the input pulses occur once every 100ns.
The condition C=1, B=A=0 (count of 100)
never appears, because the input frequency
is too high.
Problems such as this can be avoided if the
period between input pulses is made longer
than the total propagation delay of the
counter.
That for proper counter operation we need.
Where N is the number of FFs.
Stated in terms of input-clock frequency, the maximum frequency that can be used is given
by-
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 12
Propagation Delay in ripple counter 101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101
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Example: Suppose that a four-bit ripple counter is constructed using 74LS112 J-K flip-
flop. 74LS112 has low-to-high propagation delay 𝑡𝑃𝐿𝐻 = 16 𝑛𝑠 and high-to-low
propagation delay 𝑡𝑃𝐻𝐿 = 24 𝑛𝑠. Calculate 𝑓𝑚𝑎𝑥.
To calculate 𝑓𝑚𝑎𝑥, we will assume the “worst case”, that is, we will use 𝑡𝑝𝑑 = 𝑡𝑃𝐻𝐿 =
24 𝑛𝑠
Clearly, as the number of FFs in the counter increases, the total propagation delay
increases and 𝑓𝑚𝑎𝑥 decreases.
Thus asynchronous counters are not useful at very high frequencies, especially for large
number of bits.
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 13
Synchronous/Parallel Counter 101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101
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Synchronous/Parallel Counter
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 14
101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101
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Synchronous/Parallel Counter
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 15
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Synchronous down and up/down Counter
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 16
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Presettable Counters
Lecture materials on "Sequential Logic" By- Mohammed Abdul Kader, Assistant Professor, EEE, IIUC 17
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Note:
Read detail circuit operation from book.
Ref. Book:
Digital systems principle and application by Ronald J Tocci
