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Assembly Language Issues – Page 1CSCI 4717 – Computer Architecture
CSCI 4717/5717 Computer Architecture
Topic: Assembly Language Issues
Reading: Stallings, Sections 10.1 through 10.4
Assembly Language Issues – Page 2CSCI 4717 – Computer Architecture
Why are we doing this?• Much of the computer’s architecture/organization is hidden
from a HLL programmer• In the abstract sense, the programmer should not care what
the underlying architecture really is• The instruction set is the boundary where the computer
designer and the computer programmer can view the same machine
• Thus, an examination of the instruction set goes a long way to explaining the computer’s CPU itself
• This section investigates the design of the instruction set and the impact of the set on the design of the overall computer system
Assembly Language Issues – Page 3CSCI 4717 – Computer Architecture
Instruction set
• Everything that the CPU is capable of doing must be represented with an instruction, the collection of which makes up the instruction set
• Machine Code – is a binary code representing instruction set
• Usually represented by assembly codes
Assembly Language Issues – Page 4CSCI 4717 – Computer Architecture
Elements of a Machine Instruction
Each basic instruction must contain four pieces:
1. Operation code (Op code) – operation to perform
2. Source operand reference(s) – If sources are needed, where to find the data to operate on
3. Result operand reference – If there is a result, where should it be placed
4. Next Instruction Reference – When no explicit reference is made to where next
instruction is, next instruction immediately follows last instruction
– Address will be supplied if not next location in memory
Assembly Language Issues – Page 5CSCI 4717 – Computer Architecture
Elements of a Machine Instruction (continued)
Assembly Language Issues – Page 6CSCI 4717 – Computer Architecture
Locations of Operands
Operands can be in one of three areas
• Main or virtual memory – constants fall into this case as they are operand that immediately follows opcode
• CPU register
• I/O device – memory mapped works just like main or virtual memory
Assembly Language Issues – Page 7CSCI 4717 – Computer Architecture
Design of an Instruction Set
• An instruction set should be functionally complete – Permit the user to formulate any high-level data processing task
• Five categories of instructions1. Arithmetic operations
2. Logic operations
3. Data movement (internal to the system)
4. I/O (data movements between the computer and external devices)
5. Control operations
Assembly Language Issues – Page 8CSCI 4717 – Computer Architecture
How Many Instructions are Needed?
Instruction sets have been designed with
• Small numbers of instructions
• Hundreds of instructions
• Trend today is to use “enough” to get the job done well (more on this in the RISC/CISC discussions to come)
Assembly Language Issues – Page 9CSCI 4717 – Computer Architecture
How Many Instructions are Needed?
• Until the 1980s, the trend was to construct more and more complex instruction sets containing hundreds of instructions and variations
• Intent was to provide mechanisms to bridge the semantic gap, the difference in high and low level functioning of the computer
Assembly Language Issues – Page 10CSCI 4717 – Computer Architecture
Bridging the Semantic Gap
• Reconcile the views of the HLL programmer and the assembly level programmer
• Provide a diverse set of instructions in an attempt to match the programming style of HLL
• Permit the compiler to “bridge the gap” with a single instruction rather than synthesizing a series of instructions
• Did not always have the desired impact
Assembly Language Issues – Page 11CSCI 4717 – Computer Architecture
Attributes of a Good Instruction Set
• Wulff asserts that compiler writers might make the better architects because they have had to deal with poor architecture decisions
Assembly Language Issues – Page 12CSCI 4717 – Computer Architecture
Wulff’s attributes of a good instruction set to:
• Complete: be able to construct a machine-level program to evaluate any computable function
• Efficient: frequently performed functions should be done quickly with few instructions
• Regular and complete classes of instructions: provide “logical” set of operations
• Orthogonal: define instructions, data types, and addressing independently
• Additional attribute: Compatible: with existing H/W and S/W in a product line
Assembly Language Issues – Page 13CSCI 4717 – Computer Architecture
Addresses in an Instruction
• In a typical arithmetic or logical instruction, 3 references are required– 2 operands– a result
• These addresses can be explicitly given or implied by the instruction
Assembly Language Issues – Page 14CSCI 4717 – Computer Architecture
3 address instructions• Both operands and the destination for the result are
explicitly contained in the instruction word• Example: X = Y + Z• With memory speeds (due to caching) approaching
the speed of the processor, this gives a high degree of flexibility to the compiler
• Avoid the hassles of keeping items in the register set -- use memory as one large set of registers
• This format is rarely used due to the length of addresses themselves and the resulting length of the instruction words
Assembly Language Issues – Page 15CSCI 4717 – Computer Architecture
2 address instructions
• One of the addresses is used to specify both an operand and the result location
• Example: X = X + Y
• Very common in instruction sets
Assembly Language Issues – Page 16CSCI 4717 – Computer Architecture
1 address instructions
• Two addresses are implied in the instruction
• Traditional accumulator-based operations
• Example: Acc = Acc + X
Assembly Language Issues – Page 17CSCI 4717 – Computer Architecture
0 address instructions
• All addresses are implied, as in register-based operations – e.g., TBA (transfer register B to A)
• Stack-based operations• All operations are based on the use of a stack in
memory to store operands• Interact with the stack using push and pop
operations
Assembly Language Issues – Page 18CSCI 4717 – Computer Architecture
Trade off Resulting from Fewer Addresses
Fewer addresses in the instruction results in:
• More primitive instructions
• Less complex CPU
• Instructions with shorter length – fit more into memory
• More total instructions in a program
• Longer, more complex programs
• Faster fetch/execution of instructions
• Longer execution times
Assembly Language Issues – Page 19CSCI 4717 – Computer Architecture
Example: 3 Addresses
Y = (A-B) / (C+D*E)
SUB Y,A,B
MUL T,D,E
ADD T,T,C
DIV Y,Y,T
Assembly Language Issues – Page 20CSCI 4717 – Computer Architecture
Example: 2 address
Y = (A-B) / (C+D*E)
MOV Y,A
SUB Y,B
MOV T,D
MUL T,E
ADD T,C
DIV Y,T
Assembly Language Issues – Page 21CSCI 4717 – Computer Architecture
Example: 1 address
Y = (A-B) / (C+D*E)
LOAD D
MUL E
ADD C
STORE Y
LOAD A
SUB B
DIV Y
STORE Y
Assembly Language Issues – Page 22CSCI 4717 – Computer Architecture
Example: 0 address – Convert to postfix (reverse Polish) notation:
PUSH A
PUSH B
SUB
PUSH C
PUSH D
PUSH E
MUL
ADD
DIV
POP Y
Y = (A-B) / (C+D*E)
becomes
Y = AB–CDE*+/
Assembly Language Issues – Page 23CSCI 4717 – Computer Architecture
Design Decisions
• Operation repertoire– How many ops?– What can they do?– How complex are they?
• Data types – various types of operations and how they are performed
• Instruction formats– Length of op code field– Number of addresses
Assembly Language Issues – Page 24CSCI 4717 – Computer Architecture
Design Decisions (continued)
• Registers– Number of CPU registers available– Which operations can be performed on which
registers?
• Addressing modes – methods by which operands can be referenced
• RISC v CISC
Assembly Language Issues – Page 25CSCI 4717 – Computer Architecture
Types of Operands
• Addresses• Numbers
– Integer or fixed point– Floating point– BCD
• Characters– ASCII (7 bit)– EBCDIC (8 but)
• Logical Data – Bits or flags
Assembly Language Issues – Page 26CSCI 4717 – Computer Architecture
Pentium Data Types
Assembly Language Issues – Page 27CSCI 4717 – Computer Architecture
Pentium Numeric Data Formats
Assembly Language Issues – Page 28CSCI 4717 – Computer Architecture
Pentium Numeric Data Formats (continued)
Assembly Language Issues – Page 29CSCI 4717 – Computer Architecture
Endian Wars
• Architects must specify how multi-word data is stored (its byte ordering) in memory and registers
• There are two ways to do this– Big endian– Little endian
Assembly Language Issues – Page 30CSCI 4717 – Computer Architecture
Endian Wars (continued)Consider the hex value $12345678 and how it is stored in memory starting at address $100
Big endian stores most significant byte in the lowest address:
100 12
101 34
102 56
103 78
Little endian stores the words in reverse:
100 78
101 56
102 34
103 12
Assembly Language Issues – Page 31CSCI 4717 – Computer Architecture
Endianness Observations
• In storing several data items into a memory segment, each item will have the same address (big or little endian does not change this)
• Endianness does not affect the ordering of items in a data structure
• No general consensus as to which is “best”• Little endian: Intel X86, Pentium, VAX• Big endian: S370, Motorola 680x0, RISCs
Assembly Language Issues – Page 32CSCI 4717 – Computer Architecture
Endianness Observations (continued)
• No real advantage in one style over the other – Decision is based on supporting previous machines in many cases
• Biggest problems:– Data transfers between machines of different
endianness– Must go though a format conversion process– Manipulation of individual bytes (bits) of
multibyte word
Assembly Language Issues – Page 33CSCI 4717 – Computer Architecture
Addressing Modes
• Once we have determined the number of addresses contained in an instruction, the manner in which each address field specifies memory location must be determined
• Want the ability to reference a large range of address locations
• Tradeoff between– Addressing range and flexibility– Complexity of the address calculation
Assembly Language Issues – Page 34CSCI 4717 – Computer Architecture
Types of Addressing Modes
• Implied – No address needed
• Immediate Mode– The operand is contained within the
instruction itself– Data is a constant at run time– No additional memory references are required
after the fetch of the instruction itself– Size of the operand (thus its range of values)
is limited
Assembly Language Issues – Page 35CSCI 4717 – Computer Architecture
Types of Addressing Modes (continued)
• Direct mode– The address field of the instruction contains the
effective address of the operand– No calculations are required– One additional memory access is required to fetch the
operand– Address range limited by the width of the field that
contains the address reference– Address is a constant at run time but data itself can
be changed during program execution– Some machines use variations of direct addressing:
direct and extended addressing on the 68HC11 -- 8 and 16-bit addresses
Assembly Language Issues – Page 36CSCI 4717 – Computer Architecture
Types of Addressing Modes (continued)
• Indirect addressing– The address field in the instruction specifies a
memory location which contains the address of the data
– Two memory accesses are required• The first to fetch the effective address• The second to fetch the operand itself
– Range of effective addresses is equal to 2n, where n is the width of the memory data word
– Number of locations that can be used to hold the effective address is constrained to 2k, where k is the width of the instruction’s address field
Assembly Language Issues – Page 37CSCI 4717 – Computer Architecture
Types of Addressing Modes (continued)
• Register-Based Addressing Modes– Register addressing: like direct, but address
field specifies a register location– Register indirect: like indirect, but address
field specifies a register that contains the effective address
– Faster access to data, smaller address fields in the instruction word
Assembly Language Issues – Page 38CSCI 4717 – Computer Architecture
Displacement or Address Relative Addressing
• Two address fields in the instruction are used– One is an explicit address reference– The other is a register reference– EA = A + (R)
• Relative addressing– A is added to the program counter contents to
cause a branch operation in fetching the next instruction
Assembly Language Issues – Page 39CSCI 4717 – Computer Architecture
Displacement or Address Relative Addressing (continued)
• Base-register addressing– A is a displacement added to the contents of
the referenced “base register” to form the EA– Used by programmers and O/S to identify the
start of user areas, segments, etc. and provide accesses within them
Assembly Language Issues – Page 40CSCI 4717 – Computer Architecture
Displacement or Address Relative Addressing (continued)
• Indexing– Essentially the same impact as base addressing– Sometimes this method utilizes autoindexing
• Postindexing – increment index register after addressing performed
• Preindexing – increment index register before addressing performed
– Our book says that the A field is a memory address and the referenced register contains the displacement value that is added to A
Assembly Language Issues – Page 41CSCI 4717 – Computer Architecture
Types of Addressing Modes (continued)
• Stack Addressing– Indirect addressing with CPU registers– Could be considered implied addressing
Assembly Language Issues – Page 42CSCI 4717 – Computer Architecture
PowerPC Data Types
• 32-bit and 64-bit versions• Some instructions need operand aligned on 32
bit boundary
• Supports both bid-endian and little-endian (can switch at run time)
• Can handle data at the 8 (byte), 16 (halfword), 32 (word) and 64 (doubleword) bit lengths
Assembly Language Issues – Page 43CSCI 4717 – Computer Architecture
PowerPC Data Types (continued)
• Unsigned byte– Used for logical or integer arithmetic– Used in regular registers by filling rest of register with
zeros (zero extending)
• Unsigned halfword– Same as unsigned byte except 16 bits
• Signed halfword– Arithmetic operations– Sign extending to full register length
Assembly Language Issues – Page 44CSCI 4717 – Computer Architecture
PowerPC Data Types (continued)
• Unsigned word– Same as unsigned byte except 32 bits– Also used as address pointer
• Signed word– Same as signed halfword except 32 bits
• Unsigned doubleword– Used as address pointer
• Byte string – From 0 to 128 bytes in length
Assembly Language Issues – Page 45CSCI 4717 – Computer Architecture
PowerPC Data Types (continued)
• Floating point – IEEE 754– Single precision: +1.F × 2(E – 127)
– Double precision: +1.F × 2(E – 1023)
Assembly Language Issues – Page 46CSCI 4717 – Computer Architecture
Types of Operations
Everyone should have plenty of experience with these. If not, read section 10.4– Data transfer– Arithmetic– Logical– Transfer of control– I/O– Conversion (similar to arithmetic and logical)– System control